source: mainline/arch/amd64/src/fpu_context.c@ 9c1ecf9

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 9c1ecf9 was f76fed4, checked in by Ondrej Palkovsky <ondrap@…>, 19 years ago

Added lazy fpu context allocation.

  • threads that don't use fpu, don't get allocated fpu context
  • fpu context alignment on AMD64 nicely disappeared
  • Property mode set to 100644
File size: 1.9 KB
Line 
1/*
2 * Copyright (C) 2005 Jakub Vana
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 */
29
30#include <fpu_context.h>
31#include <arch.h>
32#include <cpu.h>
33
34/** Save FPU (mmx, sse) context using fxsave instruction */
35void fpu_context_save(fpu_context_t *fctx)
36{
37 __asm__ volatile (
38 "fxsave %0"
39 : "=m"(*fctx)
40 );
41}
42
43/** Restore FPU (mmx,sse) context using fxrstor instruction */
44void fpu_context_restore(fpu_context_t *fctx)
45{
46 __asm__ volatile (
47 "fxrstor %0"
48 : "=m"(*fctx)
49 );
50}
51
52void fpu_init()
53{
54 /* TODO: Zero all SSE, MMX etc. registers */
55 __asm__ volatile (
56 "fninit;"
57 );
58}
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