[e3b9572] | 1 | #
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| 2 | # Copyright (C) 2005 Ondrej Palkovsky
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| 3 | # All rights reserved.
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| 4 | #
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| 5 | # Redistribution and use in source and binary forms, with or without
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| 6 | # modification, are permitted provided that the following conditions
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| 7 | # are met:
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| 8 | #
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| 9 | # - Redistributions of source code must retain the above copyright
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| 10 | # notice, this list of conditions and the following disclaimer.
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| 11 | # - Redistributions in binary form must reproduce the above copyright
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| 12 | # notice, this list of conditions and the following disclaimer in the
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| 13 | # documentation and/or other materials provided with the distribution.
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| 14 | # - The name of the author may not be used to endorse or promote products
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| 15 | # derived from this software without specific prior written permission.
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| 16 | #
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| 17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | #
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| 28 |
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| 29 |
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| 30 | # Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error word
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| 31 | # and 1 means interrupt with error word
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| 32 |
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| 33 |
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| 34 | #define ERROR_WORD_INTERRUPT_LIST 0x00027D00
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| 35 |
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| 36 | #include <arch/pm.h>
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[49a39c2] | 37 | #include <arch/context_offset.h>
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[fa2d382] | 38 | #include <arch/mm/page.h>
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[e3b9572] | 39 |
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| 40 | .text
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| 41 | .global interrupt_handlers
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[dd4d6b0] | 42 | .global syscall_entry
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[e3b9572] | 43 | .global panic_printf
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| 44 |
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| 45 | panic_printf:
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| 46 | movq $halt, (%rsp)
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| 47 | jmp printf
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| 48 |
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[36b209a] | 49 | .global memcpy
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| 50 | memcpy:
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| 51 | jmp _memcpy
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| 52 |
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| 53 | .global cpuid
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[7df54df] | 54 | .global has_cpuid
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| 55 | .global rdtsc
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[89344d85] | 56 | .global read_efer_flag
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| 57 | .global set_efer_flag
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| 58 |
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[7df54df] | 59 | ## Determine CPUID support
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| 60 | #
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| 61 | # Return 0 in EAX if CPUID is not support, 1 if supported.
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| 62 | #
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| 63 | has_cpuid:
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| 64 | pushfq # store flags
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| 65 | popq %rax # read flags
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[d6dcdd2e] | 66 | movq %rax,%rdx # copy flags
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| 67 | btcl $21,%edx # swap the ID bit
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| 68 | pushq %rdx
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[7df54df] | 69 | popfq # propagate the change into flags
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| 70 | pushfq
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[d6dcdd2e] | 71 | popq %rdx # read flags
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[7df54df] | 72 | andl $(1<<21),%eax # interested only in ID bit
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[d6dcdd2e] | 73 | andl $(1<<21),%edx
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| 74 | xorl %edx,%eax # 0 if not supported, 1 if supported
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[7df54df] | 75 | ret
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| 76 |
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[89344d85] | 77 | cpuid:
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| 78 | movq %rbx, %r10 # we have to preserve rbx across function calls
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| 79 |
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| 80 | movl %edi,%eax # load the command into %eax
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| 81 |
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| 82 | cpuid
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| 83 | movl %eax,0(%rsi)
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| 84 | movl %ebx,4(%rsi)
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| 85 | movl %ecx,8(%rsi)
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| 86 | movl %edx,12(%rsi)
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| 87 |
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| 88 | movq %r10, %rbx
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| 89 | ret
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[7df54df] | 90 |
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| 91 | rdtsc:
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| 92 | xorq %rax,%rax
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| 93 | rdtsc
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| 94 | ret
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[89344d85] | 95 |
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| 96 | set_efer_flag:
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| 97 | movq $0xc0000080, %rcx
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| 98 | rdmsr
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| 99 | btsl %edi, %eax
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| 100 | wrmsr
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| 101 | ret
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[7df54df] | 102 |
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[89344d85] | 103 | read_efer_flag:
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| 104 | movq $0xc0000080, %rcx
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| 105 | rdmsr
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| 106 | ret
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[7df54df] | 107 |
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[e3b9572] | 108 | # Push all general purpose registers on stack except %rbp, %rsp
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[49a39c2] | 109 | .macro save_all_gpr
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| 110 | movq %rbp, IOFFSET_RBP(%rsp)
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| 111 | movq %rax, IOFFSET_RAX(%rsp)
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| 112 | movq %rbx, IOFFSET_RBX(%rsp)
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| 113 | movq %rcx, IOFFSET_RCX(%rsp)
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| 114 | movq %rdx, IOFFSET_RDX(%rsp)
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| 115 | movq %rsi, IOFFSET_RSI(%rsp)
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| 116 | movq %rdi, IOFFSET_RDI(%rsp)
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| 117 | movq %r8, IOFFSET_R8(%rsp)
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| 118 | movq %r9, IOFFSET_R9(%rsp)
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| 119 | movq %r10, IOFFSET_R10(%rsp)
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| 120 | movq %r11, IOFFSET_R11(%rsp)
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| 121 | movq %r12, IOFFSET_R12(%rsp)
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| 122 | movq %r13, IOFFSET_R13(%rsp)
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| 123 | movq %r14, IOFFSET_R14(%rsp)
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| 124 | movq %r15, IOFFSET_R15(%rsp)
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[e3b9572] | 125 | .endm
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| 126 |
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[49a39c2] | 127 | .macro restore_all_gpr
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| 128 | movq IOFFSET_RBP(%rsp), %rbp
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| 129 | movq IOFFSET_RAX(%rsp), %rax
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| 130 | movq IOFFSET_RBX(%rsp), %rbx
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| 131 | movq IOFFSET_RCX(%rsp), %rcx
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| 132 | movq IOFFSET_RDX(%rsp), %rdx
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| 133 | movq IOFFSET_RSI(%rsp), %rsi
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| 134 | movq IOFFSET_RDI(%rsp), %rdi
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| 135 | movq IOFFSET_R8(%rsp), %r8
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| 136 | movq IOFFSET_R9(%rsp), %r9
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| 137 | movq IOFFSET_R10(%rsp), %r10
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| 138 | movq IOFFSET_R11(%rsp), %r11
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| 139 | movq IOFFSET_R12(%rsp), %r12
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| 140 | movq IOFFSET_R13(%rsp), %r13
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| 141 | movq IOFFSET_R14(%rsp), %r14
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| 142 | movq IOFFSET_R15(%rsp), %r15
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[e3b9572] | 143 | .endm
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| 144 |
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| 145 | ## Declare interrupt handlers
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| 146 | #
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| 147 | # Declare interrupt handlers for n interrupt
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| 148 | # vectors starting at vector i.
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| 149 | #
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| 150 | # The handlers setup data segment registers
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[fcfac420] | 151 | # and call exc_dispatch().
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[e3b9572] | 152 | #
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| 153 | .macro handler i n
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[49a39c2] | 154 | subq $IREGISTER_SPACE, %rsp
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| 155 | save_all_gpr
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[e3b9572] | 156 |
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| 157 | movq $(\i),%rdi # %rdi - first parameter
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[49a39c2] | 158 | movq %rsp, %rsi # %rsi - pointer to interrupt_context
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[fcfac420] | 159 | call exc_dispatch # exc_dispatch(i, stack)
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[e3b9572] | 160 |
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| 161 | # Test if this is interrupt with error word or not
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| 162 | mov $\i,%cl;
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| 163 | movl $1,%eax;
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| 164 | test $0xe0,%cl;
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| 165 | jnz 0f;
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| 166 | and $0x1f,%cl;
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| 167 | shl %cl,%eax;
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| 168 | and $ERROR_WORD_INTERRUPT_LIST,%eax;
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| 169 | jz 0f;
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| 170 |
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| 171 |
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| 172 | # Return with error word
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[49a39c2] | 173 | restore_all_gpr
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| 174 | # $8 = Skip error word
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| 175 | addq $IREGISTER_SPACE + 0x8, %rsp
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[e3b9572] | 176 | iretq
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| 177 |
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| 178 | 0:
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| 179 | # Return with no error word
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[49a39c2] | 180 | restore_all_gpr
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| 181 | addq $IREGISTER_SPACE, %rsp
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[e3b9572] | 182 | iretq
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| 183 |
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| 184 | .if (\n-\i)-1
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| 185 | handler "(\i+1)",\n
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| 186 | .endif
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| 187 | .endm
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| 188 |
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| 189 | interrupt_handlers:
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| 190 | h_start:
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| 191 | handler 0 IDT_ITEMS
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| 192 | h_end:
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[dd4d6b0] | 193 |
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[e3b9572] | 194 |
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[dd4d6b0] | 195 | syscall_entry:
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[37b451f7] | 196 | # Switch to hidden gs
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| 197 | swapgs
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[fa2d382] | 198 | # %gs:0 now points to pointer to stack page
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| 199 | mov %gs:0, %r10 # We have a ptr to stack page in r10
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| 200 | addq $PAGE_SIZE-16, %r10 # We need some space to store old %sp
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[37b451f7] | 201 |
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| 202 | movq %rsp, 0(%r10) # Save old stack pointer to stack
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| 203 | movq %r10, %rsp # Change to new stack
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| 204 | pushq %rcx # Return address
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| 205 | pushq %r11 # Save flags
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| 206 |
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| 207 | # Switch back to remain consistent
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| 208 | swapgs
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| 209 |
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[6d9c49a] | 210 | sti
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[37b451f7] | 211 | movq %r9, %rcx # Exchange last parameter as a third
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[dd4d6b0] | 212 | call syscall_handler
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[6d9c49a] | 213 | cli # We will be touching stack pointer
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| 214 |
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[37b451f7] | 215 | popq %r11
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| 216 | popq %rcx
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| 217 | movq 0(%rsp), %rsp
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| 218 | sysretq
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[dd4d6b0] | 219 |
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[e3b9572] | 220 | .data
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| 221 | .global interrupt_handler_size
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| 222 |
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[42744880] | 223 | interrupt_handler_size: .quad (h_end-h_start)/IDT_ITEMS
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