source: mainline/arch/amd64/include/mm/page.h@ 6c6a19e6

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 6c6a19e6 was 5fceec7, checked in by Ondrej Palkovsky <ondrap@…>, 20 years ago

Cleanup of amd64 code.

  • Property mode set to 100644
File size: 6.3 KB
RevLine 
[1141c1a]1/*
[01e48c1]2 * Copyright (C) 2005 Ondrej Palkovsky
[1141c1a]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[93165be]29/** Paging on AMD64
30 *
31 * The space is divided in positive numbers - userspace and
32 * negative numbers - kernel space. The 'negative' space starting
33 * with 0xffff800000000000 and ending with 0xffffffff80000000
34 * (-2GB) is identically mapped physical memory. The area
35 * (0xffffffff80000000 ... 0xffffffffffffffff is again identically
36 * mapped first 2GB.
37 *
38 * ATTENTION - PA2KA(KA2PA(x)) != x if 'x' is in kernel
39 */
40
[1141c1a]41#ifndef __amd64_PAGE_H__
42#define __amd64_PAGE_H__
43
[fa2d382]44#include <arch/mm/frame.h>
45
[d1f8a87]46#define PAGE_WIDTH FRAME_WIDTH
47#define PAGE_SIZE FRAME_SIZE
48
49#ifdef KERNEL
50
[8fc0d455]51#ifndef __ASM__
52# include <mm/page.h>
53# include <arch/types.h>
54#endif
[1141c1a]55
[8fc0d455]56#ifndef __ASM__
[93165be]57static inline __address ka2pa(__address x)
58{
59 if (x > 0xffffffff80000000)
60 return x - 0xffffffff80000000;
61 else
62 return x - 0xffff800000000000;
63}
64# define KA2PA(x) ka2pa((__address)x)
65# define PA2KA_CODE(x) (((__address) (x)) + 0xffffffff80000000)
[5fceec7]66# define PA2KA(x) (((__address) (x)) + 0xffff800000000000)
[8fc0d455]67#else
[4f1475d4]68# define KA2PA(x) ((x) - 0xffffffff80000000)
69# define PA2KA(x) ((x) + 0xffffffff80000000)
[8fc0d455]70#endif
71
[ecbdc724]72#define PTL0_ENTRIES_ARCH 512
73#define PTL1_ENTRIES_ARCH 512
74#define PTL2_ENTRIES_ARCH 512
75#define PTL3_ENTRIES_ARCH 512
76
[db3341e]77#define PTL0_INDEX_ARCH(vaddr) (((vaddr)>>39)&0x1ff)
78#define PTL1_INDEX_ARCH(vaddr) (((vaddr)>>30)&0x1ff)
79#define PTL2_INDEX_ARCH(vaddr) (((vaddr)>>21)&0x1ff)
80#define PTL3_INDEX_ARCH(vaddr) (((vaddr)>>12)&0x1ff)
[1141c1a]81
[db3341e]82#define GET_PTL1_ADDRESS_ARCH(ptl0, i) ((pte_t *) ((((__u64) ((pte_t *)(ptl0))[(i)].addr_12_31)<<12) | (((__u64) ((pte_t *)(ptl0))[(i)].addr_32_51)<<32 )))
83#define GET_PTL2_ADDRESS_ARCH(ptl1, i) ((pte_t *) ((((__u64) ((pte_t *)(ptl1))[(i)].addr_12_31)<<12) | (((__u64) ((pte_t *)(ptl1))[(i)].addr_32_51)<<32 )))
84#define GET_PTL3_ADDRESS_ARCH(ptl2, i) ((pte_t *) ((((__u64) ((pte_t *)(ptl2))[(i)].addr_12_31)<<12) | (((__u64) ((pte_t *)(ptl2))[(i)].addr_32_51)<<32 )))
85#define GET_FRAME_ADDRESS_ARCH(ptl3, i) ((__address *) ((((__u64) ((pte_t *)(ptl3))[(i)].addr_12_31)<<12) | (((__u64) ((pte_t *)(ptl3))[(i)].addr_32_51)<<32 )))
[1141c1a]86
[db3341e]87#define SET_PTL0_ADDRESS_ARCH(ptl0) (write_cr3((__address) (ptl0)))
88#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) set_pt_addr((pte_t *)(ptl0), (index_t)(i), a)
89#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) set_pt_addr((pte_t *)(ptl1), (index_t)(i), a)
90#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) set_pt_addr((pte_t *)(ptl2), (index_t)(i), a)
91#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) set_pt_addr((pte_t *)(ptl3), (index_t)(i), a)
[1141c1a]92
[db3341e]93#define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_flags((pte_t *)(ptl0), (index_t)(i))
94#define GET_PTL2_FLAGS_ARCH(ptl1, i) get_pt_flags((pte_t *)(ptl1), (index_t)(i))
95#define GET_PTL3_FLAGS_ARCH(ptl2, i) get_pt_flags((pte_t *)(ptl2), (index_t)(i))
96#define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_flags((pte_t *)(ptl3), (index_t)(i))
[1141c1a]97
[db3341e]98#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_flags((pte_t *)(ptl0), (index_t)(i), (x))
99#define SET_PTL2_FLAGS_ARCH(ptl1, i, x) set_pt_flags((pte_t *)(ptl1), (index_t)(i), (x))
100#define SET_PTL3_FLAGS_ARCH(ptl2, i, x) set_pt_flags((pte_t *)(ptl2), (index_t)(i), (x))
101#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_flags((pte_t *)(ptl3), (index_t)(i), (x))
[1141c1a]102
[ecbdc724]103#define PTE_VALID_ARCH(p) (*((__u64 *) (p)) != 0)
[d3e7ff4]104#define PTE_PRESENT_ARCH(p) ((p)->present != 0)
105#define PTE_GET_FRAME_ARCH(p) ((((__address)(p)->addr_12_31)<<12) | ((__address)(p)->addr_32_51<<32))
[ecbdc724]106
[8fc0d455]107#ifndef __ASM__
[db3341e]108
[0882a9a]109/** Page Table Entry. */
[db3341e]110struct page_specifier {
111 unsigned present : 1;
112 unsigned writeable : 1;
113 unsigned uaccessible : 1;
114 unsigned page_write_through : 1;
115 unsigned page_cache_disable : 1;
116 unsigned accessed : 1;
117 unsigned dirty : 1;
118 unsigned unused: 1;
119 unsigned global : 1;
[0882a9a]120 unsigned soft_valid : 1; /**< Valid content even if present bit is cleared. */
121 unsigned avl : 2;
[db3341e]122 unsigned addr_12_31 : 30;
123 unsigned addr_32_51 : 21;
124 unsigned no_execute : 1;
125} __attribute__ ((packed));
126
127static inline int get_pt_flags(pte_t *pt, index_t i)
128{
129 pte_t *p = &pt[i];
130
131 return (
132 (!p->page_cache_disable)<<PAGE_CACHEABLE_SHIFT |
133 (!p->present)<<PAGE_PRESENT_SHIFT |
134 p->uaccessible<<PAGE_USER_SHIFT |
135 1<<PAGE_READ_SHIFT |
136 p->writeable<<PAGE_WRITE_SHIFT |
[bfb87df]137 (!p->no_execute)<<PAGE_EXEC_SHIFT |
138 p->global<<PAGE_GLOBAL_SHIFT
[db3341e]139 );
140}
141
142static inline void set_pt_addr(pte_t *pt, index_t i, __address a)
143{
144 pte_t *p = &pt[i];
145
146 p->addr_12_31 = (a >> 12) & 0xfffff;
147 p->addr_32_51 = a >> 32;
148}
149
150static inline void set_pt_flags(pte_t *pt, index_t i, int flags)
151{
152 pte_t *p = &pt[i];
153
154 p->page_cache_disable = !(flags & PAGE_CACHEABLE);
155 p->present = !(flags & PAGE_NOT_PRESENT);
156 p->uaccessible = (flags & PAGE_USER) != 0;
157 p->writeable = (flags & PAGE_WRITE) != 0;
158 p->no_execute = (flags & PAGE_EXEC) == 0;
[bfb87df]159 p->global = (flags & PAGE_GLOBAL) != 0;
[0882a9a]160
161 /*
162 * Ensure that there is at least one bit set even if the present bit is cleared.
163 */
164 p->soft_valid = 1;
[db3341e]165}
166
[1141c1a]167extern void page_arch_init(void);
168
[d1f8a87]169#endif /* __ASM__ */
170
171#endif /* KERNEL */
[1141c1a]172
173#endif
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