source: mainline/arch/amd64/include/cpu.h@ 9fa16b20

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 9fa16b20 was 281b607, checked in by Ondrej Palkovsky <ondrap@…>, 19 years ago

Added basic kernel infrastructure for ThreadLocalStorage(TLS) for
ia32(complete),amd64(complete),mips32(missing emulation of rdhwr instruction).

  • Property mode set to 100644
File size: 2.2 KB
Line 
1/*
2 * Copyright (C) 2001-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __amd64_CPU_H__
30#define __amd64_CPU_H__
31
32#define RFLAGS_RF (1 << 16)
33
34#define EFER_MSR_NUM 0xc0000080
35#define AMD_SCE_FLAG 0
36#define AMD_LME_FLAG 8
37#define AMD_LMA_FLAG 10
38#define AMD_FFXSR_FLAG 14
39#define AMD_NXE_FLAG 11
40
41/* MSR registers */
42#define AMD_MSR_STAR 0xc0000081
43#define AMD_MSR_LSTAR 0xc0000082
44#define AMD_MSR_SFMASK 0xc0000084
45#define AMD_MSR_FS 0xc0000100
46#define AMD_MSR_GS 0xc0000101
47
48#ifndef __ASM__
49
50#include <typedefs.h>
51#include <arch/pm.h>
52
53struct cpu_arch {
54 int vendor;
55 int family;
56 int model;
57 int stepping;
58 struct tss *tss;
59};
60
61struct star_msr {
62
63};
64
65struct lstar_msr {
66
67};
68
69extern void set_efer_flag(int flag);
70extern __u64 read_efer_flag(void);
71void cpu_setup_fpu(void);
72
73#endif /* __ASM__ */
74
75#endif
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