source: mainline/arch/amd64/include/cpu.h@ 0b917dd

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 0b917dd was 2382d09, checked in by Jakub Jermar <jakub@…>, 19 years ago

Improve SYS_IOSPACE_ENABLE support.
The general protection fault handler now contains
code to service early I/O Permission bitmap faults.

  • Property mode set to 100644
File size: 2.3 KB
Line 
1/*
2 * Copyright (C) 2001-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __amd64_CPU_H__
30#define __amd64_CPU_H__
31
32#define RFLAGS_IF (1 << 9)
33#define RFLAGS_RF (1 << 16)
34
35#define EFER_MSR_NUM 0xc0000080
36#define AMD_SCE_FLAG 0
37#define AMD_LME_FLAG 8
38#define AMD_LMA_FLAG 10
39#define AMD_FFXSR_FLAG 14
40#define AMD_NXE_FLAG 11
41
42/* MSR registers */
43#define AMD_MSR_STAR 0xc0000081
44#define AMD_MSR_LSTAR 0xc0000082
45#define AMD_MSR_SFMASK 0xc0000084
46#define AMD_MSR_FS 0xc0000100
47#define AMD_MSR_GS 0xc0000101
48
49#ifndef __ASM__
50
51#include <typedefs.h>
52#include <arch/pm.h>
53
54struct cpu_arch {
55 int vendor;
56 int family;
57 int model;
58 int stepping;
59 struct tss *tss;
60
61 count_t iomapver_copy; /** Copy of TASK's I/O Permission bitmap generation count. */
62};
63
64struct star_msr {
65
66};
67
68struct lstar_msr {
69
70};
71
72extern void set_efer_flag(int flag);
73extern __u64 read_efer_flag(void);
74void cpu_setup_fpu(void);
75
76#endif /* __ASM__ */
77
78#endif
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