source: mainline/arch/amd64/include/asm.h@ e515167d

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since e515167d was e515167d, checked in by Ondrej Palkovsky <ondrap@…>, 20 years ago

Added basic FPU context (not working).
Added CPU utilities from ia32
Fixed bug in vm.c that wanted PTL to be mapped in bottom memory.

  • Property mode set to 100644
File size: 3.8 KB
Line 
1/*
2 * Copyright (C) 2005 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __amd64_ASM_H__
30#define __amd64_ASM_H__
31
32#include <arch/types.h>
33#include <config.h>
34
35
36void asm_delay_loop(__u32 t);
37void asm_fake_loop(__u32 t);
38
39/** Return base address of current stack.
40 *
41 * Return the base address of the current stack.
42 * The stack is assumed to be STACK_SIZE bytes long.
43 * The stack must start on page boundary.
44 */
45static inline __address get_stack_base(void)
46{
47 __address v;
48
49 __asm__ volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((__u64)STACK_SIZE-1)));
50
51 return v;
52}
53
54static inline void cpu_sleep(void) { __asm__ volatile ("hlt"); };
55static inline void cpu_halt(void) { __asm__ volatile ("hlt"); };
56
57
58static inline __u8 inb(__u16 port)
59{
60 __u8 out;
61
62 __asm__ volatile (
63 "mov %1, %%dx;"
64 "inb %%dx,%%al;"
65 "mov %%al, %0;"
66 :"=m"(out)
67 :"m"(port)
68 :"%rdx","%rax"
69 );
70 return out;
71}
72
73static inline __u8 outb(__u16 port,__u8 b)
74{
75 __asm__ volatile (
76 "mov %0,%%dx;"
77 "mov %1,%%al;"
78 "outb %%al,%%dx;"
79 :
80 :"m"( port), "m" (b)
81 :"%rdx","%rax"
82 );
83}
84
85/** Set priority level low
86 *
87 * Enable interrupts and return previous
88 * value of EFLAGS.
89 */
90static inline pri_t cpu_priority_low(void) {
91 pri_t v;
92 __asm__ volatile (
93 "pushfq\n"
94 "popq %0\n"
95 "sti\n"
96 : "=r" (v)
97 );
98 return v;
99}
100
101/** Set priority level high
102 *
103 * Disable interrupts and return previous
104 * value of EFLAGS.
105 */
106static inline pri_t cpu_priority_high(void) {
107 pri_t v;
108 __asm__ volatile (
109 "pushfq\n"
110 "popq %0\n"
111 "cli\n"
112 : "=r" (v)
113 );
114 return v;
115}
116
117/** Restore priority level
118 *
119 * Restore EFLAGS.
120 */
121static inline void cpu_priority_restore(pri_t pri) {
122 __asm__ volatile (
123 "pushq %0\n"
124 "popfq\n"
125 : : "r" (pri)
126 );
127}
128
129/** Return raw priority level
130 *
131 * Return EFLAFS.
132 */
133static inline pri_t cpu_priority_read(void) {
134 pri_t v;
135 __asm__ volatile (
136 "pushfq\n"
137 "popq %0\n"
138 : "=r" (v)
139 );
140 return v;
141}
142
143/** Read CR2
144 *
145 * Return value in CR2
146 *
147 * @return Value read.
148 */
149static inline __u64 read_cr2(void) { __u64 v; __asm__ volatile ("movq %%cr2,%0" : "=r" (v)); return v; }
150
151/** Write CR3
152 *
153 * Write value to CR3.
154 *
155 * @param v Value to be written.
156 */
157static inline void write_cr3(__u64 v) { __asm__ volatile ("movq %0,%%cr3\n" : : "r" (v)); }
158
159/** Read CR3
160 *
161 * Return value in CR3
162 *
163 * @return Value read.
164 */
165static inline __u64 read_cr3(void) { __u64 v; __asm__ volatile ("movq %%cr3,%0" : "=r" (v)); return v; }
166
167
168extern size_t interrupt_handler_size;
169extern void interrupt_handlers(void);
170
171#endif
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