00001 /* 00002 * Copyright (C) 2005 Martin Decky 00003 * All rights reserved. 00004 * 00005 * Redistribution and use in source and binary forms, with or without 00006 * modification, are permitted provided that the following conditions 00007 * are met: 00008 * 00009 * - Redistributions of source code must retain the above copyright 00010 * notice, this list of conditions and the following disclaimer. 00011 * - Redistributions in binary form must reproduce the above copyright 00012 * notice, this list of conditions and the following disclaimer in the 00013 * documentation and/or other materials provided with the distribution. 00014 * - The name of the author may not be used to endorse or promote products 00015 * derived from this software without specific prior written permission. 00016 * 00017 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 00018 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 00019 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 00020 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 00021 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 00022 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 00023 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 00024 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 00025 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 00026 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00027 */ 00028 00035 #ifndef __ppc32_REGNAME_H__ 00036 #define __ppc32_REGNAME_H__ 00037 00038 /* Condition Register Bit Fields */ 00039 #define cr0 0 00040 #define cr1 1 00041 #define cr2 2 00042 #define cr3 3 00043 #define cr4 4 00044 #define cr5 5 00045 #define cr6 6 00046 #define cr7 7 00047 00048 /* General Purpose Registers (GPRs) */ 00049 #define r0 0 00050 #define r1 1 00051 #define r2 2 00052 #define r3 3 00053 #define r4 4 00054 #define r5 5 00055 #define r6 6 00056 #define r7 7 00057 #define r8 8 00058 #define r9 9 00059 #define r10 10 00060 #define r11 11 00061 #define r12 12 00062 #define r13 13 00063 #define r14 14 00064 #define r15 15 00065 #define r16 16 00066 #define r17 17 00067 #define r18 18 00068 #define r19 19 00069 #define r20 20 00070 #define r21 21 00071 #define r22 22 00072 #define r23 23 00073 #define r24 24 00074 #define r25 25 00075 #define r26 26 00076 #define r27 27 00077 #define r28 28 00078 #define r29 29 00079 #define r30 30 00080 #define r31 31 00081 00082 /* GPR Aliases */ 00083 #define sp 1 00084 00085 /* Floating Point Registers (FPRs) */ 00086 #define fr0 0 00087 #define fr1 1 00088 #define fr2 2 00089 #define fr3 3 00090 #define fr4 4 00091 #define fr5 5 00092 #define fr6 6 00093 #define fr7 7 00094 #define fr8 8 00095 #define fr9 9 00096 #define fr10 10 00097 #define fr11 11 00098 #define fr12 12 00099 #define fr13 13 00100 #define fr14 14 00101 #define fr15 15 00102 #define fr16 16 00103 #define fr17 17 00104 #define fr18 18 00105 #define fr19 19 00106 #define fr20 20 00107 #define fr21 21 00108 #define fr22 22 00109 #define fr23 23 00110 #define fr24 24 00111 #define fr25 25 00112 #define fr26 26 00113 #define fr27 27 00114 #define fr28 28 00115 #define fr29 29 00116 #define fr30 30 00117 #define fr31 31 00118 00119 #define vr0 0 00120 #define vr1 1 00121 #define vr2 2 00122 #define vr3 3 00123 #define vr4 4 00124 #define vr5 5 00125 #define vr6 6 00126 #define vr7 7 00127 #define vr8 8 00128 #define vr9 9 00129 #define vr10 10 00130 #define vr11 11 00131 #define vr12 12 00132 #define vr13 13 00133 #define vr14 14 00134 #define vr15 15 00135 #define vr16 16 00136 #define vr17 17 00137 #define vr18 18 00138 #define vr19 19 00139 #define vr20 20 00140 #define vr21 21 00141 #define vr22 22 00142 #define vr23 23 00143 #define vr24 24 00144 #define vr25 25 00145 #define vr26 26 00146 #define vr27 27 00147 #define vr28 28 00148 #define vr29 29 00149 #define vr30 30 00150 #define vr31 31 00151 00152 #define evr0 0 00153 #define evr1 1 00154 #define evr2 2 00155 #define evr3 3 00156 #define evr4 4 00157 #define evr5 5 00158 #define evr6 6 00159 #define evr7 7 00160 #define evr8 8 00161 #define evr9 9 00162 #define evr10 10 00163 #define evr11 11 00164 #define evr12 12 00165 #define evr13 13 00166 #define evr14 14 00167 #define evr15 15 00168 #define evr16 16 00169 #define evr17 17 00170 #define evr18 18 00171 #define evr19 19 00172 #define evr20 20 00173 #define evr21 21 00174 #define evr22 22 00175 #define evr23 23 00176 #define evr24 24 00177 #define evr25 25 00178 #define evr26 26 00179 #define evr27 27 00180 #define evr28 28 00181 #define evr29 29 00182 #define evr30 30 00183 #define evr31 31 00184 00185 /* Special Purpose Registers (SPRs) */ 00186 #define xer 1 00187 #define lr 8 00188 #define ctr 9 00189 #define dec 22 00190 #define sdr1 25 00191 #define srr0 26 00192 #define srr1 27 00193 #define sprg0 272 00194 #define sprg1 273 00195 #define sprg2 274 00196 #define sprg3 275 00197 #define prv 287 00198 #define ibat0u 528 00199 #define ibat0l 529 00200 #define ibat1u 530 00201 #define ibat1l 531 00202 #define ibat2u 532 00203 #define ibat2l 533 00204 #define ibat3u 534 00205 #define ibat3l 535 00206 #define dbat0u 536 00207 #define dbat0l 537 00208 #define dbat1u 538 00209 #define dbat1l 539 00210 #define dbat2u 540 00211 #define dbat2l 541 00212 #define dbat3u 542 00213 #define dbat3l 543 00214 #define hid0 1008 00215 00216 /* MSR bits */ 00217 #define msr_ir (1 << 4) 00218 #define msr_dr (1 << 5) 00219 #define msr_pr (1 << 14) 00220 #define msr_ee (1 << 15) 00221 00222 /* HID0 bits */ 00223 #define hid0_ice (1 << 15) 00224 #define hid0_dce (1 << 14) 00225 #define hid0_icfi (1 << 11) 00226 #define hid0_dci (1 << 10) 00227 00228 #endif 00229