Index: kernel/arch/ppc32/src/mm/as.c
===================================================================
--- kernel/arch/ppc32/src/mm/as.c	(revision 4872160f9c176d257f1757469d1adec8033d95f9)
+++ kernel/arch/ppc32/src/mm/as.c	(revision ffe4a87f6f04e3b1afccf14bda789427236053b1)
@@ -55,26 +55,13 @@
 void as_install_arch(as_t *as)
 {
-	asid_t asid;
 	uint32_t sr;
-
-	asid = as->asid;
 	
 	/* Lower 2 GB, user and supervisor access */
-	for (sr = 0; sr < 8; sr++) {
-		asm volatile (
-			"mtsrin %0, %1\n"
-			:
-			: "r" ((0x6000 << 16) + (asid << 4) + sr), "r" (sr << 28)
-		);
-	}
+	for (sr = 0; sr < 8; sr++)
+		sr_set(0x6000, as->asid, sr);
 	
 	/* Upper 2 GB, only supervisor access */
-	for (sr = 8; sr < 16; sr++) {
-		asm volatile (
-			"mtsrin %0, %1\n"
-			:
-			: "r" ((0x4000 << 16) + (asid << 4) + sr), "r" (sr << 28)
-		);
-	}
+	for (sr = 8; sr < 16; sr++)
+		sr_set(0x4000, as->asid, sr);
 }
 
Index: kernel/arch/ppc32/src/mm/frame.c
===================================================================
--- kernel/arch/ppc32/src/mm/frame.c	(revision 4872160f9c176d257f1757469d1adec8033d95f9)
+++ kernel/arch/ppc32/src/mm/frame.c	(revision ffe4a87f6f04e3b1afccf14bda789427236053b1)
@@ -45,12 +45,11 @@
 void physmem_print(void)
 {
-	unsigned int i;
-	
 	printf("Base       Size\n");
 	printf("---------- ----------\n");
-		
+	
+	size_t i;
 	for (i = 0; i < memmap.cnt; i++) {
 		printf("%#10x %#10x\n", memmap.zones[i].start,
-			memmap.zones[i].size);
+		    memmap.zones[i].size);
 	}
 }
@@ -60,11 +59,11 @@
 	pfn_t minconf = 2;
 	size_t i;
-	pfn_t start, conf;
-	size_t size;
 	
 	for (i = 0; i < memmap.cnt; i++) {
-		start = ADDR2PFN(ALIGN_UP((uintptr_t) memmap.zones[i].start, FRAME_SIZE));
-		size = SIZE2FRAMES(ALIGN_DOWN(memmap.zones[i].size, FRAME_SIZE));
+		pfn_t start = ADDR2PFN(ALIGN_UP((uintptr_t) memmap.zones[i].start,
+		    FRAME_SIZE));
+		size_t size = SIZE2FRAMES(ALIGN_DOWN(memmap.zones[i].size, FRAME_SIZE));
 		
+		pfn_t conf;
 		if ((minconf < start) || (minconf >= start + size))
 			conf = start;
@@ -73,6 +72,8 @@
 		
 		zone_create(start, size, conf, 0);
-		if (last_frame < ALIGN_UP((uintptr_t) memmap.zones[i].start + memmap.zones[i].size, FRAME_SIZE))
-			last_frame = ALIGN_UP((uintptr_t) memmap.zones[i].start + memmap.zones[i].size, FRAME_SIZE);
+		if (last_frame < ALIGN_UP((uintptr_t) memmap.zones[i].start
+		    + memmap.zones[i].size, FRAME_SIZE))
+			last_frame = ALIGN_UP((uintptr_t) memmap.zones[i].start
+			    + memmap.zones[i].size, FRAME_SIZE);
 	}
 	
@@ -82,10 +83,8 @@
 	
 	/* Mark the Page Hash Table frames as unavailable */
-	uint32_t sdr1;
-	asm volatile (
-		"mfsdr1 %0\n"
-		: "=r" (sdr1)
-	);
-	frame_mark_unavailable(ADDR2PFN(sdr1 & 0xffff000), 16); // FIXME
+	uint32_t sdr1 = sdr1_get();
+	
+	// FIXME: compute size of PHT exactly
+	frame_mark_unavailable(ADDR2PFN(sdr1 & 0xffff000), 16);
 }
 
Index: kernel/arch/ppc32/src/mm/tlb.c
===================================================================
--- kernel/arch/ppc32/src/mm/tlb.c	(revision 4872160f9c176d257f1757469d1adec8033d95f9)
+++ kernel/arch/ppc32/src/mm/tlb.c	(revision ffe4a87f6f04e3b1afccf14bda789427236053b1)
@@ -45,6 +45,6 @@
 
 static unsigned int seed = 10;
-static unsigned int seed_real __attribute__ ((section("K_UNMAPPED_DATA_START"))) = 42;
-
+static unsigned int seed_real
+    __attribute__ ((section("K_UNMAPPED_DATA_START"))) = 42;
 
 /** Try to find PTE for faulting address
@@ -54,21 +54,21 @@
  * if lock is true.
  *
- * @param as		Address space.
- * @param lock		Lock/unlock the address space.
- * @param badvaddr	Faulting virtual address.
- * @param access	Access mode that caused the fault.
- * @param istate	Pointer to interrupted state.
- * @param pfrc		Pointer to variable where as_page_fault() return code
- * 			will be stored.
- * @return		PTE on success, NULL otherwise.
- *
- */
-static pte_t *
-find_mapping_and_check(as_t *as, bool lock, uintptr_t badvaddr, int access,
-    istate_t *istate, int *pfrc)
+ * @param as       Address space.
+ * @param lock     Lock/unlock the address space.
+ * @param badvaddr Faulting virtual address.
+ * @param access   Access mode that caused the fault.
+ * @param istate   Pointer to interrupted state.
+ * @param pfrc     Pointer to variable where as_page_fault() return code
+ *                 will be stored.
+ *
+ * @return PTE on success, NULL otherwise.
+ *
+ */
+static pte_t *find_mapping_and_check(as_t *as, bool lock, uintptr_t badvaddr,
+    int access, istate_t *istate, int *pfrc)
 {
 	/*
 	 * Check if the mapping exists in page tables.
-	 */	
+	 */
 	pte_t *pte = page_mapping_find(as, badvaddr);
 	if ((pte) && (pte->present)) {
@@ -79,6 +79,4 @@
 		return pte;
 	} else {
-		int rc;
-	
 		/*
 		 * Mapping not found in page tables.
@@ -86,5 +84,7 @@
 		 */
 		page_table_unlock(as, lock);
-		switch (rc = as_page_fault(badvaddr, access, istate)) {
+		
+		int rc = as_page_fault(badvaddr, access, istate);
+		switch (rc) {
 		case AS_PF_OK:
 			/*
@@ -107,8 +107,7 @@
 		default:
 			panic("Unexpected rc (%d).", rc);
-		}	
-	}
-}
-
+		}
+	}
+}
 
 static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate)
@@ -123,5 +122,4 @@
 }
 
-
 static void pht_insert(const uintptr_t vaddr, const pte_t *pte)
 {
@@ -129,16 +127,8 @@
 	uint32_t api = (vaddr >> 22) & 0x3f;
 	
-	uint32_t vsid;
-	asm volatile (
-		"mfsrin %0, %1\n"
-		: "=r" (vsid)
-		: "r" (vaddr)
-	);
-	
-	uint32_t sdr1;
-	asm volatile (
-		"mfsdr1 %0\n"
-		: "=r" (sdr1)
-	);
+	uint32_t vsid = sr_get(vaddr);
+	uint32_t sdr1 = sdr1_get();
+	
+	// FIXME: compute size of PHT exactly
 	phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000);
 	
@@ -215,5 +205,4 @@
 }
 
-
 /** Process Instruction/Data Storage Exception
  *
@@ -224,7 +213,4 @@
 void pht_refill(int n, istate_t *istate)
 {
-	uintptr_t badvaddr;
-	pte_t *pte;
-	int pfrc;
 	as_t *as;
 	bool lock;
@@ -238,13 +224,17 @@
 	}
 	
+	uintptr_t badvaddr;
+	
 	if (n == VECTOR_DATA_STORAGE)
 		badvaddr = istate->dar;
 	else
 		badvaddr = istate->pc;
-		
+	
 	page_table_lock(as, lock);
 	
-	pte = find_mapping_and_check(as, lock, badvaddr,
+	int pfrc;
+	pte_t *pte = find_mapping_and_check(as, lock, badvaddr,
 	    PF_ACCESS_READ /* FIXME */, istate, &pfrc);
+	
 	if (!pte) {
 		switch (pfrc) {
@@ -264,5 +254,6 @@
 	}
 	
-	pte->accessed = 1; /* Record access to PTE */
+	/* Record access to PTE */
+	pte->accessed = 1;
 	pht_insert(badvaddr, pte);
 	
@@ -274,5 +265,4 @@
 	pht_refill_fail(badvaddr, istate);
 }
-
 
 /** Process Instruction/Data Storage Exception in Real Mode
@@ -291,9 +281,5 @@
 		badvaddr = istate->pc;
 	
-	uint32_t physmem;
-	asm volatile (
-		"mfsprg3 %0\n"
-		: "=r" (physmem)
-	);
+	uint32_t physmem = physmem_top();
 	
 	if ((badvaddr < PA2KA(0)) || (badvaddr >= PA2KA(physmem)))
@@ -303,16 +289,8 @@
 	uint32_t api = (badvaddr >> 22) & 0x3f;
 	
-	uint32_t vsid;
-	asm volatile (
-		"mfsrin %0, %1\n"
-		: "=r" (vsid)
-		: "r" (badvaddr)
-	);
-	
-	uint32_t sdr1;
-	asm volatile (
-		"mfsdr1 %0\n"
-		: "=r" (sdr1)
-	);
+	uint32_t vsid = sr_get(badvaddr);
+	uint32_t sdr1 = sdr1_get();
+	
+	// FIXME: compute size of PHT exactly
 	phte_t *phte_real = (phte_t *) (sdr1 & 0xffff0000);
 	
@@ -396,5 +374,4 @@
 }
 
-
 /** Process ITLB/DTLB Miss Exception in Real Mode
  *
@@ -404,10 +381,5 @@
 {
 	uint32_t badvaddr = tlbmiss & 0xfffffffc;
-	
-	uint32_t physmem;
-	asm volatile (
-		"mfsprg3 %0\n"
-		: "=r" (physmem)
-	);
+	uint32_t physmem = physmem_top();
 	
 	if ((badvaddr < PA2KA(0)) || (badvaddr >= PA2KA(physmem)))
@@ -420,15 +392,14 @@
 	uint32_t index = 0;
 	asm volatile (
-		"mtspr 981, %0\n"
-		"mtspr 982, %1\n"
-		"tlbld %2\n"
-		"tlbli %2\n"
-		: "=r" (index)
-		: "r" (ptehi),
-		  "r" (ptelo)
+		"mtspr 981, %[ptehi]\n"
+		"mtspr 982, %[ptelo]\n"
+		"tlbld %[index]\n"
+		"tlbli %[index]\n"
+		: [index] "=r" (index)
+		: [ptehi] "r" (ptehi),
+		  [ptelo] "r" (ptelo)
 	);
 }
 
-
 void tlb_arch_init(void)
 {
@@ -436,15 +407,15 @@
 }
 
-
 void tlb_invalidate_all(void)
 {
 	uint32_t index;
+	
 	asm volatile (
-		"li %0, 0\n"
+		"li %[index], 0\n"
 		"sync\n"
 		
 		".rept 64\n"
-		"tlbie %0\n"
-		"addi %0, %0, 0x1000\n"
+		"	tlbie %[index]\n"
+		"	addi %[index], %[index], 0x1000\n"
 		".endr\n"
 		
@@ -452,19 +423,16 @@
 		"tlbsync\n"
 		"sync\n"
-		: "=r" (index)
+		: [index] "=r" (index)
 	);
 }
 
-
 void tlb_invalidate_asid(asid_t asid)
 {
-	uint32_t sdr1;
-	asm volatile (
-		"mfsdr1 %0\n"
-		: "=r" (sdr1)
-	);
+	uint32_t sdr1 = sdr1_get();
+	
+	// FIXME: compute size of PHT exactly
 	phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000);
 	
-	uint32_t i;
+	size_t i;
 	for (i = 0; i < 8192; i++) {
 		if ((phte[i].v) && (phte[i].vsid >= (asid << 4)) &&
@@ -472,7 +440,7 @@
 			phte[i].v = 0;
 	}
+	
 	tlb_invalidate_all();
 }
-
 
 void tlb_invalidate_pages(asid_t asid, uintptr_t page, size_t cnt)
@@ -482,15 +450,17 @@
 }
 
-
 #define PRINT_BAT(name, ureg, lreg) \
 	asm volatile ( \
-		"mfspr %0," #ureg "\n" \
-		"mfspr %1," #lreg "\n" \
-		: "=r" (upper), "=r" (lower) \
+		"mfspr %[upper], " #ureg "\n" \
+		"mfspr %[lower], " #lreg "\n" \
+		: [upper] "=r" (upper), \
+		  [lower] "=r" (lower) \
 	); \
+	\
 	mask = (upper & 0x1ffc) >> 2; \
 	if (upper & 3) { \
 		uint32_t tmp = mask; \
 		length = 128; \
+		\
 		while (tmp) { \
 			if ((tmp & 1) == 0) { \
@@ -503,4 +473,5 @@
 	} else \
 		length = 0; \
+	\
 	printf(name ": page=%.*p frame=%.*p length=%d KB (mask=%#x)%s%s\n", \
 	    sizeof(upper) * 2, upper & 0xffff0000, sizeof(lower) * 2, \
@@ -515,10 +486,6 @@
 	
 	for (sr = 0; sr < 16; sr++) {
-		uint32_t vsid;
-		asm volatile (
-			"mfsrin %0, %1\n"
-			: "=r" (vsid)
-			: "r" (sr << 28)
-		);
+		uint32_t vsid = sr_get(sr << 28);
+		
 		printf("sr[%02u]: vsid=%.*p (asid=%u)%s%s\n", sr,
 		    sizeof(vsid) * 2, vsid & 0xffffff, (vsid & 0xffffff) >> 4,