Index: arch/amd64/Makefile.inc =================================================================== --- arch/amd64/Makefile.inc (revision b02e5d154b0ee45ab51535f200a33bf889c721f8) +++ arch/amd64/Makefile.inc (revision ffc277e3c054a3016b2cfa2ea3b7a295fd2a54c3) @@ -22,10 +22,9 @@ -CPPFLAGS=$(DEFS) -nostdinc -I../include -CFLAGS=$(CPPFLAGS) -nostdlib -fno-builtin -fno-unwind-tables -Werror-implicit-function-declaration -Wmissing-prototypes -Werror -O3 -march=opteron -m64 -mcmodel=kernel -mno-red-zone +CFLAGS=$(DEFS) -nostdlib -fno-builtin -fno-unwind-tables -O3 -march=opteron -m64 -mcmodel=kernel -mno-red-zone LFLAGS=-M ../arch/$(ARCH)/_link.ld: ../arch/$(ARCH)/_link.ld.in - $(CC) $(CFLAGS) -E -x c $< | grep -v "^\#" > $@ + $(CC) $(CFLAGS) -C -E -x c $< | grep -v "^\#" > $@ arch_sources = arch/dummy.s \ Index: arch/amd64/src/fpu_context.c =================================================================== --- arch/amd64/src/fpu_context.c (revision b02e5d154b0ee45ab51535f200a33bf889c721f8) +++ arch/amd64/src/fpu_context.c (revision ffc277e3c054a3016b2cfa2ea3b7a295fd2a54c3) @@ -46,5 +46,5 @@ void fpu_context_restore(fpu_context_t *fctx) { - /* TODO: We need malloc that allocates on 16-byte boundary !! */ + /* Align on 16-byte boundary */ if (((__u64)fctx) & 0xf) fctx = (fpu_context_t *)((((__u64)fctx) | 0xf) + 1); @@ -57,4 +57,5 @@ void fpu_init(void) { + /* TODO: Zero all SSE, MMX etc. registers */ __asm__ volatile ( "fninit;" Index: arch/ia32/Makefile.inc =================================================================== --- arch/ia32/Makefile.inc (revision b02e5d154b0ee45ab51535f200a33bf889c721f8) +++ arch/ia32/Makefile.inc (revision ffc277e3c054a3016b2cfa2ea3b7a295fd2a54c3) @@ -18,10 +18,9 @@ endif -CPPFLAGS=$(DEFS) -nostdinc -I../include -CFLAGS=$(CPPFLAGS) -nostdlib -fno-builtin -fomit-frame-pointer -Werror-implicit-function-declaration -Wmissing-prototypes -Werror -O3 +CFLAGS=$(DEFS) -nostdlib -fno-builtin -fomit-frame-pointer -O3 LFLAGS=-M -no-check-sections ../arch/$(ARCH)/_link.ld: ../arch/$(ARCH)/_link.ld.in - $(CC) $(CFLAGS) -E -x c $< | grep -v "^\#" > $@ + $(CC) $(CFLAGS) -C -E -x c $< | grep -v "^\#" > $@ arch_sources= \ Index: arch/ia64/Makefile.inc =================================================================== --- arch/ia64/Makefile.inc (revision b02e5d154b0ee45ab51535f200a33bf889c721f8) +++ arch/ia64/Makefile.inc (revision ffc277e3c054a3016b2cfa2ea3b7a295fd2a54c3) @@ -16,6 +16,5 @@ DEFS=-DARCH=$(ARCH) -CPPFLAGS=$(DEFS) -nostdinc -I../include -CFLAGS=$(CPPFLAGS) -mconstant-gp -nostdlib -fno-builtin -fno-unwind-tables -Werror-implicit-function-declaration -Wmissing-prototypes -Werror -O3 +CFLAGS=$(DEFS) -mconstant-gp -nostdlib -fno-builtin -fno-unwind-tables -O3 LFLAGS=-EL -M Index: arch/mips/Makefile.inc =================================================================== --- arch/mips/Makefile.inc (revision b02e5d154b0ee45ab51535f200a33bf889c721f8) +++ arch/mips/Makefile.inc (revision ffc277e3c054a3016b2cfa2ea3b7a295fd2a54c3) @@ -14,8 +14,39 @@ ASFLAGS=-mips3 -DEFS=-DARCH=$(ARCH) -CPPFLAGS=$(DEFS) -mno-abicalls -nostdinc -I../include -CFLAGS=$(CPPFLAGS) -mips2 -G 0 -nostdlib -fno-builtin -Werror-implicit-function-declaration -Wmissing-prototypes -Werror -O2 -msoft-float +DEFS=-DARCH=$(ARCH) -DMACHINE=${MACHINE} +CFLAGS=$(DEFS) -mno-abicalls -mips3 -G 0 -nostdlib -fno-builtin -O2 LFLAGS=-mips2 -M -no-check-sections + +# It seems that on big endian either GCC or the simulators +# have the swl/swr/lwl/lwr instructions wrong. Just for sure, +# disable it with -mmemcpy (force calling memcpy instead of inlining) + +ifeq (${MACHINE},indy) + CFLAGS += -EB -mmemcpy -DBIG_ENDIAN -DHAVE_FPU -DFPU_LAZY + BFD = elf32-big +endif + +ifeq (${MACHINE},lgxemul) + CFLAGS += -DHAVE_FPU -DFPU_LAZY + BFD = ecoff-littlemips +endif + +ifeq (${MACHINE},bgxemul) + CFLAGS += -EB -mmemcpy -DBIG_ENDIAN -DHAVE_FPU -DFPU_LAZY + BFD = ecoff-bigmips +endif + +ifeq (${MACHINE},msim) + BFD = binary + CFLAGS += -msoft-float +endif + +ifeq (${MACHINE},simics) + BFD = elf32-little + CFLAGS += -msoft-float +endif + +../arch/$(ARCH)/_link.ld: ../arch/$(ARCH)/_link.ld.in + $(CC) $(CFLAGS) -C -DBFD=${BFD} -E -x c $< | grep -v "^\#" > $@ arch_sources= \ Index: arch/mips/_link.ld =================================================================== --- arch/mips/_link.ld (revision b02e5d154b0ee45ab51535f200a33bf889c721f8) +++ (revision ) @@ -1,52 +1,0 @@ -/* - * MIPS linker script - * - * kernel text - * kernel data - * - */ - -/* OUTPUT_FORMAT(ecoff-littlemips) */ -OUTPUT_FORMAT(binary) -/* OUTPUT_FORMAT(elf32-little) */ - -ENTRY(kernel_image_start) - -SECTIONS { - .image 0x80000000: AT (0) { - _gp = 0x00000000; - - ktext_start = .; - *(.text); - ktext_end = .; - - kdata_start = .; - *(.reginfo); - *(.rodata); - *(.rodata.*); - *(.rdata); - *(.data); /* initialized data */ - *(.lit8); - *(.lit4); - *(.sdata); - *(.sbss); - *(.comment); - *(.pdr); - - hardcoded_ktext_size = .; - LONG(ktext_end - ktext_start); - hardcoded_kdata_size = .; - LONG(kdata_end - kdata_start); - hardcoded_load_address = .; - LONG(0x80000000); - *(.bss); /* uninitialized static variables */ - *(.scommon); - *(COMMON); /* global variables */ - - symbol_table = .; - *(symtab.*); /* Symbol table, must be LAST symbol!*/ - - kdata_end = .; - - } -} Index: arch/mips/_link.ld.in =================================================================== --- arch/mips/_link.ld.in (revision ffc277e3c054a3016b2cfa2ea3b7a295fd2a54c3) +++ arch/mips/_link.ld.in (revision ffc277e3c054a3016b2cfa2ea3b7a295fd2a54c3) @@ -0,0 +1,57 @@ +/* + * MIPS linker script + * + * kernel text + * kernel data + * + */ +#undef mips +#define mips mips + +OUTPUT_FORMAT(BFD) + +OUTPUT_ARCH(mips) + +ENTRY(kernel_image_start) + +SECTIONS { + . = 0x80100000; + .text : { + ktext_start = .; + *(.text); + ktext_end = .; + } + .data : { + kdata_start = .; + *(.data); /* initialized data */ + hardcoded_ktext_size = .; + LONG(ktext_end - ktext_start); + hardcoded_kdata_size = .; + LONG(kdata_end - kdata_start); + hardcoded_load_address = .; + LONG(0x80100000); + } + _gp = . + 0x8000; + .lit8 : { *(.lit8) } + .lit4 : { *(.lit4) } + .sdata : { *(.sdata) } + .sbss : { + *(.sbss); + *(.scommon); + } + .bss : { + *(.bss); /* uninitialized static variables */ + *(COMMON); /* global variables */ + } + mysymtable : { + symbol_table = .; + *(symtab.*); /* Symbol table, must be LAST symbol!*/ + } + kdata_end = .; + + .mdebug : { *(.mdebug) } + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .comment : { *(.comment) } + .note : { *(.note) } +} Index: arch/mips/boot/boot.S =================================================================== --- arch/mips/boot/boot.S (revision b02e5d154b0ee45ab51535f200a33bf889c721f8) +++ arch/mips/boot/boot.S (revision ffc277e3c054a3016b2cfa2ea3b7a295fd2a54c3) @@ -37,6 +37,6 @@ .global start start: - lui $ra, KERNEL_STARTUP_ADDRESS >> 16 - ori $ra, KERNEL_STARTUP_ADDRESS & 0xffff + lui $ra, KERNEL_LOAD_ADDRESS >> 16 + ori $ra, KERNEL_LOAD_ADDRESS & 0xffff j $ra Index: arch/mips/include/asm.h =================================================================== --- arch/mips/include/asm.h (revision b02e5d154b0ee45ab51535f200a33bf889c721f8) +++ arch/mips/include/asm.h (revision ffc277e3c054a3016b2cfa2ea3b7a295fd2a54c3) @@ -34,5 +34,10 @@ #include -#define cpu_sleep() ; + +static inline void cpu_sleep(void) +{ + /* Most of the simulators do not support */ +/* __asm__ volatile ("wait"); */ +} /** Return base address of current stack Index: arch/mips/include/asm/boot.h =================================================================== --- arch/mips/include/asm/boot.h (revision b02e5d154b0ee45ab51535f200a33bf889c721f8) +++ arch/mips/include/asm/boot.h (revision ffc277e3c054a3016b2cfa2ea3b7a295fd2a54c3) @@ -35,5 +35,5 @@ /* Kernel startup address */ -#define KERNEL_STARTUP_ADDRESS 0x80000300 +#define KERNEL_LOAD_ADDRESS 0x80100000 Index: arch/mips/include/byteorder.h =================================================================== --- arch/mips/include/byteorder.h (revision b02e5d154b0ee45ab51535f200a33bf889c721f8) +++ arch/mips/include/byteorder.h (revision ffc277e3c054a3016b2cfa2ea3b7a295fd2a54c3) @@ -31,5 +31,15 @@ /* MIPS is little-endian */ -#define native_le2host(n) n +#ifdef BIG_ENDIAN +static inline __native native_le2host(__native n) +{ + return ((n & 0xff) << 24) | + ((n & 0xff00) << 8) | + ((n & 0xff0000) >> 8) | + ((n & 0xff000000) >> 24); +} +#else +# define native_le2host(n) n +#endif #endif Index: arch/mips/include/cp0.h =================================================================== --- arch/mips/include/cp0.h (revision b02e5d154b0ee45ab51535f200a33bf889c721f8) +++ arch/mips/include/cp0.h (revision ffc277e3c054a3016b2cfa2ea3b7a295fd2a54c3) @@ -35,6 +35,7 @@ #define cp0_status_exl_exception_bit (1<<1) #define cp0_status_erl_error_bit (1<<2) +#define cp0_status_um_bit (1<<4) #define cp0_status_bev_bootstrap_bit (1<<22) -#define cp0_status_um_bit (1<<4) +#define cp0_status_fpu_bit (1<<29) #define cp0_status_im7_shift 15 @@ -44,4 +45,24 @@ */ #define cp0_compare_value 10000 + +static inline void tlbp(void) +{ + __asm__ volatile ("tlbp"); +} + +static inline void tlbr(void) +{ + __asm__ volatile ("tlbr"); +} +static inline void tlbwi(void) +{ + __asm__ volatile ("tlbwi"); +} +static inline void tlbwr(void) +{ + __asm__ volatile ("tlbwr"); +} + + extern __u32 cp0_index_read(void); @@ -87,8 +108,3 @@ extern __u32 cp0_prid_read(void); -extern void tlbp(void); -extern void tlbr(void); -extern void tlbwi(void); -extern void tlbwr(void); - #endif Index: arch/mips/include/exception.h =================================================================== --- arch/mips/include/exception.h (revision b02e5d154b0ee45ab51535f200a33bf889c721f8) +++ arch/mips/include/exception.h (revision ffc277e3c054a3016b2cfa2ea3b7a295fd2a54c3) @@ -92,4 +92,6 @@ extern void exception(struct exception_regdump *pstate); - +extern void tlb_refill_entry(void); +extern void exception_entry(void); +extern void cache_error_entry(void); #endif Index: arch/mips/include/fpu_context.h =================================================================== --- arch/mips/include/fpu_context.h (revision b02e5d154b0ee45ab51535f200a33bf889c721f8) +++ arch/mips/include/fpu_context.h (revision ffc277e3c054a3016b2cfa2ea3b7a295fd2a54c3) @@ -33,9 +33,7 @@ struct fpu_context { -/* TODO: define MIPS FPU context */ + __native dregs[32]; + __native cregs[32]; }; - - - #endif Index: arch/mips/include/thread.h =================================================================== --- arch/mips/include/thread.h (revision b02e5d154b0ee45ab51535f200a33bf889c721f8) +++ arch/mips/include/thread.h (revision ffc277e3c054a3016b2cfa2ea3b7a295fd2a54c3) @@ -30,5 +30,7 @@ #define __mips_THREAD_H__ -#define ARCH_THREAD_DATA +#include + +#define ARCH_THREAD_DATA struct exception_regdump *pstate #endif Index: arch/mips/src/asm.S =================================================================== --- arch/mips/src/asm.S (revision b02e5d154b0ee45ab51535f200a33bf889c721f8) +++ arch/mips/src/asm.S (revision ffc277e3c054a3016b2cfa2ea3b7a295fd2a54c3) @@ -27,4 +27,6 @@ # +#include + .text @@ -116,28 +118,4 @@ -.global tlbp -tlbp: - tlbp - j $31 - nop - -.global tlbr -tlbr: - tlbr - j $31 - nop - -.global tlbwi -tlbwi: - tlbwi - j $31 - nop - -.global tlbwr -tlbwr: - tlbwr - j $31 - nop - .global cpu_halt cpu_halt: @@ -156,4 +134,167 @@ nop +.macro fpu_gp_save reg ctx + mfc1 $t0,$\reg + sw $t0, \reg*4(\ctx) +.endm + +.macro fpu_gp_restore reg ctx + lw $t0, \reg*4(\ctx) + mtc1 $t0,$\reg +.endm + +.macro fpu_ct_save reg ctx + cfc1 $t0,$1 + sw $t0, (\reg+32)*4(\ctx) +.endm + +.macro fpu_ct_restore reg ctx + lw $t0, (\reg+32)*4(\ctx) + ctc1 $t0,$\reg +.endm + + +.global fpu_context_save +fpu_context_save: +#ifdef HAVE_FPU + fpu_gp_save 0,$a0 + fpu_gp_save 1,$a0 + fpu_gp_save 2,$a0 + fpu_gp_save 3,$a0 + fpu_gp_save 4,$a0 + fpu_gp_save 5,$a0 + fpu_gp_save 6,$a0 + fpu_gp_save 7,$a0 + fpu_gp_save 8,$a0 + fpu_gp_save 9,$a0 + fpu_gp_save 10,$a0 + fpu_gp_save 11,$a0 + fpu_gp_save 12,$a0 + fpu_gp_save 13,$a0 + fpu_gp_save 14,$a0 + fpu_gp_save 15,$a0 + fpu_gp_save 16,$a0 + fpu_gp_save 17,$a0 + fpu_gp_save 18,$a0 + fpu_gp_save 19,$a0 + fpu_gp_save 20,$a0 + fpu_gp_save 21,$a0 + fpu_gp_save 22,$a0 + fpu_gp_save 23,$a0 + fpu_gp_save 24,$a0 + fpu_gp_save 25,$a0 + fpu_gp_save 26,$a0 + fpu_gp_save 27,$a0 + fpu_gp_save 28,$a0 + fpu_gp_save 29,$a0 + fpu_gp_save 30,$a0 + fpu_gp_save 31,$a0 + + fpu_ct_save 1,$a0 + fpu_ct_save 2,$a0 + fpu_ct_save 3,$a0 + fpu_ct_save 4,$a0 + fpu_ct_save 5,$a0 + fpu_ct_save 6,$a0 + fpu_ct_save 7,$a0 + fpu_ct_save 8,$a0 + fpu_ct_save 9,$a0 + fpu_ct_save 10,$a0 + fpu_ct_save 11,$a0 + fpu_ct_save 12,$a0 + fpu_ct_save 13,$a0 + fpu_ct_save 14,$a0 + fpu_ct_save 15,$a0 + fpu_ct_save 16,$a0 + fpu_ct_save 17,$a0 + fpu_ct_save 18,$a0 + fpu_ct_save 19,$a0 + fpu_ct_save 20,$a0 + fpu_ct_save 21,$a0 + fpu_ct_save 22,$a0 + fpu_ct_save 23,$a0 + fpu_ct_save 24,$a0 + fpu_ct_save 25,$a0 + fpu_ct_save 26,$a0 + fpu_ct_save 27,$a0 + fpu_ct_save 28,$a0 + fpu_ct_save 29,$a0 + fpu_ct_save 30,$a0 + fpu_ct_save 31,$a0 +#endif + j $ra + nop + +.global fpu_context_restore +fpu_context_restore: +#ifdef HAVE_FPU + fpu_gp_restore 0,$a0 + fpu_gp_restore 1,$a0 + fpu_gp_restore 2,$a0 + fpu_gp_restore 3,$a0 + fpu_gp_restore 4,$a0 + fpu_gp_restore 5,$a0 + fpu_gp_restore 6,$a0 + fpu_gp_restore 7,$a0 + fpu_gp_restore 8,$a0 + fpu_gp_restore 9,$a0 + fpu_gp_restore 10,$a0 + fpu_gp_restore 11,$a0 + fpu_gp_restore 12,$a0 + fpu_gp_restore 13,$a0 + fpu_gp_restore 14,$a0 + fpu_gp_restore 15,$a0 + fpu_gp_restore 16,$a0 + fpu_gp_restore 17,$a0 + fpu_gp_restore 18,$a0 + fpu_gp_restore 19,$a0 + fpu_gp_restore 20,$a0 + fpu_gp_restore 21,$a0 + fpu_gp_restore 22,$a0 + fpu_gp_restore 23,$a0 + fpu_gp_restore 24,$a0 + fpu_gp_restore 25,$a0 + fpu_gp_restore 26,$a0 + fpu_gp_restore 27,$a0 + fpu_gp_restore 28,$a0 + fpu_gp_restore 29,$a0 + fpu_gp_restore 30,$a0 + fpu_gp_restore 31,$a0 + + fpu_ct_restore 1,$a0 + fpu_ct_restore 2,$a0 + fpu_ct_restore 3,$a0 + fpu_ct_restore 4,$a0 + fpu_ct_restore 5,$a0 + fpu_ct_restore 6,$a0 + fpu_ct_restore 7,$a0 + fpu_ct_restore 8,$a0 + fpu_ct_restore 9,$a0 + fpu_ct_restore 10,$a0 + fpu_ct_restore 11,$a0 + fpu_ct_restore 12,$a0 + fpu_ct_restore 13,$a0 + fpu_ct_restore 14,$a0 + fpu_ct_restore 15,$a0 + fpu_ct_restore 16,$a0 + fpu_ct_restore 17,$a0 + fpu_ct_restore 18,$a0 + fpu_ct_restore 19,$a0 + fpu_ct_restore 20,$a0 + fpu_ct_restore 21,$a0 + fpu_ct_restore 22,$a0 + fpu_ct_restore 23,$a0 + fpu_ct_restore 24,$a0 + fpu_ct_restore 25,$a0 + fpu_ct_restore 26,$a0 + fpu_ct_restore 27,$a0 + fpu_ct_restore 28,$a0 + fpu_ct_restore 29,$a0 + fpu_ct_restore 30,$a0 + fpu_ct_restore 31,$a0 +#endif + j $ra + nop + # THIS IS USERSPACE CODE .global utext Index: arch/mips/src/console.c =================================================================== --- arch/mips/src/console.c (revision b02e5d154b0ee45ab51535f200a33bf889c721f8) +++ arch/mips/src/console.c (revision ffc277e3c054a3016b2cfa2ea3b7a295fd2a54c3) @@ -32,6 +32,4 @@ #include -static void (*putchar_func)(const char ch) = NULL; - static void cons_putchar(const char ch) { @@ -53,4 +51,6 @@ } +static void (*putchar_func)(const char ch) = cons_putchar; + void console_init(void) { Index: arch/mips/src/dummy.S =================================================================== --- arch/mips/src/dummy.S (revision b02e5d154b0ee45ab51535f200a33bf889c721f8) +++ arch/mips/src/dummy.S (revision ffc277e3c054a3016b2cfa2ea3b7a295fd2a54c3) @@ -33,13 +33,7 @@ .global asm_delay_loop .global dummy -.global fpu_enable -.global fpu_disable -.global fpu_init calibrate_delay_loop: asm_delay_loop: -fpu_enable: -fpu_disable: -fpu_init: dummy: Index: arch/mips/src/exception.c =================================================================== --- arch/mips/src/exception.c (revision b02e5d154b0ee45ab51535f200a33bf889c721f8) +++ arch/mips/src/exception.c (revision ffc277e3c054a3016b2cfa2ea3b7a295fd2a54c3) @@ -52,4 +52,7 @@ cp0_status_write(cp0_status_read() & ~ (cp0_status_exl_exception_bit | cp0_status_um_bit)); + /* Save pstate so that the threads can access it */ + if (THREAD) + THREAD->pstate = pstate; /* decode exception number and process the exception */ @@ -86,5 +89,9 @@ break; case EXC_CpU: +#ifdef FPU_LAZY + scheduler_fpu_lazy_request(); +#else panic("unhandled Coprocessor Unusable Exception\n"); +#endif break; case EXC_Ov: @@ -111,3 +118,7 @@ pstate->epc += epc_shift; + /* Probable not needed, but just for sure that nobody + * will continue accessing it */ + if (THREAD) + THREAD->pstate = NULL; } Index: arch/mips/src/fpu_context.c =================================================================== --- arch/mips/src/fpu_context.c (revision b02e5d154b0ee45ab51535f200a33bf889c721f8) +++ arch/mips/src/fpu_context.c (revision ffc277e3c054a3016b2cfa2ea3b7a295fd2a54c3) @@ -29,12 +29,27 @@ #include +#include +#include -void fpu_context_save(fpu_context_t *fctx) -{ +void fpu_disable(void) +{ +#ifdef HAVE_FPU + cp0_status_write(cp0_status_read() & ~cp0_status_fpu_bit); + if (THREAD && THREAD->pstate) + THREAD->pstate->status &= ~cp0_status_fpu_bit; +#endif } - -void fpu_context_restore(fpu_context_t *fctx) +void fpu_enable(void) { +#ifdef HAVE_FPU + cp0_status_write(cp0_status_read() | cp0_status_fpu_bit); + if (THREAD && THREAD->pstate) + THREAD->pstate->status |= cp0_status_fpu_bit; +#endif } +void fpu_init(void) +{ + /* TODO: Zero all registers */ +} Index: arch/mips/src/mips.c =================================================================== --- arch/mips/src/mips.c (revision b02e5d154b0ee45ab51535f200a33bf889c721f8) +++ arch/mips/src/mips.c (revision ffc277e3c054a3016b2cfa2ea3b7a295fd2a54c3) @@ -35,7 +35,25 @@ #include #include +#include + +/* Size of the code jumping to the exception handler code + * - J+NOP + */ +#define EXCEPTION_JUMP_SIZE 8 + +#define TLB_EXC ((char *) 0x80000000) +#define NORM_EXC ((char *) 0x80000180) +#define CACHE_EXC ((char *) 0x80000100) + +#include void arch_pre_mm_init(void) { + /* Copy the exception vectors to the right places */ + memcpy(TLB_EXC, (char *)tlb_refill_entry, EXCEPTION_JUMP_SIZE); + memcpy(NORM_EXC, (char *)exception_entry, EXCEPTION_JUMP_SIZE); + memcpy(CACHE_EXC, (char *)cache_error_entry, EXCEPTION_JUMP_SIZE); + + /* * Switch to BEV normal level so that exception vectors point to the kernel. Index: arch/mips/src/mm/frame.c =================================================================== --- arch/mips/src/mm/frame.c (revision b02e5d154b0ee45ab51535f200a33bf889c721f8) +++ arch/mips/src/mm/frame.c (revision ffc277e3c054a3016b2cfa2ea3b7a295fd2a54c3) @@ -32,3 +32,5 @@ void frame_arch_init(void) { + /* Disable first megabyte (God knows why) */ + frame_region_not_free(0, 1024*1024); } Index: arch/mips/src/panic.S =================================================================== --- arch/mips/src/panic.S (revision b02e5d154b0ee45ab51535f200a33bf889c721f8) +++ arch/mips/src/panic.S (revision ffc277e3c054a3016b2cfa2ea3b7a295fd2a54c3) @@ -33,10 +33,11 @@ .set nomacro +#include + .global panic_printf - + +/* From printf return directly to halt() */ panic_printf: - jal printf - nop - j cpu_halt - nop - + lui $ra, %hi(halt) + j printf + ori $ra, %lo(halt) Index: arch/mips/src/start.S =================================================================== --- arch/mips/src/start.S (revision b02e5d154b0ee45ab51535f200a33bf889c721f8) +++ arch/mips/src/start.S (revision ffc277e3c054a3016b2cfa2ea3b7a295fd2a54c3) @@ -154,24 +154,4 @@ .org 0x0 -tlb_refill_entry: - j tlb_refill_handler - nop - -.org 0x100 -cache_error_entry: - j cache_error_handler - nop - -.org 0x180 -norm_exception: - j exception_handler - nop - -.org 0x200 -iv_exception: - j exception_handler - nop - -.org KA2PA(KERNEL_STARTUP_ADDRESS) kernel_image_start: /* Load temporary stack */ @@ -187,8 +167,21 @@ .space TEMP_STACK_SIZE -end_stack: +end_stack: + +tlb_refill_entry: + j tlb_refill_handler + nop + +cache_error_entry: + j cache_error_handler + nop + +exception_entry: + j exception_handler + nop + + exception_handler: -exception_entry: KERNEL_STACK_TO_K0 sub $k0, REGISTER_SPACE Index: arch/ppc/Makefile.inc =================================================================== --- arch/ppc/Makefile.inc (revision b02e5d154b0ee45ab51535f200a33bf889c721f8) +++ arch/ppc/Makefile.inc (revision ffc277e3c054a3016b2cfa2ea3b7a295fd2a54c3) @@ -15,6 +15,5 @@ DEFS=-DARCH=$(ARCH) -CPPFLAGS=$(DEFS) -nostdinc -I../include -CFLAGS=$(CPPFLAGS) -nostdlib -fno-builtin -Werror-implicit-function-declaration -Wmissing-prototypes -Werror -O2 +CFLAGS=$(DEFS) -nostdlib -fno-builtin -O2 LFLAGS=-M -no-check-sections -N