Index: kernel/arch/arm32/Makefile.inc =================================================================== --- kernel/arch/arm32/Makefile.inc (revision 954c0240b720c64358bccbdcdcb035fdd5a6f347) +++ kernel/arch/arm32/Makefile.inc (revision ffa73c60dc2eba8ce632c52a0be8bbf4ecd562d9) @@ -57,4 +57,5 @@ arch/$(KARCH)/src/exception.c \ arch/$(KARCH)/src/userspace.c \ + arch/$(KARCH)/src/smc.c \ arch/$(KARCH)/src/debug/stacktrace.c \ arch/$(KARCH)/src/debug/stacktrace_asm.S \ Index: kernel/arch/arm32/include/arch/barrier.h =================================================================== --- kernel/arch/arm32/include/arch/barrier.h (revision 954c0240b720c64358bccbdcdcb035fdd5a6f347) +++ kernel/arch/arm32/include/arch/barrier.h (revision ffa73c60dc2eba8ce632c52a0be8bbf4ecd562d9) @@ -37,16 +37,10 @@ #define KERN_arm32_BARRIER_H_ -#ifdef KERNEL #include #include #include -#else -#include -#endif - -#define CS_ENTER_BARRIER() asm volatile ("" ::: "memory") -#define CS_LEAVE_BARRIER() asm volatile ("" ::: "memory") #if defined PROCESSOR_ARCH_armv7_a + /* * ARMv7 uses instructions for memory barriers see ARM Architecture reference @@ -57,9 +51,10 @@ * and functionality on armv7 architecture. */ -#define memory_barrier() asm volatile ("dmb" ::: "memory") -#define read_barrier() asm volatile ("dsb" ::: "memory") -#define write_barrier() asm volatile ("dsb st" ::: "memory") -#define inst_barrier() asm volatile ("isb" ::: "memory") -#elif defined PROCESSOR_ARCH_armv6 | defined KERNEL +#define dmb() asm volatile ("dmb" ::: "memory") +#define dsb() asm volatile ("dsb" ::: "memory") +#define isb() asm volatile ("isb" ::: "memory") + +#elif defined PROCESSOR_ARCH_armv6 + /* * ARMv6 introduced user access of the following commands: @@ -75,66 +70,15 @@ * CP15 implementation is mandatory only for armv6+. */ -#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a) -#define memory_barrier() CP15DMB_write(0) +#define dmb() CP15DMB_write(0) +#define dsb() CP15DSB_write(0) +#define isb() CP15ISB_write(0) + #else -#define memory_barrier() CP15DSB_write(0) -#endif -#define read_barrier() CP15DSB_write(0) -#define write_barrier() read_barrier() -#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a) -#define inst_barrier() CP15ISB_write(0) -#else -#define inst_barrier() -#endif -#else -/* - * Older manuals mention syscalls as a way to implement cache coherency and - * barriers. See for example ARM Architecture Reference Manual Version D - * chapter 2.7.4 Prefetching and self-modifying code (p. A2-28) - */ -// TODO implement on per PROCESSOR basis or via syscalls -#define memory_barrier() asm volatile ("" ::: "memory") -#define read_barrier() asm volatile ("" ::: "memory") -#define write_barrier() asm volatile ("" ::: "memory") -#define inst_barrier() asm volatile ("" ::: "memory") -#endif -#ifdef KERNEL - -/* - * There are multiple ways ICache can be implemented on ARM machines. Namely - * PIPT, VIPT, and ASID and VMID tagged VIVT (see ARM Architecture Reference - * Manual B3.11.2 (p. 1383). However, CortexA8 Manual states: "For maximum - * compatibility across processors, ARM recommends that operating systems target - * the ARMv7 base architecture that uses ASID-tagged VIVT instruction caches, - * and do not assume the presence of the IVIPT extension. Software that relies - * on the IVIPT extension might fail in an unpredictable way on an ARMv7 - * implementation that does not include the IVIPT extension." (7.2.6 p. 245). - * Only PIPT invalidates cache for all VA aliases if one block is invalidated. - * - * @note: Supporting ASID and VMID tagged VIVT may need to add ICache - * maintenance to other places than just smc. - */ - -#ifdef KERNEL - -/* - * @note: Cache type register is not available in uspace. We would need - * to export the cache line value, or use syscall for uspace smc_coherence - */ -#define smc_coherence(a, l) \ -do { \ - for (uintptr_t addr = (uintptr_t) a; addr < (uintptr_t) a + l; \ - addr += CP15_C7_MVA_ALIGN) \ - dcache_clean_mva_pou(ALIGN_DOWN((uintptr_t) a, CP15_C7_MVA_ALIGN)); \ - write_barrier(); /* Wait for completion */\ - icache_invalidate();\ - write_barrier();\ - inst_barrier(); /* Wait for Inst refetch */\ -} while (0) +#define dmb() CP15DSB_write(0) +#define dsb() CP15DSB_write(0) +#define isb() #endif - -#endif /* KERNEL */ #endif Index: kernel/arch/arm32/include/arch/mm/page.h =================================================================== --- kernel/arch/arm32/include/arch/mm/page.h (revision 954c0240b720c64358bccbdcdcb035fdd5a6f347) +++ kernel/arch/arm32/include/arch/mm/page.h (revision ffa73c60dc2eba8ce632c52a0be8bbf4ecd562d9) @@ -41,4 +41,5 @@ #include #include +#include #include #include Index: kernel/arch/arm32/include/arch/mm/page_armv4.h =================================================================== --- kernel/arch/arm32/include/arch/mm/page_armv4.h (revision 954c0240b720c64358bccbdcdcb035fdd5a6f347) +++ kernel/arch/arm32/include/arch/mm/page_armv4.h (revision ffa73c60dc2eba8ce632c52a0be8bbf4ecd562d9) @@ -37,4 +37,6 @@ #ifndef KERN_arm32_PAGE_armv4_H_ #define KERN_arm32_PAGE_armv4_H_ + +#include #ifndef KERN_arm32_PAGE_H_ Index: kernel/arch/arm32/src/atomic.c =================================================================== --- kernel/arch/arm32/src/atomic.c (revision 954c0240b720c64358bccbdcdcb035fdd5a6f347) +++ kernel/arch/arm32/src/atomic.c (revision ffa73c60dc2eba8ce632c52a0be8bbf4ecd562d9) @@ -35,4 +35,5 @@ #include +#include @@ -64,4 +65,9 @@ return cur_val; +} + +void __sync_synchronize(void) +{ + dsb(); } Index: kernel/arch/arm32/src/mm/tlb.c =================================================================== --- kernel/arch/arm32/src/mm/tlb.c (revision 954c0240b720c64358bccbdcdcb035fdd5a6f347) +++ kernel/arch/arm32/src/mm/tlb.c (revision ffa73c60dc2eba8ce632c52a0be8bbf4ecd562d9) @@ -41,4 +41,5 @@ #include #include +#include /** Invalidate all entries in TLB. @@ -59,6 +60,6 @@ * ARM Architecture reference Manual ch. B3.10.1 p. B3-1374 B3-1375 */ - read_barrier(); - inst_barrier(); + dsb(); + isb(); } @@ -105,6 +106,6 @@ * ARM Architecture reference Manual ch. B3.10.1 p. B3-1374 B3-1375 */ - read_barrier(); - inst_barrier(); + dsb(); + isb(); } Index: kernel/arch/arm32/src/smc.c =================================================================== --- kernel/arch/arm32/src/smc.c (revision ffa73c60dc2eba8ce632c52a0be8bbf4ecd562d9) +++ kernel/arch/arm32/src/smc.c (revision ffa73c60dc2eba8ce632c52a0be8bbf4ecd562d9) @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +/* + * There are multiple ways ICache can be implemented on ARM machines. Namely + * PIPT, VIPT, and ASID and VMID tagged VIVT (see ARM Architecture Reference + * Manual B3.11.2 (p. 1383). However, CortexA8 Manual states: "For maximum + * compatibility across processors, ARM recommends that operating systems target + * the ARMv7 base architecture that uses ASID-tagged VIVT instruction caches, + * and do not assume the presence of the IVIPT extension. Software that relies + * on the IVIPT extension might fail in an unpredictable way on an ARMv7 + * implementation that does not include the IVIPT extension." (7.2.6 p. 245). + * Only PIPT invalidates cache for all VA aliases if one block is invalidated. + * + * @note: Supporting ASID and VMID tagged VIVT may need to add ICache + * maintenance to other places than just smc. + */ + +// TODO: Determine CP15_C7_MVA_ALIGN dynamically + +void smc_coherence(void *a, size_t l) +{ + uintptr_t end = (uintptr_t) a + l; + uintptr_t begin = ALIGN_DOWN((uintptr_t) a, CP15_C7_MVA_ALIGN); + + for (uintptr_t addr = begin; addr < end; addr += CP15_C7_MVA_ALIGN) { + dcache_clean_mva_pou(addr); + } + + /* Wait for completion */ + dsb(); + + icache_invalidate(); + dsb(); + /* Wait for Inst refetch */ + isb(); +} +