Index: kernel/arch/arm32/include/arch/barrier.h
===================================================================
--- kernel/arch/arm32/include/arch/barrier.h	(revision fa86fff978f42fa20491d74ff2a6cc904ab53fd0)
+++ kernel/arch/arm32/include/arch/barrier.h	(revision ffa73c60dc2eba8ce632c52a0be8bbf4ecd562d9)
@@ -37,16 +37,10 @@
 #define KERN_arm32_BARRIER_H_
 
-#ifdef KERNEL
 #include <arch/cache.h>
 #include <arch/cp15.h>
 #include <align.h>
-#else
-#include <libarch/cp15.h>
-#endif
-
-#define CS_ENTER_BARRIER()  asm volatile ("" ::: "memory")
-#define CS_LEAVE_BARRIER()  asm volatile ("" ::: "memory")
 
 #if defined PROCESSOR_ARCH_armv7_a
+
 /*
  * ARMv7 uses instructions for memory barriers see ARM Architecture reference
@@ -57,9 +51,10 @@
  * and functionality on armv7 architecture.
  */
-#define memory_barrier()  asm volatile ("dmb" ::: "memory")
-#define read_barrier()    asm volatile ("dsb" ::: "memory")
-#define write_barrier()   asm volatile ("dsb st" ::: "memory")
-#define inst_barrier()    asm volatile ("isb" ::: "memory")
-#elif defined PROCESSOR_ARCH_armv6 | defined KERNEL
+#define dmb()    asm volatile ("dmb" ::: "memory")
+#define dsb()    asm volatile ("dsb" ::: "memory")
+#define isb()    asm volatile ("isb" ::: "memory")
+
+#elif defined PROCESSOR_ARCH_armv6
+
 /*
  * ARMv6 introduced user access of the following commands:
@@ -75,66 +70,15 @@
  * CP15 implementation is mandatory only for armv6+.
  */
-#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
-#define memory_barrier()  CP15DMB_write(0)
+#define dmb()    CP15DMB_write(0)
+#define dsb()    CP15DSB_write(0)
+#define isb()    CP15ISB_write(0)
+
 #else
-#define memory_barrier()  CP15DSB_write(0)
-#endif
-#define read_barrier()    CP15DSB_write(0)
-#define write_barrier()   read_barrier()
-#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
-#define inst_barrier()    CP15ISB_write(0)
-#else
-#define inst_barrier()
-#endif
-#else
-/*
- * Older manuals mention syscalls as a way to implement cache coherency and
- * barriers. See for example ARM Architecture Reference Manual Version D
- * chapter 2.7.4 Prefetching and self-modifying code (p. A2-28)
- */
-// TODO implement on per PROCESSOR basis or via syscalls
-#define memory_barrier()  asm volatile ("" ::: "memory")
-#define read_barrier()    asm volatile ("" ::: "memory")
-#define write_barrier()   asm volatile ("" ::: "memory")
-#define inst_barrier()    asm volatile ("" ::: "memory")
-#endif
 
-#ifdef KERNEL
-
-/*
- * There are multiple ways ICache can be implemented on ARM machines. Namely
- * PIPT, VIPT, and ASID and VMID tagged VIVT (see ARM Architecture Reference
- * Manual B3.11.2 (p. 1383).  However, CortexA8 Manual states: "For maximum
- * compatibility across processors, ARM recommends that operating systems target
- * the ARMv7 base architecture that uses ASID-tagged VIVT instruction caches,
- * and do not assume the presence of the IVIPT extension. Software that relies
- * on the IVIPT extension might fail in an unpredictable way on an ARMv7
- * implementation that does not include the IVIPT extension." (7.2.6 p. 245).
- * Only PIPT invalidates cache for all VA aliases if one block is invalidated.
- *
- * @note: Supporting ASID and VMID tagged VIVT may need to add ICache
- * maintenance to other places than just smc.
- */
-
-#ifdef KERNEL
-
-/*
- * @note: Cache type register is not available in uspace. We would need
- * to export the cache line value, or use syscall for uspace smc_coherence
- */
-#define smc_coherence(a, l) \
-do { \
-	for (uintptr_t addr = (uintptr_t) a; addr < (uintptr_t) a + l; \
-	    addr += CP15_C7_MVA_ALIGN) \
-		dcache_clean_mva_pou(ALIGN_DOWN((uintptr_t) a, CP15_C7_MVA_ALIGN)); \
-	write_barrier();               /* Wait for completion */\
-	icache_invalidate();\
-	write_barrier();\
-	inst_barrier();                /* Wait for Inst refetch */\
-} while (0)
+#define dmb()    CP15DSB_write(0)
+#define dsb()    CP15DSB_write(0)
+#define isb()
 
 #endif
-
-#endif	/* KERNEL */
 
 #endif
Index: kernel/arch/arm32/include/arch/mm/page.h
===================================================================
--- kernel/arch/arm32/include/arch/mm/page.h	(revision fa86fff978f42fa20491d74ff2a6cc904ab53fd0)
+++ kernel/arch/arm32/include/arch/mm/page.h	(revision ffa73c60dc2eba8ce632c52a0be8bbf4ecd562d9)
@@ -41,4 +41,5 @@
 #include <arch/exception.h>
 #include <barrier.h>
+#include <arch/barrier.h>
 #include <arch/cp15.h>
 #include <trace.h>
Index: kernel/arch/arm32/include/arch/mm/page_armv4.h
===================================================================
--- kernel/arch/arm32/include/arch/mm/page_armv4.h	(revision fa86fff978f42fa20491d74ff2a6cc904ab53fd0)
+++ kernel/arch/arm32/include/arch/mm/page_armv4.h	(revision ffa73c60dc2eba8ce632c52a0be8bbf4ecd562d9)
@@ -37,4 +37,6 @@
 #ifndef KERN_arm32_PAGE_armv4_H_
 #define KERN_arm32_PAGE_armv4_H_
+
+#include <arch/cache.h>
 
 #ifndef KERN_arm32_PAGE_H_