Changeset ff381a7 in mainline for kernel/arch/arm32/src

Timestamp:

2015-11-02T20:54:19Z (10 years ago)

Author:

Jiri Svoboda <jiri@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

d8513177

Parents:

3feeab2 (diff), 5265eea4 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge mainline changes.

Location:

kernel/arch/arm32/src

Files:

• cpu/cpu.c (modified) (2 diffs)
• mm/tlb.c (modified) (1 diff)

kernel/arch/arm32/src/cpu/cpu.c

@@ -130 +130 @@
 {
         uint32_t control_reg = SCTLR_read();
-        
+
+        dcache_invalidate();
+        read_barrier();
+
         /* Turn off tex remap, RAZ/WI prior to armv7 */
         control_reg &= ~SCTLR_TEX_REMAP_EN_FLAG;
@@ -322 +325 @@
 void icache_invalidate(void)
 {
+#if defined(PROCESSOR_ARCH_armv7_a)
         ICIALLU_write(0);
+#else
+        ICIALL_write(0);
+#endif
+}
+
+#if !defined(PROCESSOR_ARCH_armv7_a)
+static bool cache_is_unified(void)
+{
+        if (MIDR_read() != CTR_read()) {
+                /* We have the CTR register */
+                return (CTR_read() & CTR_SEP_FLAG) != CTR_SEP_FLAG;
+        } else {
+                panic("Unknown cache type");
+        }
+}
+#endif
+
+void dcache_invalidate(void)
+{
+#if defined(PROCESSOR_ARCH_armv7_a)
+        dcache_flush_invalidate();
+#else
+        if (cache_is_unified())
+                CIALL_write(0);
+        else
+                DCIALL_write(0);
+#endif
+}
+
+void dcache_clean_mva_pou(uintptr_t mva)
+{
+#if defined(PROCESSOR_ARCH_armv7_a)
+        DCCMVAU_write(mva);
+#else
+        if (cache_is_unified())
+                CCMVA_write(mva);
+        else
+                DCCMVA_write(mva);
+#endif
 }
 

kernel/arch/arm32/src/mm/tlb.c

@@ -79 +79 @@
 static inline void invalidate_page(uintptr_t page)
 {
-        //TODO: What about TLBIMVAA?
+#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
+        if (TLBTR_read() & TLBTR_SEP_FLAG) {
+                ITLBIMVA_write(page);
+                DTLBIMVA_write(page);
+        } else {
+                TLBIMVA_write(page);
+        }
+#elif defined(PROCESSOR_arm920t)
+        ITLBIMVA_write(page);
+        DTLBIMVA_write(page);
+#elif defined(PROCESSOR_arm926ej_s)
         TLBIMVA_write(page);
+#else
+#error Unknown TLB type
+#endif
+
         /*
          * "A TLB maintenance operation is only guaranteed to be complete after