Index: kernel/arch/sparc64/include/mm/as.h
===================================================================
--- kernel/arch/sparc64/include/mm/as.h	(revision b97b348a7bdc9e9697abe5dcd02f197f8ff5053f)
+++ kernel/arch/sparc64/include/mm/as.h	(revision fef504a2ec75b492fbfc942a4a1caa99b045fd64)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup sparc64mm	
+/** @addtogroup sparc64mm
  * @{
  */
@@ -37,7 +37,11 @@
 
 #if defined (SUN4U)
+
 #include <arch/mm/sun4u/as.h>
+
 #elif defined (SUN4V)
+
 #include <arch/mm/sun4v/as.h>
+
 #endif
 
Index: kernel/arch/sparc64/include/mm/frame.h
===================================================================
--- kernel/arch/sparc64/include/mm/frame.h	(revision b97b348a7bdc9e9697abe5dcd02f197f8ff5053f)
+++ kernel/arch/sparc64/include/mm/frame.h	(revision fef504a2ec75b492fbfc942a4a1caa99b045fd64)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup sparc64mm	
+/** @addtogroup sparc64mm
  * @{
  */
@@ -37,7 +37,11 @@
 
 #if defined (SUN4U)
+
 #include <arch/mm/sun4u/frame.h>
+
 #elif defined (SUN4V)
+
 #include <arch/mm/sun4v/frame.h>
+
 #endif
 
Index: kernel/arch/sparc64/include/mm/sun4u/tlb.h
===================================================================
--- kernel/arch/sparc64/include/mm/sun4u/tlb.h	(revision b97b348a7bdc9e9697abe5dcd02f197f8ff5053f)
+++ kernel/arch/sparc64/include/mm/sun4u/tlb.h	(revision fef504a2ec75b492fbfc942a4a1caa99b045fd64)
@@ -100,4 +100,5 @@
 #include <arch/barrier.h>
 #include <typedefs.h>
+#include <trace.h>
 #include <arch/register.h>
 #include <arch/cpu.h>
@@ -242,5 +243,5 @@
  * Determine the number of entries in the DMMU's small TLB. 
  */
-static inline uint16_t tlb_dsmall_size(void)
+NO_TRACE static inline uint16_t tlb_dsmall_size(void)
 {
 	return 16;
@@ -250,5 +251,5 @@
  * Determine the number of entries in each DMMU's big TLB. 
  */
-static inline uint16_t tlb_dbig_size(void)
+NO_TRACE static inline uint16_t tlb_dbig_size(void)
 {
 	return 512;
@@ -258,5 +259,5 @@
  * Determine the number of entries in the IMMU's small TLB. 
  */
-static inline uint16_t tlb_ismall_size(void)
+NO_TRACE static inline uint16_t tlb_ismall_size(void)
 {
 	return 16;
@@ -266,5 +267,5 @@
  * Determine the number of entries in the IMMU's big TLB. 
  */
-static inline uint16_t tlb_ibig_size(void)
+NO_TRACE static inline uint16_t tlb_ibig_size(void)
 {
 	if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS)
@@ -280,5 +281,5 @@
  * @return		Current value of Primary Context Register.
  */
-static inline uint64_t mmu_primary_context_read(void)
+NO_TRACE static inline uint64_t mmu_primary_context_read(void)
 {
 	return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG);
@@ -289,5 +290,5 @@
  * @param v		New value of Primary Context Register.
  */
-static inline void mmu_primary_context_write(uint64_t v)
+NO_TRACE static inline void mmu_primary_context_write(uint64_t v)
 {
 	asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
@@ -299,5 +300,5 @@
  * @return		Current value of Secondary Context Register.
  */
-static inline uint64_t mmu_secondary_context_read(void)
+NO_TRACE static inline uint64_t mmu_secondary_context_read(void)
 {
 	return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG);
@@ -308,5 +309,5 @@
  * @param v		New value of Primary Context Register.
  */
-static inline void mmu_secondary_context_write(uint64_t v)
+NO_TRACE static inline void mmu_secondary_context_write(uint64_t v)
 {
 	asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v);
@@ -323,5 +324,5 @@
  * 			Register.
  */
-static inline uint64_t itlb_data_access_read(size_t entry)
+NO_TRACE static inline uint64_t itlb_data_access_read(size_t entry)
 {
 	itlb_data_access_addr_t reg;
@@ -337,5 +338,5 @@
  * @param value		Value to be written.
  */
-static inline void itlb_data_access_write(size_t entry, uint64_t value)
+NO_TRACE static inline void itlb_data_access_write(size_t entry, uint64_t value)
 {
 	itlb_data_access_addr_t reg;
@@ -354,5 +355,5 @@
  * 			Register.
  */
-static inline uint64_t dtlb_data_access_read(size_t entry)
+NO_TRACE static inline uint64_t dtlb_data_access_read(size_t entry)
 {
 	dtlb_data_access_addr_t reg;
@@ -368,5 +369,5 @@
  * @param value		Value to be written.
  */
-static inline void dtlb_data_access_write(size_t entry, uint64_t value)
+NO_TRACE static inline void dtlb_data_access_write(size_t entry, uint64_t value)
 {
 	dtlb_data_access_addr_t reg;
@@ -384,5 +385,5 @@
  * @return		Current value of specified IMMU TLB Tag Read Register.
  */
-static inline uint64_t itlb_tag_read_read(size_t entry)
+NO_TRACE static inline uint64_t itlb_tag_read_read(size_t entry)
 {
 	itlb_tag_read_addr_t tag;
@@ -399,5 +400,5 @@
  * @return		Current value of specified DMMU TLB Tag Read Register.
  */
-static inline uint64_t dtlb_tag_read_read(size_t entry)
+NO_TRACE static inline uint64_t dtlb_tag_read_read(size_t entry)
 {
 	dtlb_tag_read_addr_t tag;
@@ -419,5 +420,5 @@
  * 			Register.
  */
-static inline uint64_t itlb_data_access_read(int tlb, size_t entry)
+NO_TRACE static inline uint64_t itlb_data_access_read(int tlb, size_t entry)
 {
 	itlb_data_access_addr_t reg;
@@ -434,5 +435,5 @@
  * @param value		Value to be written.
  */
-static inline void itlb_data_access_write(int tlb, size_t entry,
+NO_TRACE static inline void itlb_data_access_write(int tlb, size_t entry,
 	uint64_t value)
 {
@@ -454,5 +455,5 @@
  * 			Register.
  */
-static inline uint64_t dtlb_data_access_read(int tlb, size_t entry)
+NO_TRACE static inline uint64_t dtlb_data_access_read(int tlb, size_t entry)
 {
 	dtlb_data_access_addr_t reg;
@@ -470,5 +471,5 @@
  * @param value		Value to be written.
  */
-static inline void dtlb_data_access_write(int tlb, size_t entry,
+NO_TRACE static inline void dtlb_data_access_write(int tlb, size_t entry,
 	uint64_t value)
 {
@@ -489,5 +490,5 @@
  * @return		Current value of specified IMMU TLB Tag Read Register.
  */
-static inline uint64_t itlb_tag_read_read(int tlb, size_t entry)
+NO_TRACE static inline uint64_t itlb_tag_read_read(int tlb, size_t entry)
 {
 	itlb_tag_read_addr_t tag;
@@ -506,5 +507,5 @@
  * @return		Current value of specified DMMU TLB Tag Read Register.
  */
-static inline uint64_t dtlb_tag_read_read(int tlb, size_t entry)
+NO_TRACE static inline uint64_t dtlb_tag_read_read(int tlb, size_t entry)
 {
 	dtlb_tag_read_addr_t tag;
@@ -523,5 +524,5 @@
  * @param v		Value to be written.
  */
-static inline void itlb_tag_access_write(uint64_t v)
+NO_TRACE static inline void itlb_tag_access_write(uint64_t v)
 {
 	asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);
@@ -533,5 +534,5 @@
  * @return		Current value of IMMU TLB Tag Access Register.
  */
-static inline uint64_t itlb_tag_access_read(void)
+NO_TRACE static inline uint64_t itlb_tag_access_read(void)
 {
 	return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS);
@@ -542,5 +543,5 @@
  * @param v		Value to be written.
  */
-static inline void dtlb_tag_access_write(uint64_t v)
+NO_TRACE static inline void dtlb_tag_access_write(uint64_t v)
 {
 	asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v);
@@ -552,5 +553,5 @@
  * @return 		Current value of DMMU TLB Tag Access Register.
  */
-static inline uint64_t dtlb_tag_access_read(void)
+NO_TRACE static inline uint64_t dtlb_tag_access_read(void)
 {
 	return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS);
@@ -562,5 +563,5 @@
  * @param v		Value to be written.
  */
-static inline void itlb_data_in_write(uint64_t v)
+NO_TRACE static inline void itlb_data_in_write(uint64_t v)
 {
 	asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v);
@@ -572,5 +573,5 @@
  * @param v		Value to be written.
  */
-static inline void dtlb_data_in_write(uint64_t v)
+NO_TRACE static inline void dtlb_data_in_write(uint64_t v)
 {
 	asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v);
@@ -582,5 +583,5 @@
  * @return		Current content of I-SFSR register.
  */
-static inline uint64_t itlb_sfsr_read(void)
+NO_TRACE static inline uint64_t itlb_sfsr_read(void)
 {
 	return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR);
@@ -591,5 +592,5 @@
  * @param v		New value of I-SFSR register.
  */
-static inline void itlb_sfsr_write(uint64_t v)
+NO_TRACE static inline void itlb_sfsr_write(uint64_t v)
 {
 	asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v);
@@ -601,5 +602,5 @@
  * @return		Current content of D-SFSR register.
  */
-static inline uint64_t dtlb_sfsr_read(void)
+NO_TRACE static inline uint64_t dtlb_sfsr_read(void)
 {
 	return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR);
@@ -610,5 +611,5 @@
  * @param v		New value of D-SFSR register.
  */
-static inline void dtlb_sfsr_write(uint64_t v)
+NO_TRACE static inline void dtlb_sfsr_write(uint64_t v)
 {
 	asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v);
@@ -620,5 +621,5 @@
  * @return		Current content of D-SFAR register.
  */
-static inline uint64_t dtlb_sfar_read(void)
+NO_TRACE static inline uint64_t dtlb_sfar_read(void)
 {
 	return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR);
@@ -633,5 +634,5 @@
  * @param page		Address which is on the page to be demapped.
  */
-static inline void itlb_demap(int type, int context_encoding, uintptr_t page)
+NO_TRACE static inline void itlb_demap(int type, int context_encoding, uintptr_t page)
 {
 	tlb_demap_addr_t da;
@@ -659,5 +660,5 @@
  * @param page		Address which is on the page to be demapped.
  */
-static inline void dtlb_demap(int type, int context_encoding, uintptr_t page)
+NO_TRACE static inline void dtlb_demap(int type, int context_encoding, uintptr_t page)
 {
 	tlb_demap_addr_t da;
Index: kernel/arch/sparc64/include/mm/sun4v/tlb.h
===================================================================
--- kernel/arch/sparc64/include/mm/sun4v/tlb.h	(revision b97b348a7bdc9e9697abe5dcd02f197f8ff5053f)
+++ kernel/arch/sparc64/include/mm/sun4v/tlb.h	(revision fef504a2ec75b492fbfc942a4a1caa99b045fd64)
@@ -43,5 +43,5 @@
 
 #include <arch/mm/tte.h>
-#include <print.h>
+#include <trace.h>
 #include <arch/mm/mmu.h>
 #include <arch/mm/page.h>
@@ -88,32 +88,32 @@
  * @return	Current value of Primary Context Register.
  */
-static inline uint64_t mmu_primary_context_read(void)
+NO_TRACE static inline uint64_t mmu_primary_context_read(void)
 {
 	return asi_u64_read(ASI_PRIMARY_CONTEXT_REG, VA_PRIMARY_CONTEXT_REG);
 }
- 
+
 /** Write MMU Primary Context Register.
  *
  * @param v	New value of Primary Context Register.
  */
-static inline void mmu_primary_context_write(uint64_t v)
+NO_TRACE static inline void mmu_primary_context_write(uint64_t v)
 {
 	asi_u64_write(ASI_PRIMARY_CONTEXT_REG, VA_PRIMARY_CONTEXT_REG, v);
 }
- 
+
 /** Read MMU Secondary Context Register.
  *
  * @return	Current value of Secondary Context Register.
  */
-static inline uint64_t mmu_secondary_context_read(void)
+NO_TRACE static inline uint64_t mmu_secondary_context_read(void)
 {
 	return asi_u64_read(ASI_SECONDARY_CONTEXT_REG, VA_SECONDARY_CONTEXT_REG);
 }
- 
+
 /** Write MMU Secondary Context Register.
  *
  * @param v	New value of Secondary Context Register.
  */
-static inline void mmu_secondary_context_write(uint64_t v)
+NO_TRACE static inline void mmu_secondary_context_write(uint64_t v)
 {
 	asi_u64_write(ASI_SECONDARY_CONTEXT_REG, VA_SECONDARY_CONTEXT_REG, v);
@@ -126,5 +126,5 @@
  * @param mmu_flag	MMU_FLAG_DTLB, MMU_FLAG_ITLB or a combination of both
  */
-static inline void mmu_demap_ctx(int context, int mmu_flag) {
+NO_TRACE static inline void mmu_demap_ctx(int context, int mmu_flag) {
 	__hypercall_fast4(MMU_DEMAP_CTX, 0, 0, context, mmu_flag);
 }
@@ -137,5 +137,5 @@
  * @param mmu_flag	MMU_FLAG_DTLB, MMU_FLAG_ITLB or a combination of both
  */
-static inline void mmu_demap_page(uintptr_t vaddr, int context, int mmu_flag) {
+NO_TRACE static inline void mmu_demap_page(uintptr_t vaddr, int context, int mmu_flag) {
 	__hypercall_fast5(MMU_DEMAP_PAGE, 0, 0, vaddr, context, mmu_flag);
 }
Index: kernel/arch/sparc64/include/mm/tlb.h
===================================================================
--- kernel/arch/sparc64/include/mm/tlb.h	(revision b97b348a7bdc9e9697abe5dcd02f197f8ff5053f)
+++ kernel/arch/sparc64/include/mm/tlb.h	(revision fef504a2ec75b492fbfc942a4a1caa99b045fd64)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup sparc64mm	
+/** @addtogroup sparc64mm
  * @{
  */
@@ -36,9 +36,12 @@
 #define KERN_sparc64_TLB_H_
 
+#if defined (SUN4U)
 
-#if defined (SUN4U)
 #include <arch/mm/sun4u/tlb.h>
+
 #elif defined (SUN4V)
+
 #include <arch/mm/sun4v/tlb.h>
+
 #endif