Index: kernel/arch/arm32/include/asm.h =================================================================== --- kernel/arch/arm32/include/asm.h (revision 22a28a696141d62f28e48ed72d1d255ff519795c) +++ kernel/arch/arm32/include/asm.h (revision fef504a2ec75b492fbfc942a4a1caa99b045fd64) @@ -41,36 +41,37 @@ #include #include +#include /** No such instruction on ARM to sleep CPU. */ -static inline void cpu_sleep(void) +NO_TRACE static inline void cpu_sleep(void) { } -static inline void pio_write_8(ioport8_t *port, uint8_t v) +NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v) { *port = v; } -static inline void pio_write_16(ioport16_t *port, uint16_t v) +NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v) { *port = v; } -static inline void pio_write_32(ioport32_t *port, uint32_t v) +NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v) { *port = v; } -static inline uint8_t pio_read_8(ioport8_t *port) +NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port) { return *port; } -static inline uint16_t pio_read_16(ioport16_t *port) +NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port) { return *port; } -static inline uint32_t pio_read_32(ioport32_t *port) +NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port) { return *port; @@ -84,7 +85,8 @@ * */ -static inline uintptr_t get_stack_base(void) +NO_TRACE static inline uintptr_t get_stack_base(void) { uintptr_t v; + asm volatile ( "and %[v], sp, %[size]\n" @@ -92,4 +94,5 @@ : [size] "r" (~(STACK_SIZE - 1)) ); + return v; } Index: kernel/arch/arm32/include/atomic.h =================================================================== --- kernel/arch/arm32/include/atomic.h (revision 22a28a696141d62f28e48ed72d1d255ff519795c) +++ kernel/arch/arm32/include/atomic.h (revision fef504a2ec75b492fbfc942a4a1caa99b045fd64) @@ -38,4 +38,5 @@ #include +#include /** Atomic addition. @@ -47,5 +48,6 @@ * */ -static inline atomic_count_t atomic_add(atomic_t *val, atomic_count_t i) +NO_TRACE static inline atomic_count_t atomic_add(atomic_t *val, + atomic_count_t i) { /* @@ -66,5 +68,5 @@ * */ -static inline void atomic_inc(atomic_t *val) +NO_TRACE static inline void atomic_inc(atomic_t *val) { atomic_add(val, 1); @@ -76,5 +78,5 @@ * */ -static inline void atomic_dec(atomic_t *val) { +NO_TRACE static inline void atomic_dec(atomic_t *val) { atomic_add(val, -1); } @@ -86,5 +88,5 @@ * */ -static inline atomic_count_t atomic_preinc(atomic_t *val) +NO_TRACE static inline atomic_count_t atomic_preinc(atomic_t *val) { return atomic_add(val, 1); @@ -97,5 +99,5 @@ * */ -static inline atomic_count_t atomic_predec(atomic_t *val) +NO_TRACE static inline atomic_count_t atomic_predec(atomic_t *val) { return atomic_add(val, -1); @@ -108,5 +110,5 @@ * */ -static inline atomic_count_t atomic_postinc(atomic_t *val) +NO_TRACE static inline atomic_count_t atomic_postinc(atomic_t *val) { return atomic_add(val, 1) - 1; @@ -119,5 +121,5 @@ * */ -static inline atomic_count_t atomic_postdec(atomic_t *val) +NO_TRACE static inline atomic_count_t atomic_postdec(atomic_t *val) { return atomic_add(val, -1) + 1; Index: kernel/arch/arm32/include/cycle.h =================================================================== --- kernel/arch/arm32/include/cycle.h (revision 22a28a696141d62f28e48ed72d1d255ff519795c) +++ kernel/arch/arm32/include/cycle.h (revision fef504a2ec75b492fbfc942a4a1caa99b045fd64) @@ -37,11 +37,14 @@ #define KERN_arm32_CYCLE_H_ -/** Returns count of CPU cycles. +#include + +/** Return count of CPU cycles. * - * No such instruction on ARM to get count of cycles. + * No such instruction on ARM to get count of cycles. * - * @return Count of CPU cycles. + * @return Count of CPU cycles. + * */ -static inline uint64_t get_cycle(void) +NO_TRACE static inline uint64_t get_cycle(void) { return 0; Index: kernel/arch/arm32/include/exception.h =================================================================== --- kernel/arch/arm32/include/exception.h (revision 22a28a696141d62f28e48ed72d1d255ff519795c) +++ kernel/arch/arm32/include/exception.h (revision fef504a2ec75b492fbfc942a4a1caa99b045fd64) @@ -40,4 +40,5 @@ #include #include +#include /** If defined, forces using of high exception vectors. */ @@ -45,17 +46,17 @@ #ifdef HIGH_EXCEPTION_VECTORS - #define EXC_BASE_ADDRESS 0xffff0000 + #define EXC_BASE_ADDRESS 0xffff0000 #else - #define EXC_BASE_ADDRESS 0x0 + #define EXC_BASE_ADDRESS 0x0 #endif /* Exception Vectors */ -#define EXC_RESET_VEC (EXC_BASE_ADDRESS + 0x0) -#define EXC_UNDEF_INSTR_VEC (EXC_BASE_ADDRESS + 0x4) -#define EXC_SWI_VEC (EXC_BASE_ADDRESS + 0x8) -#define EXC_PREFETCH_ABORT_VEC (EXC_BASE_ADDRESS + 0xc) -#define EXC_DATA_ABORT_VEC (EXC_BASE_ADDRESS + 0x10) -#define EXC_IRQ_VEC (EXC_BASE_ADDRESS + 0x18) -#define EXC_FIQ_VEC (EXC_BASE_ADDRESS + 0x1c) +#define EXC_RESET_VEC (EXC_BASE_ADDRESS + 0x0) +#define EXC_UNDEF_INSTR_VEC (EXC_BASE_ADDRESS + 0x4) +#define EXC_SWI_VEC (EXC_BASE_ADDRESS + 0x8) +#define EXC_PREFETCH_ABORT_VEC (EXC_BASE_ADDRESS + 0xc) +#define EXC_DATA_ABORT_VEC (EXC_BASE_ADDRESS + 0x10) +#define EXC_IRQ_VEC (EXC_BASE_ADDRESS + 0x18) +#define EXC_FIQ_VEC (EXC_BASE_ADDRESS + 0x1c) /* Exception numbers */ @@ -68,12 +69,11 @@ #define EXC_FIQ 6 - /** Kernel stack pointer. * * It is set when thread switches to user mode, * and then used for exception handling. + * */ extern uintptr_t supervisor_sp; - /** Temporary exception stack pointer. @@ -81,7 +81,7 @@ * Temporary stack is used in exceptions handling routines * before switching to thread's kernel stack. + * */ extern uintptr_t exc_stack; - /** Struct representing CPU state saved when an exception occurs. */ @@ -90,5 +90,5 @@ uint32_t sp; uint32_t lr; - + uint32_t r0; uint32_t r1; @@ -104,38 +104,36 @@ uint32_t fp; uint32_t r12; - + uint32_t pc; } istate_t; - -/** Sets Program Counter member of given istate structure. +/** Set Program Counter member of given istate structure. * - * @param istate istate structure + * @param istate istate structure * @param retaddr new value of istate's PC member + * */ -static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr) +NO_TRACE static inline void istate_set_retaddr(istate_t *istate, + uintptr_t retaddr) { - istate->pc = retaddr; + istate->pc = retaddr; } - -/** Returns true if exception happened while in userspace. */ -static inline int istate_from_uspace(istate_t *istate) +/** Return true if exception happened while in userspace. */ +NO_TRACE static inline int istate_from_uspace(istate_t *istate) { - return (istate->spsr & STATUS_REG_MODE_MASK) == USER_MODE; + return (istate->spsr & STATUS_REG_MODE_MASK) == USER_MODE; } - -/** Returns Program Counter member of given istate structure. */ -static inline unative_t istate_get_pc(istate_t *istate) +/** Return Program Counter member of given istate structure. */ +NO_TRACE static inline unative_t istate_get_pc(istate_t *istate) { - return istate->pc; + return istate->pc; } -static inline unative_t istate_get_fp(istate_t *istate) +NO_TRACE static inline unative_t istate_get_fp(istate_t *istate) { return istate->fp; } - extern void install_exception_handlers(void); @@ -149,5 +147,4 @@ extern void swi_exception_entry(void); - #endif Index: kernel/arch/arm32/include/faddr.h =================================================================== --- kernel/arch/arm32/include/faddr.h (revision 22a28a696141d62f28e48ed72d1d255ff519795c) +++ kernel/arch/arm32/include/faddr.h (revision fef504a2ec75b492fbfc942a4a1caa99b045fd64) @@ -27,5 +27,5 @@ */ -/** @addtogroup arm32 +/** @addtogroup arm32 * @{ */ @@ -42,6 +42,7 @@ * * @param fptr Function pointer. + * */ -#define FADDR(fptr) ((uintptr_t) (fptr)) +#define FADDR(fptr) ((uintptr_t) (fptr)) #endif Index: kernel/arch/arm32/include/interrupt.h =================================================================== --- kernel/arch/arm32/include/interrupt.h (revision 22a28a696141d62f28e48ed72d1d255ff519795c) +++ kernel/arch/arm32/include/interrupt.h (revision fef504a2ec75b492fbfc942a4a1caa99b045fd64) @@ -41,9 +41,8 @@ /** Initial size of exception dispatch table. */ -#define IVT_ITEMS 6 +#define IVT_ITEMS 6 /** Index of the first item in exception dispatch table. */ -#define IVT_FIRST 0 - +#define IVT_FIRST 0 extern void interrupt_init(void); @@ -54,5 +53,4 @@ extern bool interrupts_disabled(void); - #endif Index: kernel/arch/arm32/include/mm/page.h =================================================================== --- kernel/arch/arm32/include/mm/page.h (revision 22a28a696141d62f28e48ed72d1d255ff519795c) +++ kernel/arch/arm32/include/mm/page.h (revision fef504a2ec75b492fbfc942a4a1caa99b045fd64) @@ -27,5 +27,5 @@ */ -/** @addtogroup arm32mm +/** @addtogroup arm32mm * @{ */ @@ -40,4 +40,5 @@ #include #include +#include #define PAGE_WIDTH FRAME_WIDTH @@ -192,7 +193,8 @@ /** Sets the address of level 0 page table. * - * @param pt Pointer to the page table to set. - */ -static inline void set_ptl0_addr(pte_t *pt) + * @param pt Pointer to the page table to set. + * + */ +NO_TRACE static inline void set_ptl0_addr(pte_t *pt) { asm volatile ( @@ -205,12 +207,13 @@ /** Returns level 0 page table entry flags. * - * @param pt Level 0 page table. - * @param i Index of the entry to return. - */ -static inline int get_pt_level0_flags(pte_t *pt, size_t i) + * @param pt Level 0 page table. + * @param i Index of the entry to return. + * + */ +NO_TRACE static inline int get_pt_level0_flags(pte_t *pt, size_t i) { pte_level0_t *p = &pt[i].l0; int np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT); - + return (np << PAGE_PRESENT_SHIFT) | (1 << PAGE_USER_SHIFT) | (1 << PAGE_READ_SHIFT) | (1 << PAGE_WRITE_SHIFT) | @@ -220,14 +223,15 @@ /** Returns level 1 page table entry flags. * - * @param pt Level 1 page table. - * @param i Index of the entry to return. - */ -static inline int get_pt_level1_flags(pte_t *pt, size_t i) + * @param pt Level 1 page table. + * @param i Index of the entry to return. + * + */ +NO_TRACE static inline int get_pt_level1_flags(pte_t *pt, size_t i) { pte_level1_t *p = &pt[i].l1; - + int dt = p->descriptor_type; int ap = p->access_permission_0; - + return ((dt == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) | ((ap == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT) | @@ -241,15 +245,15 @@ } - /** Sets flags of level 0 page table entry. * - * @param pt level 0 page table - * @param i index of the entry to be changed - * @param flags new flags - */ -static inline void set_pt_level0_flags(pte_t *pt, size_t i, int flags) + * @param pt level 0 page table + * @param i index of the entry to be changed + * @param flags new flags + * + */ +NO_TRACE static inline void set_pt_level0_flags(pte_t *pt, size_t i, int flags) { pte_level0_t *p = &pt[i].l0; - + if (flags & PAGE_NOT_PRESENT) { p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; @@ -262,5 +266,5 @@ p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE; p->should_be_zero = 0; - } + } } @@ -268,13 +272,14 @@ /** Sets flags of level 1 page table entry. * - * We use same access rights for the whole page. When page is not preset we - * store 1 in acess_rigts_3 so that at least one bit is 1 (to mark correct - * page entry, see #PAGE_VALID_ARCH). - * - * @param pt Level 1 page table. - * @param i Index of the entry to be changed. - * @param flags New flags. - */ -static inline void set_pt_level1_flags(pte_t *pt, size_t i, int flags) + * We use same access rights for the whole page. When page + * is not preset we store 1 in acess_rigts_3 so that at least + * one bit is 1 (to mark correct page entry, see #PAGE_VALID_ARCH). + * + * @param pt Level 1 page table. + * @param i Index of the entry to be changed. + * @param flags New flags. + * + */ +NO_TRACE static inline void set_pt_level1_flags(pte_t *pt, size_t i, int flags) { pte_level1_t *p = &pt[i].l1; @@ -287,12 +292,12 @@ p->access_permission_3 = p->access_permission_0; } - + p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0; - + /* default access permission */ p->access_permission_0 = p->access_permission_1 = p->access_permission_2 = p->access_permission_3 = PTE_AP_USER_NO_KERNEL_RW; - + if (flags & PAGE_USER) { if (flags & PAGE_READ) { Index: kernel/arch/arm32/include/mm/tlb.h =================================================================== --- kernel/arch/arm32/include/mm/tlb.h (revision 22a28a696141d62f28e48ed72d1d255ff519795c) +++ kernel/arch/arm32/include/mm/tlb.h (revision fef504a2ec75b492fbfc942a4a1caa99b045fd64) @@ -27,5 +27,5 @@ */ -/** @addtogroup arm32mm +/** @addtogroup arm32mm * @{ */