Index: kernel/genarch/include/genarch/drivers/am335x/irc.h =================================================================== --- kernel/genarch/include/genarch/drivers/am335x/irc.h (revision 5bf69ac6ffa4fe1a737fc18458a2129f6c61ec96) +++ kernel/genarch/include/genarch/drivers/am335x/irc.h (revision feeac0d8cd6e0ce736779bc5f1dc701c5cf42ba6) @@ -38,214 +38,14 @@ #define KERN_AM335x_IRQC_H_ -#define AM335x_IRC_BASE_ADDRESS 0x48200000 -#define AM335x_IRC_SIZE 4096 +#define AM335x_IRC_BASE_ADDRESS 0x48200000 +#define AM335x_IRC_SIZE 4096 -#define AM335x_IRC_IRQ_COUNT 128 +#define AM335x_IRC_IRQ_COUNT 128 +#define AM335x_IRC_IRQ_GROUPS_COUNT 4 -#include +#define OMAP_IRC_IRQ_COUNT AM335x_IRC_IRQ_COUNT +#define OMAP_IRC_IRQ_GROUPS_COUNT AM335x_IRC_IRQ_GROUPS_COUNT -typedef struct { - const ioport32_t revision; -#define AM335x_IRC_REV_MASK 0xFF - - const uint8_t padd0[12]; - - /* This register controls the various parameters - * of the OCP interface. - */ - ioport32_t sysconfig; -#define AM335x_IRC_SYSCONFIG_AUTOIDLE_FLAG (1 << 0) -#define AM335x_IRC_SYSCONFIG_SOFTRESET_FLAG (1 << 1) - - /* This register provides status information about the module */ - const ioport32_t sysstatus; -#define AM335x_IRC_SYSSTATUS_RESET_DONE_FLAG (1 << 0) - - const uint8_t padd1[40]; - - /* This register supplies the currently active IRQ interrupt number */ - ioport32_t sir_irq; -#define AM335x_IRC_SIR_IRQ_ACTIVEIRQ_MASK 0x7F -#define AM335x_IRC_SIR_IRQ_SPURIOUSIRQFLAG_MASK 0xFFFFFFF8 - - /* This register supplies the currently active FIQ interrupt number */ - const ioport32_t sir_fiq; -#define AM335x_IRC_FIQ_IRQ_ACTIVEFIQ_MASK 0x7F -#define AM335x_IRC_FIQ_IRQ_SPURIOUSFIQFLAG_MASK 0xFFFFFFF8 - - /* This register contains the new interrupt agreement bits */ - ioport32_t control; -#define AM335x_IRC_CONTROL_NEWIRQAGR_FLAG (1 << 0) -#define AM335x_IRC_CONTROL_NEWFIQAGR_FLAG (1 << 1) - - /* This register controls protection of the other registers. - * This register can only be accessed in priviledged mode, regardless - * of the current value of the protection bit. - */ - ioport32_t protection; -#define AM335x_IRC_PROTECTION_FLAG (1 << 0) - - /* This register controls the clock auto-idle for the functional - * clock and the input synchronizers. - */ - ioport32_t idle; -#define AM335x_IRC_IDLE_FUNCIDLE_FLAG (1 << 0) -#define AM335x_IRC_IDLE_TURBO_FLAG (1 << 1) - - const uint8_t padd2[12]; - - /* This register supplies the currently active IRQ priority level */ - const ioport32_t irq_priority; -#define AM335x_IRC_IRQ_PRIORITY_IRQPRIORITY_MASK 0x7F -#define AM335x_IRC_IRQ_PRIORITY_SPURIOUSIRQFLAG_MASK 0xFFFFFFF8 - - /* This register supplies the currently active FIQ priority level */ - const ioport32_t fiq_priority; -#define AM335x_IRC_FIQ_PRIORITY_FIQPRIORITY_MASK 0x7F -#define AM335x_IRC_FIQ_PRIORITY_SPURIOUSIRQFLAG_MASK 0xFFFFFFF8 - - /* This register sets the priority threshold */ - ioport32_t threshold; -#define AM335x_IRC_THRESHOLD_PRIORITYTHRESHOLD_MASK 0xFF -#define AM335x_IRC_THRESHOLD_PRIORITYTHRESHOLD_ENABLED 0x00 -#define AM335x_IRC_THRESHOLD_PRIORITYTHRESHOLD_DISABLED 0xFF - - const uint8_t padd[20]; - - struct { - /* Raw interrupt input status before masking */ - const ioport32_t itr; - - /* Interrupt mask */ - ioport32_t mir; - - /* This register is used to clear the interrupt mask bits, - * Write 1 clears the mask bit to 0. - */ - ioport32_t mir_clear; - - /* This register is used to set the interrupt mask bits, - * Write 1 sets the mask bit to 1. - */ - ioport32_t mir_set; - - /* This register is used to set the software interrupt bits, - * it is also used to read the current active software - * interrupts. - * Write 1 sets the software interrups bits to 1. - */ - ioport32_t isr_set; - - /* This register is used to clear the software interrups bits. - * Write 1 clears the software interrupt bits to 0. - */ - ioport32_t isr_clear; - - /* This register contains the IRQ status after masking. */ - const ioport32_t pending_irq; - - /* This register contains the FIQ status after masking. */ - const ioport32_t pending_fiq; - } interrupts[4]; - - /* These registers contain the priority for the interrups and - * the FIQ/IRQ steering. - */ - ioport32_t ilr[AM335x_IRC_IRQ_COUNT]; -/* 0 = Interrupt routed to IRQ, 1 = interrupt routed to FIQ */ -#define AM335x_IRC_ILR_FIQNIRQ_FLAG (1 << 0) -#define AM335x_IRC_ILR_PRIORITY_MASK 0x3F -#define AM335x_IRC_ILR_PRIORITY_SHIFT 2 - -} am335x_irc_regs_t; - -static inline void am335x_irc_init(am335x_irc_regs_t *regs) -{ - int i; - - /* Initialization sequence */ - - /* 1 - Program the SYSCONFIG register: if necessary, enable the - * autogating by setting the AUTOIDLE bit. - */ - regs->sysconfig &= ~AM335x_IRC_SYSCONFIG_AUTOIDLE_FLAG; - - /* 2 - Program the IDLE register: if necessary, disable functional - * clock autogating or enable synchronizer autogating by setting - * the FUNCIDLE bit or the TURBO bit accordingly. - */ - regs->idle &= ~AM335x_IRC_IDLE_FUNCIDLE_FLAG; - regs->idle &= ~AM335x_IRC_IDLE_TURBO_FLAG; - - /* 3 - Program ILRm register for each interrupt line: Assign a - * priority level and set the FIQNIRQ bit for an FIQ interrupt - * (by default, interrupts are mapped to IRQ and - * priority is 0 (highest). - */ - - for (i = 0; i < AM335x_IRC_IRQ_COUNT; ++i) - regs->ilr[i] = 0; - - /* 4 - Program the MIRn register: Enable interrupts (by default, - * all interrupt lines are masked). - */ - for (i = 0; i < 4; ++i) - regs->interrupts[i].mir_set = 0xFFFFFFFF; -} - -/** Get the currently active IRQ interrupt number - * - * @param regs Pointer to the irc memory mapped registers - * - * @return The active IRQ interrupt number - */ -static inline unsigned am335x_irc_inum_get(am335x_irc_regs_t *regs) -{ - return regs->sir_irq & AM335x_IRC_SIR_IRQ_ACTIVEIRQ_MASK; -} - -/** Reset IRQ output and enable new IRQ generation - * - * @param regs Pointer to the irc memory mapped registers - */ -static inline void am335x_irc_irq_ack(am335x_irc_regs_t *regs) -{ - regs->control = AM335x_IRC_CONTROL_NEWIRQAGR_FLAG; -} - -/** Reset FIQ output and enable new FIQ generation - * - * @param regs Pointer to the irc memory mapped registers - */ -static inline void am335x_irc_fiq_ack(am335x_irc_regs_t *regs) -{ - regs->control = AM335x_IRC_CONTROL_NEWFIQAGR_FLAG; -} - -/** Clear an interrupt mask bit - * - * @param regs Pointer to the irc memory mapped registers - * @param inum The interrupt to be enabled - */ -static inline void am335x_irc_enable(am335x_irc_regs_t *regs, unsigned inum) -{ - ASSERT(inum < AM335x_IRC_IRQ_COUNT); - const unsigned set = inum / 32; - const unsigned pos = inum % 32; - regs->interrupts[set].mir_clear = (1 << pos); -} - -/** Set an interrupt mask bit - * - * @param regs Pointer to the irc memory mapped registers - * @param inum The interrupt to be disabled - */ -static inline void am335x_irc_disable(am335x_irc_regs_t *regs, unsigned inum) -{ - ASSERT(inum < AM335x_IRC_IRQ_COUNT); - const unsigned set = inum / 32; - const unsigned pos = inum % 32; - regs->interrupts[set].mir_set = (1 << pos); -} +#include #endif Index: kernel/genarch/include/genarch/drivers/amdm37x/irc.h =================================================================== --- kernel/genarch/include/genarch/drivers/amdm37x/irc.h (revision 5bf69ac6ffa4fe1a737fc18458a2129f6c61ec96) +++ kernel/genarch/include/genarch/drivers/amdm37x/irc.h (revision feeac0d8cd6e0ce736779bc5f1dc701c5cf42ba6) @@ -38,165 +38,14 @@ /* AMDM37x TRM p. 1079 */ -#define AMDM37x_IRC_BASE_ADDRESS 0x48200000 -#define AMDM37x_IRC_SIZE 4096 +#define AMDM37x_IRC_BASE_ADDRESS 0x48200000 +#define AMDM37x_IRC_SIZE 4096 -#define AMDM37x_IRC_IRQ_COUNT 96 +#define AMDM37x_IRC_IRQ_COUNT 96 +#define AMDM37x_IRC_IRQ_GROUPS_COUNT 3 -#include +#define OMAP_IRC_IRQ_COUNT AMDM37x_IRC_IRQ_COUNT +#define OMAP_IRC_IRQ_GROUPS_COUNT AMDM37x_IRC_IRQ_GROUPS_COUNT -typedef struct { - const ioport32_t revision; /**< Revision */ -#define AMDM37x_IRC_REV_MASK (0xff) - - uint8_t padd0_[12]; - - ioport32_t sysconfig; /**< SYS config */ -#define AMDM37x_IRC_SYSCONFIG_AUTOIDLE_FLAG (1 << 0) -#define AMDM37x_IRC_SYSCONFIG_SOFTRESET_FLAG (1 << 1) - - const ioport32_t sysstatus; /**< SYS status */ -#define AMDM37x_IRC_SYSSTATUS_RESET_DONE_FLAG (1 << 0) - - uint8_t padd1_[40]; - - const ioport32_t sir_irq; /**< Currently active irq number */ -#define AMDM37x_IRC_SIR_IRQ_ACTIVEIRQ_MASK (0x7f) -#define AMDM37x_IRC_SIR_IRQ_SPURIOUSIRQFLAG_MASK (0xfffffff8) - - const ioport32_t sir_fiq; -#define AMDM37x_IRC_SIR_FIQ_ACTIVEIRQ_MASK (0x7f) -#define AMDM37x_IRC_SIR_FIQ_SPURIOUSIRQFLAG_MASK (0xfffffff8) - - ioport32_t control; /**< New interrupt agreement. */ -#define AMDM37x_IRC_CONTROL_NEWIRQAGR_FLAG (1 << 0) -#define AMDM37x_IRC_CONTROL_NEWFIQAGR_FLAG (1 << 1) - - ioport32_t protection; /**< Protect other registers. */ -#define AMDM37x_IRC_PROTECTION_PROETCTION_FLAG (1 << 0) - - ioport32_t idle; /**< Idle and autogating */ -#define AMDM37x_IRC_IDLE_FUNCIDLE_FLAG (1 << 0) -#define AMDM37x_IRC_IDLE_TURBO_FLAG (1 << 1) - - uint8_t padd2_[12]; - - ioport32_t irq_priority; /**< Active IRQ priority */ -#define AMDM37x_IRC_IRQ_PRIORITY_IRQPRIORITY_MASK (0x7f) -#define AMDM37x_IRC_IRQ_PRIORITY_SPURIOUSIRQFLAG_MASK (0xfffffff8) - - ioport32_t fiq_priority; /**< Active FIQ priority */ -#define AMDM37x_IRC_FIQ_PRIORITY_FIQPRIORITY_MASK (0x7f) -#define AMDM37x_IRC_FIQ_PRIORITY_SPURIOUSFIQFLAG_MASK (0xfffffff8) - - ioport32_t threshold; /**< Priority threshold */ -#define AMDM37x_IRC_THRESHOLD_PRIORITYTHRESHOLD_MASK (0xff) -#define AMDM37x_IRC_THRESHOLD_PRIORITYTHRESHOLD_ENABLED (0x00) -#define AMDM37x_IRC_THRESHOLD_PRIORITYTHRESHOLD_DISABLED (0xff) - - uint8_t padd3__[20]; - - struct { - const ioport32_t itr; /**< Interrupt input status before masking */ - ioport32_t mir; /**< Interrupt mask */ - ioport32_t mir_clear; /**< Clear mir mask bits */ - ioport32_t mir_set; /**< Set mir mask bits */ - ioport32_t isr_set; /**< Set software interrupt bits */ - ioport32_t isr_clear; /**< Clear software interrupt bits */ - const ioport32_t pending_irq; /**< IRQ status after masking */ - const ioport32_t pending_fiq; /**< FIQ status after masking */ - } interrupts[3]; - - uint8_t padd4_[32]; - - ioport32_t ilr[96]; /**< FIQ/IRQ steering */ -#define AMDM37x_IRC_ILR_FIQNIRQ (1 << 0) -#define AMDM37x_IRC_ILR_PRIORITY_MASK (0x3f) -#define AMDM37x_IRC_ILR_PRIORITY_SHIFT (2) - -} amdm37x_irc_regs_t; - -static inline void amdm37x_irc_dump(amdm37x_irc_regs_t *regs) -{ -#define DUMP_REG(name) \ - printf("%s %p(%x).\n", #name, ®s->name, regs->name); - - DUMP_REG(revision); - DUMP_REG(sysconfig); - DUMP_REG(sysstatus); - DUMP_REG(sir_irq); - DUMP_REG(sir_fiq); - DUMP_REG(control); - DUMP_REG(protection); - DUMP_REG(idle); - DUMP_REG(irq_priority); - DUMP_REG(fiq_priority); - DUMP_REG(threshold); - - for (int i = 0; i < 3; ++i) { - DUMP_REG(interrupts[i].itr); - DUMP_REG(interrupts[i].mir); - DUMP_REG(interrupts[i].isr_set); - DUMP_REG(interrupts[i].pending_irq); - DUMP_REG(interrupts[i].pending_fiq); - } - for (int i = 0; i < AMDM37x_IRC_IRQ_COUNT; ++i) { - DUMP_REG(ilr[i]); - } - -#undef DUMP_REG -} - -static inline void amdm37x_irc_init(amdm37x_irc_regs_t *regs) -{ - /* AMDM37x TRM sec 12.5.1 p. 2425 */ - /* Program system config register */ - //TODO enable this when you know the meaning - //regs->sysconfig |= AMDM37x_IRC_SYSCONFIG_AUTOIDLE_FLAG; - - /* Program idle register */ - //TODO enable this when you know the meaning - //regs->sysconfig |= AMDM37x_IRC_IDLE_TURBO_FLAG; - - /* Program ilr[m] assign priority, decide fiq */ - for (unsigned i = 0; i < AMDM37x_IRC_IRQ_COUNT; ++i) { - regs->ilr[i] = 0; /* highest prio(default) route to irq */ - } - - /* Disable all interrupts */ - regs->interrupts[0].mir_set = 0xffffffff; - regs->interrupts[1].mir_set = 0xffffffff; - regs->interrupts[2].mir_set = 0xffffffff; -} - -static inline unsigned amdm37x_irc_inum_get(amdm37x_irc_regs_t *regs) -{ - return regs->sir_irq & AMDM37x_IRC_SIR_IRQ_ACTIVEIRQ_MASK; -} - -static inline void amdm37x_irc_irq_ack(amdm37x_irc_regs_t *regs) -{ - regs->control = AMDM37x_IRC_CONTROL_NEWIRQAGR_FLAG; -} - -static inline void amdm37x_irc_fiq_ack(amdm37x_irc_regs_t *regs) -{ - regs->control = AMDM37x_IRC_CONTROL_NEWFIQAGR_FLAG; -} - -static inline void amdm37x_irc_enable(amdm37x_irc_regs_t *regs, unsigned inum) -{ - ASSERT(inum < AMDM37x_IRC_IRQ_COUNT); - const unsigned set = inum / 32; - const unsigned pos = inum % 32; - regs->interrupts[set].mir_clear = (1 << pos); -} - -static inline void amdm37x_irc_disable(amdm37x_irc_regs_t *regs, unsigned inum) -{ - ASSERT(inum < AMDM37x_IRC_IRQ_COUNT); - const unsigned set = inum / 32; - const unsigned pos = inum % 32; - regs->interrupts[set].mir_set = (1 << pos); -} +#include #endif