Index: kernel/arch/ppc32/src/mm/tlb.c
===================================================================
--- kernel/arch/ppc32/src/mm/tlb.c	(revision 7b187ef6f8a1aeda140487a35c3664962045e88c)
+++ kernel/arch/ppc32/src/mm/tlb.c	(revision fd723123e15e0acd1e98c618cb1941a5f5354f09)
@@ -228,8 +228,8 @@
 
 
-/** Process Instruction/Data Storage Interrupt
- *
- * @param n		Interrupt vector number.
- * @param istate	Interrupted register context.
+/** Process Instruction/Data Storage Exception
+ *
+ * @param n      Exception vector number.
+ * @param istate Interrupted register context.
  *
  */
@@ -288,8 +288,8 @@
 
 
-/** Process Instruction/Data Storage Interrupt in Real Mode
- *
- * @param n		Interrupt vector number.
- * @param istate	Interrupted register context.
+/** Process Instruction/Data Storage Exception in Real Mode
+ *
+ * @param n      Exception vector number.
+ * @param istate Interrupted register context.
  *
  */
@@ -406,4 +406,38 @@
 	
 	return true;
+}
+
+
+/** Process ITLB/DTLB Miss Exception in Real Mode
+ *
+ *
+ */
+void tlb_refill_real(int n, uint32_t tlbmiss, ptehi_t ptehi, ptelo_t ptelo, istate_t *istate)
+{
+	uint32_t badvaddr = tlbmiss & 0xfffffffc;
+	
+	uint32_t physmem;
+	asm volatile (
+		"mfsprg3 %0\n"
+		: "=r" (physmem)
+	);
+	
+	if ((badvaddr < PA2KA(0)) || (badvaddr >= PA2KA(physmem)))
+		return; // FIXME
+	
+	ptelo.rpn = KA2PA(badvaddr) >> 12;
+	ptelo.wimg = 0;
+	ptelo.pp = 2; // FIXME
+	
+	uint32_t index = 0;
+	asm volatile (
+		"mtspr 981, %0\n"
+		"mtspr 982, %1\n"
+		"tlbld %2\n"
+		"tlbli %2\n"
+		: "=r" (index)
+		: "r" (ptehi),
+		  "r" (ptelo)
+	);
 }