Index: kernel/arch/arm32/src/arm32.c
===================================================================
--- kernel/arch/arm32/src/arm32.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/arm32/src/arm32.c	(revision fd57cf17d12bbe3b41626a0b8708f075134a073e)
@@ -69,5 +69,5 @@
 {
 	init.cnt = min3(bootinfo->cnt, TASKMAP_MAX_RECORDS, CONFIG_INIT_TASKS);
-	
+
 	size_t i;
 	for (i = 0; i < init.cnt; i++) {
@@ -93,5 +93,5 @@
 {
 	machine_init();
-	
+
 	/* Initialize exception dispatch table */
 	exception_init();
@@ -100,5 +100,5 @@
 	/* Initialize Restartable Atomic Sequences support. */
 	ras_init();
-	
+
 	machine_output_init();
 }
@@ -132,5 +132,5 @@
 {
 	uint8_t *stck;
-	
+
 	stck = &THREAD->kstack[STACK_SIZE];
 	supervisor_sp = (uintptr_t) stck;
Index: kernel/arch/arm32/src/asm.S
===================================================================
--- kernel/arch/arm32/src/asm.S	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/arm32/src/asm.S	(revision fd57cf17d12bbe3b41626a0b8708f075134a073e)
@@ -39,10 +39,10 @@
 	mov r5, r0 /* save dst */
 	beq 4f
-	
+
 	1:
 		cmp r2, #0
 		movne ip, #0
 		beq 3f
-	
+
 	2:
 		ldrb r3, [ip, r1]
@@ -51,9 +51,9 @@
 		cmp ip, r2
 		bne 2b
-	
+
 	3:
 		mov r0, r5
 		ldmia sp!, {r4, r5, pc}
-	
+
 	4:
 		add r3, r0, #3
@@ -66,5 +66,5 @@
 		mov lr, #0
 		mov ip, lr
-	
+
 	5:
 		ldr r3, [ip, r1]
@@ -74,5 +74,5 @@
 		add ip, ip, #4
 		bne 5b
-	
+
 	6:
 		ands r4, r2, #3
@@ -82,5 +82,5 @@
 		add ip, r3, r1
 		mov r2, #0
-	
+
 	7:
 		ldrb r3, [r2, ip]
Index: kernel/arch/arm32/src/atomic.c
===================================================================
--- kernel/arch/arm32/src/atomic.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/arm32/src/atomic.c	(revision fd57cf17d12bbe3b41626a0b8708f075134a073e)
@@ -54,13 +54,13 @@
 	 */
 	irq_spinlock_lock(&cas_lock, true);
-	
+
 	void * cur_val = *ptr;
-	
+
 	if (cur_val == expected) {
 		*ptr = new_val;
 	}
-	
+
 	irq_spinlock_unlock(&cas_lock, true);
-	
+
 	return cur_val;
 }
Index: kernel/arch/arm32/src/context.S
===================================================================
--- kernel/arch/arm32/src/context.S	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/arm32/src/context.S	(revision fd57cf17d12bbe3b41626a0b8708f075134a073e)
@@ -54,5 +54,5 @@
 	ldmia r0!, {sp, lr}
 	ldmia r0!, {r4-r11}
-	
+
 	mov r0, #0
 	mov pc, lr
Index: kernel/arch/arm32/src/exc_handler.S
===================================================================
--- kernel/arch/arm32/src/exc_handler.S	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/arm32/src/exc_handler.S	(revision fd57cf17d12bbe3b41626a0b8708f075134a073e)
@@ -97,5 +97,5 @@
 	# Stop stack traces here
 	mov fp, #0
-	
+
 	b 2f
 
Index: kernel/arch/arm32/src/exception.c
===================================================================
--- kernel/arch/arm32/src/exception.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/arm32/src/exception.c	(revision fd57cf17d12bbe3b41626a0b8708f075134a073e)
@@ -71,9 +71,9 @@
 	volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE -
 	    PREFETCH_OFFSET;
-	
+
 	/* make it LDR instruction and store at exception vector */
 	*vector = handler_address_ptr | LDR_OPCODE;
 	smc_coherence(vector);
-	
+
 	/* store handler's address */
 	*(vector + EXC_VECTORS) = handler_addr;
@@ -99,20 +99,20 @@
 	install_handler((unsigned) reset_exception_entry,
 	    (unsigned *) EXC_RESET_VEC);
-	
+
 	install_handler((unsigned) undef_instr_exception_entry,
 	    (unsigned *) EXC_UNDEF_INSTR_VEC);
-	
+
 	install_handler((unsigned) swi_exception_entry,
 	    (unsigned *) EXC_SWI_VEC);
-	
+
 	install_handler((unsigned) prefetch_abort_exception_entry,
 	    (unsigned *) EXC_PREFETCH_ABORT_VEC);
-	
+
 	install_handler((unsigned) data_abort_exception_entry,
 	    (unsigned *) EXC_DATA_ABORT_VEC);
-	
+
 	install_handler((unsigned) irq_exception_entry,
 	    (unsigned *) EXC_IRQ_VEC);
-	
+
 	install_handler((unsigned) fiq_exception_entry,
 	    (unsigned *) EXC_FIQ_VEC);
@@ -140,8 +140,8 @@
 {
 	uint32_t control_reg = SCTLR_read();
-	
+
 	/* switch on the high vectors bit */
 	control_reg |= SCTLR_HIGH_VECTORS_EN_FLAG;
-	
+
 	SCTLR_write(control_reg);
 }
@@ -190,5 +190,5 @@
 #endif
 	install_exception_handlers();
-	
+
 	exc_register(EXC_UNDEF_INSTR, "undefined instruction", true,
 	    (iroutine_t) undef_insn_exception);
Index: kernel/arch/arm32/src/interrupt.c
===================================================================
--- kernel/arch/arm32/src/interrupt.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/arm32/src/interrupt.c	(revision fd57cf17d12bbe3b41626a0b8708f075134a073e)
@@ -49,5 +49,5 @@
 
 	current_status_reg_control_write(STATUS_REG_IRQ_DISABLED_BIT | ipl);
-	
+
 	return ipl;
 }
@@ -62,5 +62,5 @@
 
 	current_status_reg_control_write(ipl & ~STATUS_REG_IRQ_DISABLED_BIT);
-	
+
 	return ipl;
 }
Index: kernel/arch/arm32/src/mach/integratorcp/integratorcp.c
===================================================================
--- kernel/arch/arm32/src/mach/integratorcp/integratorcp.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/arm32/src/mach/integratorcp/integratorcp.c	(revision fd57cf17d12bbe3b41626a0b8708f075134a073e)
@@ -103,5 +103,5 @@
 	*(uint32_t *) ((char *)(icp.hw_map.vga) + 0x1C) = 0x182B;
 	*(uint32_t *) ((char *)(icp.hw_map.cmcr) + 0xC) = 0x33805000;
-	
+
 }
 
@@ -259,5 +259,5 @@
 	uint32_t sources = icp_irqc_get_sources();
 	unsigned int i;
-	
+
 	for (i = 0; i < ICP_IRQC_MAX_IRQ; i++) {
 		if (sources & (1 << i)) {
@@ -295,5 +295,5 @@
 		vga_init = true;
 	}
-	
+
 	fb_properties_t prop = {
 		.addr = ICP_FB,
@@ -304,5 +304,5 @@
 		.visual = VISUAL_RGB_8_8_8_0,
 	};
-	
+
 	outdev_t *fbdev = fb_init(&prop);
 	if (fbdev)
@@ -322,5 +322,5 @@
 	pl050->data = (ioport8_t *) icp.hw_map.kbd_data;
 	pl050->ctrl = (ioport8_t *) icp.hw_map.kbd_ctrl;
-		
+
 	pl050_instance_t *pl050_instance = pl050_init(pl050, ICP_KBD_IRQ);
 	if (pl050_instance) {
Index: kernel/arch/arm32/src/mm/frame.c
===================================================================
--- kernel/arch/arm32/src/mm/frame.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/arm32/src/mm/frame.c	(revision fd57cf17d12bbe3b41626a0b8708f075134a073e)
@@ -49,5 +49,5 @@
 	base = ALIGN_UP(base, FRAME_SIZE);
 	size = ALIGN_DOWN(size, FRAME_SIZE);
-	
+
 	if (!frame_adjust_zone_bounds(low, &base, &size))
 		return;
@@ -64,5 +64,5 @@
 			    ZONE_AVAILABLE | ZONE_HIGHMEM);
 	}
-	
+
 }
 
Index: kernel/arch/arm32/src/mm/page.c
===================================================================
--- kernel/arch/arm32/src/mm/page.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/arm32/src/mm/page.c	(revision fd57cf17d12bbe3b41626a0b8708f075134a073e)
@@ -56,5 +56,5 @@
 
 	page_table_lock(AS_KERNEL, true);
-	
+
 	/* Kernel identity mapping */
 	//FIXME: We need to consider the possibility that
@@ -66,5 +66,5 @@
 	    cur += FRAME_SIZE)
 		page_mapping_insert(AS_KERNEL, PA2KA(cur), cur, flags);
-	
+
 #ifdef HIGH_EXCEPTION_VECTORS
 	/* Create mapping for exception table at high offset */
@@ -76,7 +76,7 @@
 
 	page_table_unlock(AS_KERNEL, true);
-	
+
 	as_switch(NULL, AS_KERNEL);
-	
+
 	boot_page_table_free();
 }
Index: kernel/arch/arm32/src/ras.c
===================================================================
--- kernel/arch/arm32/src/ras.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/arm32/src/ras.c	(revision fd57cf17d12bbe3b41626a0b8708f075134a073e)
@@ -55,8 +55,8 @@
 	if (!frame)
 		frame = frame_alloc(1, FRAME_LOWMEM, 0);
-	
+
 	ras_page = (uintptr_t *) km_map(frame,
 	    PAGE_SIZE, PAGE_READ | PAGE_WRITE | PAGE_USER | PAGE_CACHEABLE);
-	
+
 	memsetb(ras_page, PAGE_SIZE, 0);
 	ras_page[RAS_START] = 0;
Index: kernel/arch/arm32/src/start.S
===================================================================
--- kernel/arch/arm32/src/start.S	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/arm32/src/start.S	(revision fd57cf17d12bbe3b41626a0b8708f075134a073e)
@@ -60,9 +60,9 @@
 	orr r3, r4, #0x13
 	msr cpsr_c, r3
-	
+
 	ldr sp, =temp_stack
-	
+
 	bl arm32_pre_main
-	
+
 	#
 	# Create the first stack frame.