Index: arch/mips32/include/cp0.h
===================================================================
--- arch/mips32/include/cp0.h	(revision e07fe0c1834e24beaa907000673e1e37acbc7c7d)
+++ arch/mips32/include/cp0.h	(revision fbe058f936b3f872b943c3aaef6878e7ee038c8e)
@@ -81,11 +81,11 @@
 extern __u32 cp0_badvaddr_read(void);
 
-extern volatile __u32 cp0_count_read(void);
+extern __u32 cp0_count_read(void);
 extern void cp0_count_write(__u32 val);
 
-extern volatile __u32 cp0_entry_hi_read(void);
+extern __u32 cp0_entry_hi_read(void);
 extern void cp0_entry_hi_write(__u32 val);
 
-extern volatile __u32 cp0_compare_read(void);
+extern __u32 cp0_compare_read(void);
 extern void cp0_compare_write(__u32 val);
 
Index: arch/mips32/src/cpu/cpu.c
===================================================================
--- arch/mips32/src/cpu/cpu.c	(revision e07fe0c1834e24beaa907000673e1e37acbc7c7d)
+++ arch/mips32/src/cpu/cpu.c	(revision fbe058f936b3f872b943c3aaef6878e7ee038c8e)
@@ -109,5 +109,5 @@
 		for (i=0;imp_data80[i].vendor;i++)
 			;
-		if (m->arch.imp_num & 0x7f >= i) {
+		if ((m->arch.imp_num & 0x7f) >= i) {
 			printf("imp=%d\n",m->arch.imp_num);
 			return;
Index: arch/mips32/src/drivers/arc.c
===================================================================
--- arch/mips32/src/drivers/arc.c	(revision e07fe0c1834e24beaa907000673e1e37acbc7c7d)
+++ arch/mips32/src/drivers/arc.c	(revision fbe058f936b3f872b943c3aaef6878e7ee038c8e)
@@ -218,4 +218,22 @@
 }
 
+static char arc_read(chardev_t *dev)
+{
+	char ch;
+	__u32 count;
+	long result;
+
+	result = arc_entry->read(0, &ch, 1, &count);
+	if (result || count!=1) {
+		printf("Error reading from ARC keyboard.\n");
+		cpu_halt();
+	}
+	if (ch == '\r')
+		return '\n';
+	if (ch == 0x7f)
+		return '\b';
+	return ch;
+}
+
 static void arc_write(chardev_t *dev, const char ch)
 {
@@ -236,5 +254,6 @@
 	.resume = arc_enable,
 	.suspend = arc_disable,
-	.write = arc_write
+	.write = arc_write,
+	.read = arc_read
 };
 
Index: arch/mips32/src/exception.c
===================================================================
--- arch/mips32/src/exception.c	(revision e07fe0c1834e24beaa907000673e1e37acbc7c7d)
+++ arch/mips32/src/exception.c	(revision fbe058f936b3f872b943c3aaef6878e7ee038c8e)
@@ -143,5 +143,4 @@
 	int cause;
 	int excno;
-	__u32 epc_shift = 0;
 
 	ASSERT(CPU != NULL);
Index: arch/mips32/src/interrupt.c
===================================================================
--- arch/mips32/src/interrupt.c	(revision e07fe0c1834e24beaa907000673e1e37acbc7c7d)
+++ arch/mips32/src/interrupt.c	(revision fbe058f936b3f872b943c3aaef6878e7ee038c8e)
@@ -94,6 +94,4 @@
 void interrupt_init(void)
 {
-	int i;
-
 	int_register(TIMER_IRQ, "timer", timer_exception);
 	int_register(0, "swint0", swint0);