Changeset fb7c52f in mainline
- Timestamp:
- 2009-11-27T19:56:29Z (15 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 103de761, 67392fa
- Parents:
- 8359969 (diff), ad7c340 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the(diff)
links above to see all the changes relative to each parent. - Location:
- kernel
- Files:
-
- 12 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/amd64/include/mm/page.h
r8359969 rfb7c52f 177 177 #define PFERR_CODE_ID (1 << 4) 178 178 179 /** Page Table Entry. */ 180 typedef struct { 181 unsigned present : 1; 182 unsigned writeable : 1; 183 unsigned uaccessible : 1; 184 unsigned page_write_through : 1; 185 unsigned page_cache_disable : 1; 186 unsigned accessed : 1; 187 unsigned dirty : 1; 188 unsigned unused: 1; 189 unsigned global : 1; 190 unsigned soft_valid : 1; /**< Valid content even if present bit is cleared. */ 191 unsigned avl : 2; 192 unsigned addr_12_31 : 30; 193 unsigned addr_32_51 : 21; 194 unsigned no_execute : 1; 195 } __attribute__ ((packed)) pte_t; 196 179 197 static inline unsigned int get_pt_flags(pte_t *pt, size_t i) 180 198 { -
kernel/arch/amd64/include/types.h
r8359969 rfb7c52f 82 82 #define PRIxn "llx" 83 83 84 /** Page Table Entry. */85 typedef struct {86 unsigned present : 1;87 unsigned writeable : 1;88 unsigned uaccessible : 1;89 unsigned page_write_through : 1;90 unsigned page_cache_disable : 1;91 unsigned accessed : 1;92 unsigned dirty : 1;93 unsigned unused: 1;94 unsigned global : 1;95 unsigned soft_valid : 1; /**< Valid content even if present bit is cleared. */96 unsigned avl : 2;97 unsigned addr_12_31 : 30;98 unsigned addr_32_51 : 21;99 unsigned no_execute : 1;100 } __attribute__ ((packed)) pte_t;101 102 84 #endif 103 85 -
kernel/arch/arm32/include/mm/page.h
r8359969 rfb7c52f 75 75 /* Get PTE address accessors for each level. */ 76 76 #define GET_PTL1_ADDRESS_ARCH(ptl0, i) \ 77 ((pte_t *) ((((pte_ level0_t *)(ptl0))[(i)]).coarse_table_addr << 10))77 ((pte_t *) ((((pte_t *)(ptl0))[(i)].l0).coarse_table_addr << 10)) 78 78 #define GET_PTL2_ADDRESS_ARCH(ptl1, i) \ 79 79 (ptl1) … … 81 81 (ptl2) 82 82 #define GET_FRAME_ADDRESS_ARCH(ptl3, i) \ 83 ((uintptr_t) ((((pte_ level1_t *)(ptl3))[(i)]).frame_base_addr << 12))83 ((uintptr_t) ((((pte_t *)(ptl3))[(i)].l1).frame_base_addr << 12)) 84 84 85 85 /* Set PTE address accessors for each level. */ 86 86 #define SET_PTL0_ADDRESS_ARCH(ptl0) \ 87 (set_ptl0_addr((pte_ level0_t *) (ptl0)))87 (set_ptl0_addr((pte_t *) (ptl0))) 88 88 #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \ 89 (((pte_ level0_t *) (ptl0))[(i)].coarse_table_addr = (a) >> 10)89 (((pte_t *) (ptl0))[(i)].l0.coarse_table_addr = (a) >> 10) 90 90 #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) 91 91 #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) 92 92 #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \ 93 (((pte_ level1_t *) (ptl3))[(i)].frame_base_addr = (a) >> 12)93 (((pte_t *) (ptl3))[(i)].l1.frame_base_addr = (a) >> 12) 94 94 95 95 /* Get PTE flags accessors for each level. */ 96 96 #define GET_PTL1_FLAGS_ARCH(ptl0, i) \ 97 get_pt_level0_flags((pte_ level0_t *) (ptl0), (size_t) (i))97 get_pt_level0_flags((pte_t *) (ptl0), (size_t) (i)) 98 98 #define GET_PTL2_FLAGS_ARCH(ptl1, i) \ 99 99 PAGE_PRESENT … … 101 101 PAGE_PRESENT 102 102 #define GET_FRAME_FLAGS_ARCH(ptl3, i) \ 103 get_pt_level1_flags((pte_ level1_t *) (ptl3), (size_t) (i))103 get_pt_level1_flags((pte_t *) (ptl3), (size_t) (i)) 104 104 105 105 /* Set PTE flags accessors for each level. */ 106 106 #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \ 107 set_pt_level0_flags((pte_ level0_t *) (ptl0), (size_t) (i), (x))107 set_pt_level0_flags((pte_t *) (ptl0), (size_t) (i), (x)) 108 108 #define SET_PTL2_FLAGS_ARCH(ptl1, i, x) 109 109 #define SET_PTL3_FLAGS_ARCH(ptl2, i, x) 110 110 #define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \ 111 set_pt_level1_flags((pte_ level1_t *) (ptl3), (size_t) (i), (x))111 set_pt_level1_flags((pte_t *) (ptl3), (size_t) (i), (x)) 112 112 113 113 /* Macros for querying the last-level PTE entries. */ … … 115 115 (*((uint32_t *) (pte)) != 0) 116 116 #define PTE_PRESENT_ARCH(pte) \ 117 (((pte_ level0_t *) (pte))->descriptor_type != 0)117 (((pte_t *) (pte))->l0.descriptor_type != 0) 118 118 #define PTE_GET_FRAME_ARCH(pte) \ 119 (((pte_ level1_t *) (pte))->frame_base_addr << FRAME_WIDTH)119 (((pte_t *) (pte))->l1.frame_base_addr << FRAME_WIDTH) 120 120 #define PTE_WRITABLE_ARCH(pte) \ 121 (((pte_level1_t *) (pte))->access_permission_0 == \ 122 PTE_AP_USER_RW_KERNEL_RW) 121 (((pte_t *) (pte))->l1.access_permission_0 == PTE_AP_USER_RW_KERNEL_RW) 123 122 #define PTE_EXECUTABLE_ARCH(pte) \ 124 123 1 … … 159 158 } ATTRIBUTE_PACKED pte_level1_t; 160 159 160 typedef union { 161 pte_level0_t l0; 162 pte_level1_t l1; 163 } pte_t; 161 164 162 165 /* Level 1 page tables access permissions */ … … 191 194 * @param pt Pointer to the page table to set. 192 195 */ 193 static inline void set_ptl0_addr(pte_ level0_t *pt)196 static inline void set_ptl0_addr(pte_t *pt) 194 197 { 195 198 asm volatile ( … … 205 208 * @param i Index of the entry to return. 206 209 */ 207 static inline int get_pt_level0_flags(pte_ level0_t *pt, size_t i)208 { 209 pte_level0_t *p = &pt[i] ;210 static inline int get_pt_level0_flags(pte_t *pt, size_t i) 211 { 212 pte_level0_t *p = &pt[i].l0; 210 213 int np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT); 211 214 … … 220 223 * @param i Index of the entry to return. 221 224 */ 222 static inline int get_pt_level1_flags(pte_ level1_t *pt, size_t i)223 { 224 pte_level1_t *p = &pt[i] ;225 static inline int get_pt_level1_flags(pte_t *pt, size_t i) 226 { 227 pte_level1_t *p = &pt[i].l1; 225 228 226 229 int dt = p->descriptor_type; … … 245 248 * @param flags new flags 246 249 */ 247 static inline void set_pt_level0_flags(pte_ level0_t *pt, size_t i, int flags)248 { 249 pte_level0_t *p = &pt[i] ;250 static inline void set_pt_level0_flags(pte_t *pt, size_t i, int flags) 251 { 252 pte_level0_t *p = &pt[i].l0; 250 253 251 254 if (flags & PAGE_NOT_PRESENT) { … … 273 276 * @param flags New flags. 274 277 */ 275 static inline void set_pt_level1_flags(pte_ level1_t *pt, size_t i, int flags)276 { 277 pte_level1_t *p = &pt[i] ;278 static inline void set_pt_level1_flags(pte_t *pt, size_t i, int flags) 279 { 280 pte_level1_t *p = &pt[i].l1; 278 281 279 282 if (flags & PAGE_NOT_PRESENT) { -
kernel/arch/arm32/include/types.h
r8359969 rfb7c52f 87 87 #define PRIxn "x" /**< Format for hexadecimal (u)native_t. */ 88 88 89 /** Page table entry.90 *91 * We have different structs for level 0 and level 1 page table entries.92 * See page.h for definition of pte_level*_t.93 */94 typedef struct {95 unsigned dummy : 32;96 } pte_t;97 98 89 #endif 99 90 -
kernel/arch/ia32/include/mm/page.h
r8359969 rfb7c52f 146 146 #define PFERR_CODE_RSVD (1 << 3) 147 147 148 /** Page Table Entry. */ 149 typedef struct { 150 unsigned present : 1; 151 unsigned writeable : 1; 152 unsigned uaccessible : 1; 153 unsigned page_write_through : 1; 154 unsigned page_cache_disable : 1; 155 unsigned accessed : 1; 156 unsigned dirty : 1; 157 unsigned pat : 1; 158 unsigned global : 1; 159 unsigned soft_valid : 1; /**< Valid content even if the present bit is not set. */ 160 unsigned avl : 2; 161 unsigned frame_address : 20; 162 } __attribute__ ((packed)) pte_t; 163 148 164 static inline unsigned int get_pt_flags(pte_t *pt, size_t i) 149 165 { -
kernel/arch/ia32/include/types.h
r8359969 rfb7c52f 80 80 #define PRIxn "x" /**< Format for hexadecimal (u)native_t. */ 81 81 82 /** Page Table Entry. */83 typedef struct {84 unsigned present : 1;85 unsigned writeable : 1;86 unsigned uaccessible : 1;87 unsigned page_write_through : 1;88 unsigned page_cache_disable : 1;89 unsigned accessed : 1;90 unsigned dirty : 1;91 unsigned pat : 1;92 unsigned global : 1;93 unsigned soft_valid : 1; /**< Valid content even if the present bit is not set. */94 unsigned avl : 2;95 unsigned frame_address : 20;96 } __attribute__ ((packed)) pte_t;97 98 82 #endif 99 83 -
kernel/arch/mips32/include/mm/page.h
r8359969 rfb7c52f 141 141 #include <arch/exception.h> 142 142 143 /** Page Table Entry. */ 144 typedef struct { 145 unsigned g : 1; /**< Global bit. */ 146 unsigned p : 1; /**< Present bit. */ 147 unsigned d : 1; /**< Dirty bit. */ 148 unsigned cacheable : 1; /**< Cacheable bit. */ 149 unsigned : 1; /**< Unused. */ 150 unsigned soft_valid : 1; /**< Valid content even if not present. */ 151 unsigned pfn : 24; /**< Physical frame number. */ 152 unsigned w : 1; /**< Page writable bit. */ 153 unsigned a : 1; /**< Accessed bit. */ 154 } pte_t; 155 156 143 157 static inline unsigned int get_pt_flags(pte_t *pt, size_t i) 144 158 { -
kernel/arch/mips32/include/types.h
r8359969 rfb7c52f 80 80 #define PRIxn "x" /**< Format for hexadecimal (u)native_t. */ 81 81 82 /** Page Table Entry. */83 typedef struct {84 unsigned g : 1; /**< Global bit. */85 unsigned p : 1; /**< Present bit. */86 unsigned d : 1; /**< Dirty bit. */87 unsigned cacheable : 1; /**< Cacheable bit. */88 unsigned : 1; /**< Unused. */89 unsigned soft_valid : 1; /**< Valid content even if not present. */90 unsigned pfn : 24; /**< Physical frame number. */91 unsigned w : 1; /**< Page writable bit. */92 unsigned a : 1; /**< Accessed bit. */93 } pte_t;94 95 82 #endif 96 83 -
kernel/arch/ppc32/include/mm/page.h
r8359969 rfb7c52f 131 131 #include <arch/interrupt.h> 132 132 133 /** Page Table Entry. */ 134 typedef struct { 135 unsigned present : 1; /**< Present bit. */ 136 unsigned page_write_through : 1; /**< Write thought caching. */ 137 unsigned page_cache_disable : 1; /**< No caching. */ 138 unsigned accessed : 1; /**< Accessed bit. */ 139 unsigned global : 1; /**< Global bit. */ 140 unsigned valid : 1; /**< Valid content even if not present. */ 141 unsigned pfn : 20; /**< Physical frame number. */ 142 } pte_t; 143 133 144 static inline unsigned int get_pt_flags(pte_t *pt, size_t i) 134 145 { -
kernel/arch/ppc32/include/types.h
r8359969 rfb7c52f 82 82 #define PRIxn "x" 83 83 84 /** Page Table Entry. */85 typedef struct {86 unsigned present : 1; /**< Present bit. */87 unsigned page_write_through : 1; /**< Write thought caching. */88 unsigned page_cache_disable : 1; /**< No caching. */89 unsigned accessed : 1; /**< Accessed bit. */90 unsigned global : 1; /**< Global bit. */91 unsigned valid : 1; /**< Valid content even if not present. */92 unsigned pfn : 20; /**< Physical frame number. */93 } pte_t;94 95 84 #endif 96 85 -
kernel/genarch/include/mm/as_pt.h
r8359969 rfb7c52f 36 36 #define KERN_AS_PT_H_ 37 37 38 #include <mm/mm.h> 39 #include <arch/types.h> 38 #include <arch/mm/page.h> 40 39 41 40 #define AS_PAGE_TABLE -
kernel/genarch/include/mm/page_pt.h
r8359969 rfb7c52f 44 44 #define KERN_PAGE_PT_H_ 45 45 46 #include <arch/types.h>47 46 #include <mm/as.h> 48 47 #include <mm/page.h> 48 #include <arch/mm/page.h> 49 #include <arch/types.h> 49 50 50 51 /*
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