Changeset f72c2f5 in mainline


Ignore:
Timestamp:
2011-03-29T20:29:26Z (14 years ago)
Author:
Martin Decky <martin@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
49852df
Parents:
d21e72db
Message:

remove unused variables

File:
1 edited

Legend:

Unmodified
Added
Removed
  • kernel/arch/ia64/src/mm/tlb.c

    rd21e72db rf72c2f5  
    475475void alternate_instruction_tlb_fault(uint64_t vector, istate_t *istate)
    476476{
    477         region_register_t rr;
    478         rid_t rid;
    479477        uintptr_t va;
    480478        pte_t *t;
    481479       
    482480        va = istate->cr_ifa; /* faulting address */
    483         rr.word = rr_read(VA2VRN(va));
    484         rid = rr.map.rid;
    485481       
    486482        page_table_lock(AS, true);
     
    649645void data_dirty_bit_fault(uint64_t vector, istate_t *istate)
    650646{
    651         region_register_t rr;
    652         rid_t rid;
    653647        uintptr_t va;
    654648        pte_t *t;
    655649       
    656650        va = istate->cr_ifa;  /* faulting address */
    657         rr.word = rr_read(VA2VRN(va));
    658         rid = rr.map.rid;
    659651       
    660652        page_table_lock(AS, true);
     
    686678void instruction_access_bit_fault(uint64_t vector, istate_t *istate)
    687679{
    688         region_register_t rr;
    689         rid_t rid;
    690680        uintptr_t va;
    691681        pte_t *t;
    692682       
    693683        va = istate->cr_ifa;  /* faulting address */
    694         rr.word = rr_read(VA2VRN(va));
    695         rid = rr.map.rid;
    696684       
    697685        page_table_lock(AS, true);
     
    723711void data_access_bit_fault(uint64_t vector, istate_t *istate)
    724712{
    725         region_register_t rr;
    726         rid_t rid;
    727713        uintptr_t va;
    728714        pte_t *t;
    729715       
    730716        va = istate->cr_ifa;  /* faulting address */
    731         rr.word = rr_read(VA2VRN(va));
    732         rid = rr.map.rid;
    733717       
    734718        page_table_lock(AS, true);
     
    760744void data_access_rights_fault(uint64_t vector, istate_t *istate)
    761745{
    762         region_register_t rr;
    763         rid_t rid;
    764746        uintptr_t va;
    765747        pte_t *t;
    766748       
    767749        va = istate->cr_ifa;  /* faulting address */
    768         rr.word = rr_read(VA2VRN(va));
    769         rid = rr.map.rid;
    770750       
    771751        /*
     
    792772void page_not_present(uint64_t vector, istate_t *istate)
    793773{
    794         region_register_t rr;
    795         rid_t rid;
    796774        uintptr_t va;
    797775        pte_t *t;
    798776       
    799777        va = istate->cr_ifa;  /* faulting address */
    800         rr.word = rr_read(VA2VRN(va));
    801         rid = rr.map.rid;
    802778       
    803779        page_table_lock(AS, true);
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