Changeset f6b5593 in mainline for kernel/arch/ia64/include/register.h
- Timestamp:
- 2009-09-21T11:53:03Z (15 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 4098e38
- Parents:
- 2f636b6 (diff), c1618ed (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the(diff)links above to see all the changes relative to each parent. - File:
-
- 1 edited
-
kernel/arch/ia64/include/register.h (modified) (4 diffs)
Legend:
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- Added
- Removed
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kernel/arch/ia64/include/register.h
r2f636b6 rf6b5593 27 27 */ 28 28 29 /** @addtogroup ia64 29 /** @addtogroup ia64 30 30 * @{ 31 31 */ … … 36 36 #define KERN_ia64_REGISTER_H_ 37 37 38 #define CR_IVR_MASK 0xf 39 #define PSR_IC_MASK 0x2000 40 #define PSR_I_MASK 0x4000 41 #define PSR_PK_MASK 0x8000 42 43 #define PSR_DT_MASK (1 << 17) 44 #define PSR_RT_MASK (1 << 27) 45 46 #define PSR_DFL_MASK (1 << 18) 47 #define PSR_DFH_MASK (1 << 19) 48 49 #define PSR_IT_MASK 0x0000001000000000 50 51 #define PSR_CPL_SHIFT 32 52 #define PSR_CPL_MASK_SHIFTED 3 53 54 #define PFM_MASK (~0x3fffffffff) 55 56 #define RSC_MODE_MASK 3 57 #define RSC_PL_MASK 12 38 #define DCR_PP_MASK (1 << 0) 39 #define DCR_BE_MASK (1 << 1) 40 #define DCR_LC_MASK (1 << 2) 41 #define DCR_DM_MASK (1 << 8) 42 #define DCR_DP_MASK (1 << 9) 43 #define DCR_DK_MASK (1 << 10) 44 #define DCR_DX_MASK (1 << 11) 45 #define DCR_DR_MASK (1 << 12) 46 #define DCR_DA_MASK (1 << 13) 47 #define DCR_DD_MASK (1 << 14) 48 49 #define CR_IVR_MASK 0x0f 50 51 #define PSR_IC_MASK (1 << 13) 52 #define PSR_I_MASK (1 << 14) 53 #define PSR_PK_MASK (1 << 15) 54 #define PSR_DT_MASK (1 << 17) 55 #define PSR_DFL_MASK (1 << 18) 56 #define PSR_DFH_MASK (1 << 19) 57 #define PSR_RT_MASK (1 << 27) 58 #define PSR_IT_MASK (1 << 36) 59 60 #define PSR_CPL_SHIFT 32 61 #define PSR_CPL_MASK_SHIFTED 3 62 63 #define PFM_MASK (~0x3fffffffff) 64 65 #define RSC_MODE_MASK 3 66 #define RSC_PL_MASK 12 58 67 59 68 /** Application registers. */ 60 #define AR_KR0 61 #define AR_KR1 62 #define AR_KR2 63 #define AR_KR3 64 #define AR_KR4 65 #define AR_KR5 66 #define AR_KR6 67 #define AR_KR7 68 /* AR 8-15reserved */69 #define AR_RSC 70 #define AR_BSP 71 #define AR_BSPSTORE 72 #define AR_RNAT 73 /* AR 20 reserved */74 #define AR_FCR 75 /* AR 22-23reserved */76 #define AR_EFLAG 77 #define AR_CSD 78 #define AR_SSD 79 #define AR_CFLG 80 #define AR_FSR 81 #define AR_FIR 82 #define AR_FDR 83 /* AR 31 reserved */84 #define AR_CCV 85 /* AR 33-35reserved */86 #define AR_UNAT 87 /* AR 37-39reserved */88 #define AR_FPSR 89 /* AR 41-43reserved */90 #define AR_ITC 91 /* AR 45-47reserved */92 /* AR 48-63ignored */93 #define AR_PFS 94 #define AR_LC 95 #define AR_EC 96 /* AR 67-111reserved */97 /* AR 112-127ignored */69 #define AR_KR0 0 70 #define AR_KR1 1 71 #define AR_KR2 2 72 #define AR_KR3 3 73 #define AR_KR4 4 74 #define AR_KR5 5 75 #define AR_KR6 6 76 #define AR_KR7 7 77 /* ARs 8-15 are reserved */ 78 #define AR_RSC 16 79 #define AR_BSP 17 80 #define AR_BSPSTORE 18 81 #define AR_RNAT 19 82 /* AR 20 is reserved */ 83 #define AR_FCR 21 84 /* ARs 22-23 are reserved */ 85 #define AR_EFLAG 24 86 #define AR_CSD 25 87 #define AR_SSD 26 88 #define AR_CFLG 27 89 #define AR_FSR 28 90 #define AR_FIR 29 91 #define AR_FDR 30 92 /* AR 31 is reserved */ 93 #define AR_CCV 32 94 /* ARs 33-35 are reserved */ 95 #define AR_UNAT 36 96 /* ARs 37-39 are reserved */ 97 #define AR_FPSR 40 98 /* ARs 41-43 are reserved */ 99 #define AR_ITC 44 100 /* ARs 45-47 are reserved */ 101 /* ARs 48-63 are ignored */ 102 #define AR_PFS 64 103 #define AR_LC 65 104 #define AR_EC 66 105 /* ARs 67-111 are reserved */ 106 /* ARs 112-127 are ignored */ 98 107 99 108 /** Control registers. */ 100 #define CR_DCR 101 #define CR_ITM 102 #define CR_IVA 103 /* CR3-CR7 reserved */104 #define CR_PTA 105 /* CR9-CR15 reserved */106 #define CR_IPSR 107 #define CR_ISR 108 /* CR18 reserved */109 #define CR_IIP 110 #define CR_IFA 111 #define CR_ITIR 112 #define CR_IIPA 113 #define CR_IFS 114 #define CR_IIM 115 #define CR_IHA 116 /* CR26-CR63 reserved */117 #define CR_LID 118 #define CR_IVR 119 #define CR_TPR 120 #define CR_EOI 121 #define CR_IRR0 122 #define CR_IRR1 123 #define CR_IRR2 124 #define CR_IRR3 125 #define CR_ITV 126 #define CR_PMV 127 #define CR_CMCV 128 /* CR75-CR79 reserved */129 #define CR_LRR0 130 #define CR_LRR1 131 /* CR82-CR127 reserved */109 #define CR_DCR 0 110 #define CR_ITM 1 111 #define CR_IVA 2 112 /* CR3-CR7 are reserved */ 113 #define CR_PTA 8 114 /* CR9-CR15 are reserved */ 115 #define CR_IPSR 16 116 #define CR_ISR 17 117 /* CR18 is reserved */ 118 #define CR_IIP 19 119 #define CR_IFA 20 120 #define CR_ITIR 21 121 #define CR_IIPA 22 122 #define CR_IFS 23 123 #define CR_IIM 24 124 #define CR_IHA 25 125 /* CR26-CR63 are reserved */ 126 #define CR_LID 64 127 #define CR_IVR 65 128 #define CR_TPR 66 129 #define CR_EOI 67 130 #define CR_IRR0 68 131 #define CR_IRR1 69 132 #define CR_IRR2 70 133 #define CR_IRR3 71 134 #define CR_ITV 72 135 #define CR_PMV 73 136 #define CR_CMCV 74 137 /* CR75-CR79 are reserved */ 138 #define CR_LRR0 80 139 #define CR_LRR1 81 140 /* CR82-CR127 are reserved */ 132 141 133 142 #ifndef __ASM__ … … 136 145 137 146 /** Processor Status Register. */ 138 union psr { 139 uint64_t value; 140 struct { 141 unsigned : 1; 142 unsigned be : 1; /**< Big-Endian data accesses. */ 143 unsigned up : 1; /**< User Performance monitor enable. */ 144 unsigned ac : 1; /**< Alignment Check. */ 145 unsigned mfl : 1; /**< Lower floating-point register written. */ 146 unsigned mfh : 1; /**< Upper floating-point register written. */ 147 unsigned : 7; 148 unsigned ic : 1; /**< Interruption Collection. */ 149 unsigned i : 1; /**< Interrupt Bit. */ 150 unsigned pk : 1; /**< Protection Key enable. */ 151 unsigned : 1; 152 unsigned dt : 1; /**< Data address Translation. */ 153 unsigned dfl : 1; /**< Disabled Floating-point Low register set. */ 154 unsigned dfh : 1; /**< Disabled Floating-point High register set. */ 155 unsigned sp : 1; /**< Secure Performance monitors. */ 156 unsigned pp : 1; /**< Privileged Performance monitor enable. */ 157 unsigned di : 1; /**< Disable Instruction set transition. */ 158 unsigned si : 1; /**< Secure Interval timer. */ 159 unsigned db : 1; /**< Debug Breakpoint fault. */ 160 unsigned lp : 1; /**< Lower Privilege transfer trap. */ 161 unsigned tb : 1; /**< Taken Branch trap. */ 162 unsigned rt : 1; /**< Register Stack Translation. */ 163 unsigned : 4; 164 unsigned cpl : 2; /**< Current Privilege Level. */ 165 unsigned is : 1; /**< Instruction Set. */ 166 unsigned mc : 1; /**< Machine Check abort mask. */ 167 unsigned it : 1; /**< Instruction address Translation. */ 168 unsigned id : 1; /**< Instruction Debug fault disable. */ 169 unsigned da : 1; /**< Disable Data Access and Dirty-bit faults. */ 170 unsigned dd : 1; /**< Data Debug fault disable. */ 171 unsigned ss : 1; /**< Single Step enable. */ 172 unsigned ri : 2; /**< Restart Instruction. */ 173 unsigned ed : 1; /**< Exception Deferral. */ 174 unsigned bn : 1; /**< Register Bank. */ 175 unsigned ia : 1; /**< Disable Instruction Access-bit faults. */ 176 } __attribute__ ((packed)); 177 }; 178 typedef union psr psr_t; 147 typedef union { 148 uint64_t value; 149 struct { 150 unsigned int : 1; 151 unsigned int be : 1; /**< Big-Endian data accesses. */ 152 unsigned int up : 1; /**< User Performance monitor enable. */ 153 unsigned int ac : 1; /**< Alignment Check. */ 154 unsigned int mfl : 1; /**< Lower floating-point register written. */ 155 unsigned int mfh : 1; /**< Upper floating-point register written. */ 156 unsigned int : 7; 157 unsigned int ic : 1; /**< Interruption Collection. */ 158 unsigned int i : 1; /**< Interrupt Bit. */ 159 unsigned int pk : 1; /**< Protection Key enable. */ 160 unsigned int : 1; 161 unsigned int dt : 1; /**< Data address Translation. */ 162 unsigned int dfl : 1; /**< Disabled Floating-point Low register set. */ 163 unsigned int dfh : 1; /**< Disabled Floating-point High register set. */ 164 unsigned int sp : 1; /**< Secure Performance monitors. */ 165 unsigned int pp : 1; /**< Privileged Performance monitor enable. */ 166 unsigned int di : 1; /**< Disable Instruction set transition. */ 167 unsigned int si : 1; /**< Secure Interval timer. */ 168 unsigned int db : 1; /**< Debug Breakpoint fault. */ 169 unsigned int lp : 1; /**< Lower Privilege transfer trap. */ 170 unsigned int tb : 1; /**< Taken Branch trap. */ 171 unsigned int rt : 1; /**< Register Stack Translation. */ 172 unsigned int : 4; 173 unsigned int cpl : 2; /**< Current Privilege Level. */ 174 unsigned int is : 1; /**< Instruction Set. */ 175 unsigned int mc : 1; /**< Machine Check abort mask. */ 176 unsigned int it : 1; /**< Instruction address Translation. */ 177 unsigned int id : 1; /**< Instruction Debug fault disable. */ 178 unsigned int da : 1; /**< Disable Data Access and Dirty-bit faults. */ 179 unsigned int dd : 1; /**< Data Debug fault disable. */ 180 unsigned int ss : 1; /**< Single Step enable. */ 181 unsigned int ri : 2; /**< Restart Instruction. */ 182 unsigned int ed : 1; /**< Exception Deferral. */ 183 unsigned int bn : 1; /**< Register Bank. */ 184 unsigned int ia : 1; /**< Disable Instruction Access-bit faults. */ 185 } __attribute__ ((packed)); 186 } psr_t; 179 187 180 188 /** Register Stack Configuration Register */ 181 union rsc { 182 uint64_t value; 183 struct { 184 unsigned mode : 2; 185 unsigned pl : 2; /**< Privilege Level. */ 186 unsigned be : 1; /**< Big-endian. */ 187 unsigned : 11; 188 unsigned loadrs : 14; 189 } __attribute__ ((packed)); 190 }; 191 typedef union rsc rsc_t; 189 typedef union { 190 uint64_t value; 191 struct { 192 unsigned int mode : 2; 193 unsigned int pl : 2; /**< Privilege Level. */ 194 unsigned int be : 1; /**< Big-endian. */ 195 unsigned int : 11; 196 unsigned int loadrs : 14; 197 } __attribute__ ((packed)); 198 } rsc_t; 192 199 193 200 /** External Interrupt Vector Register */ 194 union cr_ivr { 195 uint8_t vector; 196 uint64_t value; 197 }; 198 199 typedef union cr_ivr cr_ivr_t; 201 typedef union { 202 uint8_t vector; 203 uint64_t value; 204 } cr_ivr_t; 200 205 201 206 /** Task Priority Register */ 202 union cr_tpr { 203 struct { 204 unsigned : 4; 205 unsigned mic: 4; /**< Mask Interrupt Class. */ 206 unsigned : 8; 207 unsigned mmi: 1; /**< Mask Maskable Interrupts. */ 208 } __attribute__ ((packed)); 209 uint64_t value; 210 }; 211 212 typedef union cr_tpr cr_tpr_t; 207 typedef union { 208 uint64_t value; 209 struct { 210 unsigned int : 4; 211 unsigned int mic: 4; /**< Mask Interrupt Class. */ 212 unsigned int : 8; 213 unsigned int mmi: 1; /**< Mask Maskable Interrupts. */ 214 } __attribute__ ((packed)); 215 } cr_tpr_t; 213 216 214 217 /** Interval Timer Vector */ 215 union cr_itv { 216 struct { 217 unsigned vector : 8; 218 unsigned : 4; 219 unsigned : 1; 220 unsigned : 3; 221 unsigned m : 1; /**< Mask. */ 222 } __attribute__ ((packed)); 223 uint64_t value; 224 }; 225 226 typedef union cr_itv cr_itv_t; 218 typedef union { 219 uint64_t value; 220 struct { 221 unsigned int vector : 8; 222 unsigned int : 4; 223 unsigned int : 1; 224 unsigned int : 3; 225 unsigned int m : 1; /**< Mask. */ 226 } __attribute__ ((packed)); 227 } cr_itv_t; 227 228 228 229 /** Interruption Status Register */ 229 union cr_isr { 230 typedef union { 231 uint64_t value; 230 232 struct { 231 233 union { 232 234 /** General Exception code field structuring. */ 235 uint16_t code; 233 236 struct { 234 unsigned ge_na : 4;235 unsigned ge_code : 4;237 unsigned int ge_na : 4; 238 unsigned int ge_code : 4; 236 239 } __attribute__ ((packed)); 237 uint16_t code;238 240 }; 239 241 uint8_t vector; 240 unsigned : 8; 241 unsigned x : 1; /**< Execute exception. */ 242 unsigned w : 1; /**< Write exception. */ 243 unsigned r : 1; /**< Read exception. */ 244 unsigned na : 1; /**< Non-access exception. */ 245 unsigned sp : 1; /**< Speculative load exception. */ 246 unsigned rs : 1; /**< Register stack. */ 247 unsigned ir : 1; /**< Incomplete Register frame. */ 248 unsigned ni : 1; /**< Nested Interruption. */ 249 unsigned so : 1; /**< IA-32 Supervisor Override. */ 250 unsigned ei : 2; /**< Excepting Instruction. */ 251 unsigned ed : 1; /**< Exception Deferral. */ 252 unsigned : 20; 253 } __attribute__ ((packed)); 254 uint64_t value; 255 }; 256 257 typedef union cr_isr cr_isr_t; 242 unsigned int : 8; 243 unsigned int x : 1; /**< Execute exception. */ 244 unsigned int w : 1; /**< Write exception. */ 245 unsigned int r : 1; /**< Read exception. */ 246 unsigned int na : 1; /**< Non-access exception. */ 247 unsigned int sp : 1; /**< Speculative load exception. */ 248 unsigned int rs : 1; /**< Register stack. */ 249 unsigned int ir : 1; /**< Incomplete Register frame. */ 250 unsigned int ni : 1; /**< Nested Interruption. */ 251 unsigned int so : 1; /**< IA-32 Supervisor Override. */ 252 unsigned int ei : 2; /**< Excepting Instruction. */ 253 unsigned int ed : 1; /**< Exception Deferral. */ 254 unsigned int : 20; 255 } __attribute__ ((packed)); 256 } cr_isr_t; 258 257 259 258 /** CPUID Register 3 */ 260 union cpuid3 { 259 typedef union { 260 uint64_t value; 261 261 struct { 262 262 uint8_t number; … … 266 266 uint8_t archrev; 267 267 } __attribute__ ((packed)); 268 uint64_t value; 269 }; 270 271 typedef union cpuid3 cpuid3_t; 268 } cpuid3_t; 272 269 273 270 #endif /* !__ASM__ */
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