Changeset f6b5593 in mainline for kernel/arch/ia64/include/mm/page.h
- Timestamp:
- 2009-09-21T11:53:03Z (15 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 4098e38
- Parents:
- 2f636b6 (diff), c1618ed (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the(diff)
links above to see all the changes relative to each parent. - File:
-
- 1 edited
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kernel/arch/ia64/include/mm/page.h
r2f636b6 rf6b5593 28 28 */ 29 29 30 /** @addtogroup ia64mm 30 /** @addtogroup ia64mm 31 31 * @{ 32 32 */ … … 39 39 #include <arch/mm/frame.h> 40 40 41 #define PAGE_SIZE 42 #define PAGE_WIDTH 41 #define PAGE_SIZE FRAME_SIZE 42 #define PAGE_WIDTH FRAME_WIDTH 43 43 44 44 #ifdef KERNEL 45 45 46 46 /** Bit width of the TLB-locked portion of kernel address space. */ 47 #define KERNEL_PAGE_WIDTH 28/* 256M */48 #define IO_PAGE_WIDTH 26/* 64M */49 #define FW_PAGE_WIDTH 28/* 256M */50 51 #define USPACE_IO_PAGE_WIDTH 12/* 4K */47 #define KERNEL_PAGE_WIDTH 28 /* 256M */ 48 #define IO_PAGE_WIDTH 26 /* 64M */ 49 #define FW_PAGE_WIDTH 28 /* 256M */ 50 51 #define USPACE_IO_PAGE_WIDTH 12 /* 4K */ 52 52 53 53 … … 59 59 60 60 /* Firmware area (bellow 4GB in phys mem) */ 61 #define FW_OFFSET 61 #define FW_OFFSET 0x00000000F0000000 62 62 /* Legacy IO space */ 63 #define IO_OFFSET 63 #define IO_OFFSET 0x0001000000000000 64 64 /* Videoram - now mapped to 0 as VGA text mode vram on 0xb8000 */ 65 #define VIO_OFFSET 66 67 68 #define PPN_SHIFT 69 70 #define VRN_SHIFT 71 #define VRN_MASK (7LL << VRN_SHIFT)72 #define VA2VRN(va) ((va)>>VRN_SHIFT)65 #define VIO_OFFSET 0x0002000000000000 66 67 68 #define PPN_SHIFT 12 69 70 #define VRN_SHIFT 61 71 #define VRN_MASK (7ULL << VRN_SHIFT) 72 #define VA2VRN(va) ((va) >> VRN_SHIFT) 73 73 74 74 #ifdef __ASM__ 75 #define VRN_KERNEL775 #define VRN_KERNEL 7 76 76 #else 77 #define VRN_KERNEL 7LL77 #define VRN_KERNEL 7ULL 78 78 #endif 79 79 80 #define REGION_REGISTERS 81 82 #define KA2PA(x) ((uintptr_t) (x- (VRN_KERNEL << VRN_SHIFT)))83 #define PA2KA(x) ((uintptr_t) (x+ (VRN_KERNEL << VRN_SHIFT)))84 85 #define VHPT_WIDTH 20/* 1M */86 #define VHPT_SIZE 87 88 #define PTA_BASE_SHIFT 80 #define REGION_REGISTERS 8 81 82 #define KA2PA(x) ((uintptr_t) ((x) - (VRN_KERNEL << VRN_SHIFT))) 83 #define PA2KA(x) ((uintptr_t) ((x) + (VRN_KERNEL << VRN_SHIFT))) 84 85 #define VHPT_WIDTH 20 /* 1M */ 86 #define VHPT_SIZE (1 << VHPT_WIDTH) 87 88 #define PTA_BASE_SHIFT 15 89 89 90 90 /** Memory Attributes. */ 91 #define MA_WRITEBACK 0x092 #define MA_UNCACHEABLE 0x491 #define MA_WRITEBACK 0x00 92 #define MA_UNCACHEABLE 0x04 93 93 94 94 /** Privilege Levels. Only the most and the least privileged ones are ever used. */ 95 #define PL_KERNEL 0x096 #define PL_USER 0x395 #define PL_KERNEL 0x00 96 #define PL_USER 0x03 97 97 98 98 /* Access Rigths. Only certain combinations are used by the kernel. */ 99 #define AR_READ 0x0100 #define AR_EXECUTE 0x1101 #define AR_WRITE 0x299 #define AR_READ 0x00 100 #define AR_EXECUTE 0x01 101 #define AR_WRITE 0x02 102 102 103 103 #ifndef __ASM__ … … 113 113 struct vhpt_tag_info { 114 114 unsigned long long tag : 63; 115 unsigned ti : 1;115 unsigned int ti : 1; 116 116 } __attribute__ ((packed)); 117 117 … … 123 123 struct vhpt_entry_present { 124 124 /* Word 0 */ 125 unsigned p : 1;126 unsigned : 1;127 unsigned ma : 3;128 unsigned a : 1;129 unsigned d : 1;130 unsigned pl : 2;131 unsigned ar : 3;125 unsigned int p : 1; 126 unsigned int : 1; 127 unsigned int ma : 3; 128 unsigned int a : 1; 129 unsigned int d : 1; 130 unsigned int pl : 2; 131 unsigned int ar : 3; 132 132 unsigned long long ppn : 38; 133 unsigned : 2;134 unsigned ed : 1;135 unsigned i g1 : 11;133 unsigned int : 2; 134 unsigned int ed : 1; 135 unsigned int ig1 : 11; 136 136 137 137 /* Word 1 */ 138 unsigned : 2;139 unsigned ps : 6;140 unsigned key : 24;141 unsigned : 32;138 unsigned int : 2; 139 unsigned int ps : 6; 140 unsigned int key : 24; 141 unsigned int : 32; 142 142 143 143 /* Word 2 */ 144 144 union vhpt_tag tag; 145 145 146 /* Word 3 */ 146 /* Word 3 */ 147 147 uint64_t ig3 : 64; 148 148 } __attribute__ ((packed)); … … 150 150 struct vhpt_entry_not_present { 151 151 /* Word 0 */ 152 unsigned p : 1;152 unsigned int p : 1; 153 153 unsigned long long ig0 : 52; 154 unsigned i g1 : 11;154 unsigned int ig1 : 11; 155 155 156 156 /* Word 1 */ 157 unsigned : 2;158 unsigned ps : 6;157 unsigned int : 2; 158 unsigned int ps : 6; 159 159 unsigned long long ig2 : 56; 160 160 161 161 /* Word 2 */ 162 162 union vhpt_tag tag; 163 163 164 /* Word 3 */ 164 /* Word 3 */ 165 165 uint64_t ig3 : 64; 166 166 } __attribute__ ((packed)); 167 167 168 typedef union vhpt_entry{168 typedef union { 169 169 struct vhpt_entry_present present; 170 170 struct vhpt_entry_not_present not_present; … … 173 173 174 174 struct region_register_map { 175 unsigned ve : 1;176 unsigned : 1;177 unsigned ps : 6;178 unsigned rid : 24;179 unsigned : 32;180 } __attribute__ ((packed)); 181 182 typedef union region_register{175 unsigned int ve : 1; 176 unsigned int : 1; 177 unsigned int ps : 6; 178 unsigned int rid : 24; 179 unsigned int : 32; 180 } __attribute__ ((packed)); 181 182 typedef union { 183 183 struct region_register_map map; 184 184 unsigned long long word; 185 } region_register ;185 } region_register_t; 186 186 187 187 struct pta_register_map { 188 unsigned ve : 1;189 unsigned : 1;190 unsigned size : 6;191 unsigned vf : 1;192 unsigned : 6;188 unsigned int ve : 1; 189 unsigned int : 1; 190 unsigned int size : 6; 191 unsigned int vf : 1; 192 unsigned int : 6; 193 193 unsigned long long base : 49; 194 194 } __attribute__ ((packed)); … … 197 197 struct pta_register_map map; 198 198 uint64_t word; 199 } pta_register ;199 } pta_register_t; 200 200 201 201 /** Return Translation Hashed Entry Address. … … 211 211 { 212 212 uint64_t ret; 213 214 asm volatile ("thash %0 = %1\n" : "=r" (ret) : "r" (va)); 215 213 214 asm volatile ( 215 "thash %[ret] = %[va]\n" 216 : [ret] "=r" (ret) 217 : [va] "r" (va) 218 ); 219 216 220 return ret; 217 221 } … … 229 233 { 230 234 uint64_t ret; 231 232 asm volatile ("ttag %0 = %1\n" : "=r" (ret) : "r" (va)); 233 235 236 asm volatile ( 237 "ttag %[ret] = %[va]\n" 238 : [ret] "=r" (ret) 239 : [va] "r" (va) 240 ); 241 234 242 return ret; 235 243 } … … 244 252 { 245 253 uint64_t ret; 254 246 255 ASSERT(i < REGION_REGISTERS); 247 asm volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i << VRN_SHIFT)); 256 257 asm volatile ( 258 "mov %[ret] = rr[%[index]]\n" 259 : [ret] "=r" (ret) 260 : [index] "r" (i << VRN_SHIFT) 261 ); 262 248 263 return ret; 249 264 } … … 257 272 { 258 273 ASSERT(i < REGION_REGISTERS); 259 asm volatile ( 260 "mov rr[%0] = %1\n" 261 : 262 : "r" (i << VRN_SHIFT), "r" (v) 263 ); 264 } 265 274 275 asm volatile ( 276 "mov rr[%[index]] = %[value]\n" 277 :: [index] "r" (i << VRN_SHIFT), 278 [value] "r" (v) 279 ); 280 } 281 266 282 /** Read Page Table Register. 267 283 * … … 272 288 uint64_t ret; 273 289 274 asm volatile ("mov %0 = cr.pta\n" : "=r" (ret)); 290 asm volatile ( 291 "mov %[ret] = cr.pta\n" 292 : [ret] "=r" (ret) 293 ); 275 294 276 295 return ret; … … 283 302 static inline void pta_write(uint64_t v) 284 303 { 285 asm volatile ("mov cr.pta = %0\n" : : "r" (v)); 304 asm volatile ( 305 "mov cr.pta = %[value]\n" 306 :: [value] "r" (v) 307 ); 286 308 } 287 309
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