Changeset f6b5593 in mainline for kernel/arch/ia64/include/asm.h
- Timestamp:
- 2009-09-21T11:53:03Z (15 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 4098e38
- Parents:
- 2f636b6 (diff), c1618ed (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
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- 1 edited
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kernel/arch/ia64/include/asm.h
r2f636b6 rf6b5593 27 27 */ 28 28 29 /** @addtogroup ia64 29 /** @addtogroup ia64 30 30 * @{ 31 31 */ … … 41 41 #include <arch/register.h> 42 42 43 #define IA64_IOSPACE_ADDRESS 0xE001000000000000ULL43 #define IA64_IOSPACE_ADDRESS 0xE001000000000000ULL 44 44 45 45 static inline void pio_write_8(ioport8_t *port, uint8_t v) 46 46 { 47 47 uintptr_t prt = (uintptr_t) port; 48 49 *((ioport8_t *) (IA64_IOSPACE_ADDRESS +48 49 *((ioport8_t *) (IA64_IOSPACE_ADDRESS + 50 50 ((prt & 0xfff) | ((prt >> 2) << 12)))) = v; 51 52 asm volatile ("mf\n" ::: "memory"); 51 52 asm volatile ( 53 "mf\n" 54 ::: "memory" 55 ); 53 56 } 54 57 … … 56 59 { 57 60 uintptr_t prt = (uintptr_t) port; 58 59 *((ioport16_t *) (IA64_IOSPACE_ADDRESS +61 62 *((ioport16_t *) (IA64_IOSPACE_ADDRESS + 60 63 ((prt & 0xfff) | ((prt >> 2) << 12)))) = v; 61 62 asm volatile ("mf\n" ::: "memory"); 64 65 asm volatile ( 66 "mf\n" 67 ::: "memory" 68 ); 63 69 } 64 70 … … 66 72 { 67 73 uintptr_t prt = (uintptr_t) port; 68 69 *((ioport32_t *) (IA64_IOSPACE_ADDRESS +74 75 *((ioport32_t *) (IA64_IOSPACE_ADDRESS + 70 76 ((prt & 0xfff) | ((prt >> 2) << 12)))) = v; 71 72 asm volatile ("mf\n" ::: "memory"); 77 78 asm volatile ( 79 "mf\n" 80 ::: "memory" 81 ); 73 82 } 74 83 … … 76 85 { 77 86 uintptr_t prt = (uintptr_t) port; 78 79 asm volatile ("mf\n" ::: "memory"); 80 81 return *((ioport8_t *)(IA64_IOSPACE_ADDRESS + 87 88 asm volatile ( 89 "mf\n" 90 ::: "memory" 91 ); 92 93 return *((ioport8_t *) (IA64_IOSPACE_ADDRESS + 82 94 ((prt & 0xfff) | ((prt >> 2) << 12)))); 83 95 } … … 86 98 { 87 99 uintptr_t prt = (uintptr_t) port; 88 89 asm volatile ("mf\n" ::: "memory"); 90 91 return *((ioport16_t *)(IA64_IOSPACE_ADDRESS + 100 101 asm volatile ( 102 "mf\n" 103 ::: "memory" 104 ); 105 106 return *((ioport16_t *) (IA64_IOSPACE_ADDRESS + 92 107 ((prt & 0xfff) | ((prt >> 2) << 12)))); 93 108 } … … 96 111 { 97 112 uintptr_t prt = (uintptr_t) port; 98 99 asm volatile ("mf\n" ::: "memory"); 100 101 return *((ioport32_t *)(IA64_IOSPACE_ADDRESS + 113 114 asm volatile ( 115 "mf\n" 116 ::: "memory" 117 ); 118 119 return *((ioport32_t *) (IA64_IOSPACE_ADDRESS + 102 120 ((prt & 0xfff) | ((prt >> 2) << 12)))); 103 121 } … … 112 130 { 113 131 uint64_t v; 114 115 //I'm not sure why but this code bad inlines in scheduler, 116 //so THE shifts about 16B and causes kernel panic 117 //asm volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1))); 118 //return v; 119 120 //this code have the same meaning but inlines well 121 asm volatile ("mov %0 = r12" : "=r" (v) ); 122 return v & (~(STACK_SIZE-1)); 132 133 /* I'm not sure why but this code bad inlines in scheduler, 134 so THE shifts about 16B and causes kernel panic 135 136 asm volatile ( 137 "and %[value] = %[mask], r12" 138 : [value] "=r" (v) 139 : [mask] "r" (~(STACK_SIZE - 1)) 140 ); 141 return v; 142 143 This code have the same meaning but inlines well. 144 */ 145 146 asm volatile ( 147 "mov %[value] = r12" 148 : [value] "=r" (v) 149 ); 150 151 return (v & (~(STACK_SIZE - 1))); 123 152 } 124 153 … … 131 160 uint64_t v; 132 161 133 asm volatile ("mov %0 = psr\n" : "=r" (v)); 162 asm volatile ( 163 "mov %[value] = psr\n" 164 : [value] "=r" (v) 165 ); 134 166 135 167 return v; … … 144 176 uint64_t v; 145 177 146 asm volatile ("mov %0 = cr.iva\n" : "=r" (v)); 178 asm volatile ( 179 "mov %[value] = cr.iva\n" 180 : [value] "=r" (v) 181 ); 147 182 148 183 return v; … … 155 190 static inline void iva_write(uint64_t v) 156 191 { 157 asm volatile ("mov cr.iva = %0\n" : : "r" (v)); 192 asm volatile ( 193 "mov cr.iva = %[value]\n" 194 :: [value] "r" (v) 195 ); 158 196 } 159 197 … … 167 205 uint64_t v; 168 206 169 asm volatile ("mov %0 = cr.ivr\n" : "=r" (v)); 207 asm volatile ( 208 "mov %[value] = cr.ivr\n" 209 : [value] "=r" (v) 210 ); 170 211 171 212 return v; … … 176 217 uint64_t v; 177 218 178 asm volatile ("mov %0 = cr64\n" : "=r" (v)); 219 asm volatile ( 220 "mov %[value] = cr64\n" 221 : [value] "=r" (v) 222 ); 179 223 180 224 return v; … … 188 232 static inline void itc_write(uint64_t v) 189 233 { 190 asm volatile ("mov ar.itc = %0\n" : : "r" (v)); 234 asm volatile ( 235 "mov ar.itc = %[value]\n" 236 :: [value] "r" (v) 237 ); 191 238 } 192 239 … … 199 246 uint64_t v; 200 247 201 asm volatile ("mov %0 = ar.itc\n" : "=r" (v)); 248 asm volatile ( 249 "mov %[value] = ar.itc\n" 250 : [value] "=r" (v) 251 ); 202 252 203 253 return v; … … 210 260 static inline void itm_write(uint64_t v) 211 261 { 212 asm volatile ("mov cr.itm = %0\n" : : "r" (v)); 262 asm volatile ( 263 "mov cr.itm = %[value]\n" 264 :: [value] "r" (v) 265 ); 213 266 } 214 267 … … 221 274 uint64_t v; 222 275 223 asm volatile ("mov %0 = cr.itm\n" : "=r" (v)); 276 asm volatile ( 277 "mov %[value] = cr.itm\n" 278 : [value] "=r" (v) 279 ); 224 280 225 281 return v; … … 234 290 uint64_t v; 235 291 236 asm volatile ("mov %0 = cr.itv\n" : "=r" (v)); 292 asm volatile ( 293 "mov %[value] = cr.itv\n" 294 : [value] "=r" (v) 295 ); 237 296 238 297 return v; … … 245 304 static inline void itv_write(uint64_t v) 246 305 { 247 asm volatile ("mov cr.itv = %0\n" : : "r" (v)); 306 asm volatile ( 307 "mov cr.itv = %[value]\n" 308 :: [value] "r" (v) 309 ); 248 310 } 249 311 … … 254 316 static inline void eoi_write(uint64_t v) 255 317 { 256 asm volatile ("mov cr.eoi = %0\n" : : "r" (v)); 318 asm volatile ( 319 "mov cr.eoi = %[value]\n" 320 :: [value] "r" (v) 321 ); 257 322 } 258 323 … … 264 329 { 265 330 uint64_t v; 266 267 asm volatile ("mov %0 = cr.tpr\n" : "=r" (v)); 331 332 asm volatile ( 333 "mov %[value] = cr.tpr\n" 334 : [value] "=r" (v) 335 ); 268 336 269 337 return v; … … 276 344 static inline void tpr_write(uint64_t v) 277 345 { 278 asm volatile ("mov cr.tpr = %0\n" : : "r" (v)); 346 asm volatile ( 347 "mov cr.tpr = %[value]\n" 348 :: [value] "r" (v) 349 ); 279 350 } 280 351 … … 291 362 292 363 asm volatile ( 293 "mov % 0= psr\n"294 "rsm % 1\n"295 : "=r" (v)296 : "i" (PSR_I_MASK)364 "mov %[value] = psr\n" 365 "rsm %[mask]\n" 366 : [value] "=r" (v) 367 : [mask] "i" (PSR_I_MASK) 297 368 ); 298 369 … … 312 383 313 384 asm volatile ( 314 "mov % 0= psr\n"315 "ssm % 1\n"385 "mov %[value] = psr\n" 386 "ssm %[mask]\n" 316 387 ";;\n" 317 388 "srlz.d\n" 318 : "=r" (v)319 : "i" (PSR_I_MASK)389 : [value] "=r" (v) 390 : [mask] "i" (PSR_I_MASK) 320 391 ); 321 392 … … 349 420 static inline void pk_disable(void) 350 421 { 351 asm volatile ("rsm %0\n" : : "i" (PSR_PK_MASK)); 422 asm volatile ( 423 "rsm %[mask]\n" 424 ";;\n" 425 "srlz.d\n" 426 :: [mask] "i" (PSR_PK_MASK) 427 ); 352 428 } 353 429
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