Index: boot/arch/amd64/Makefile.inc =================================================================== --- boot/arch/amd64/Makefile.inc (revision ef9a2a897b47371cfb43b8b8bb95ad044136eccf) +++ boot/arch/amd64/Makefile.inc (revision f64fe6e66d56e463f7d0a175dfd25a55757a880f) @@ -28,16 +28,22 @@ RD_SRVS_ESSENTIAL += \ + $(USPACE_PATH)/srv/audio/hound/hound \ + $(USPACE_PATH)/srv/devman/devman \ $(USPACE_PATH)/srv/hw/irc/apic/apic \ $(USPACE_PATH)/srv/hw/irc/i8259/i8259 -RD_DRVS += \ + +RD_DRVS_ESSENTIAL += \ infrastructure/rootpc \ block/ata_bd \ bus/pci/pciintel \ bus/isa \ + audio/sb16 \ char/i8042 \ + char/ps2mouse \ + char/xtkbd + +RD_DRVS_NON_ESSENTIAL += \ char/ns8250 \ - char/ps2mouse \ - char/xtkbd \ time/cmos-rtc \ bus/usb/ehci\ @@ -55,4 +61,9 @@ bus/isa +RD_APPS_ESSENTIAL += \ + $(USPACE_PATH)/app/edit/edit \ + $(USPACE_PATH)/app/mixerctl/mixerctl \ + $(USPACE_PATH)/app/wavplay/wavplay \ + BOOT_OUTPUT = $(ROOT_PATH)/image.iso PREBUILD = $(INITRD).img Index: boot/arch/arm32/Makefile.inc =================================================================== --- boot/arch/arm32/Makefile.inc (revision ef9a2a897b47371cfb43b8b8bb95ad044136eccf) +++ boot/arch/arm32/Makefile.inc (revision f64fe6e66d56e463f7d0a175dfd25a55757a880f) @@ -57,5 +57,5 @@ endif -RD_DRVS += \ +RD_DRVS_ESSENTIAL += \ infrastructure/rootamdm37x \ fb/amdm37x_dispc \ Index: boot/arch/arm32/include/cp15.h =================================================================== --- boot/arch/arm32/include/cp15.h (revision f64fe6e66d56e463f7d0a175dfd25a55757a880f) +++ boot/arch/arm32/include/cp15.h (revision f64fe6e66d56e463f7d0a175dfd25a55757a880f) @@ -0,0 +1,1 @@ +../../../../kernel/arch/arm32/include/arch/cp15.h Index: boot/arch/arm32/src/asm.S =================================================================== --- boot/arch/arm32/src/asm.S (revision ef9a2a897b47371cfb43b8b8bb95ad044136eccf) +++ boot/arch/arm32/src/asm.S (revision f64fe6e66d56e463f7d0a175dfd25a55757a880f) @@ -56,5 +56,4 @@ jump_to_kernel: # - # TODO # Make sure that the I-cache, D-cache and memory are mutually coherent # before passing control to the copied code. @@ -68,10 +67,19 @@ #define CP15_C1_BP 11 #define CP15_C1_DC 2 - # Disable I-cache and D-cache before the kernel is started. + + +#ifndef PROCESSOR_ARCH_armv7_a mrc p15, 0, r4, c1, c0, 0 + + # D-cache before the kernel is started. bic r4, r4, #(1 << CP15_C1_DC) + + # Disable I-cache and Branche predictors. bic r4, r4, #(1 << CP15_C1_IC) bic r4, r4, #(1 << CP15_C1_BP) + mcr p15, 0, r4, c1, c0, 0 +#endif + @@ -81,8 +89,10 @@ #else #cp15 dsb, r4 is ignored (should be zero) + mov r4, #0 mcr p15, 0, r4, c7, c10, 4 #endif # Clean ICache and BPredictors, r4 ignored (SBZ) + mov r4, #0 mcr p15, 0, r4, c7, c5, 0 nop Index: boot/arch/arm32/src/main.c =================================================================== --- boot/arch/arm32/src/main.c (revision ef9a2a897b47371cfb43b8b8bb95ad044136eccf) +++ boot/arch/arm32/src/main.c (revision f64fe6e66d56e463f7d0a175dfd25a55757a880f) @@ -53,25 +53,9 @@ extern void *bdata_end; - -static inline void invalidate_icache(void) -{ - /* ICIALLU Invalidate entire ICache */ - asm volatile ("mov r0, #0\n" "mcr p15, 0, r0, c7, c5, 0\n" ::: "r0" ); -} - -static inline void invalidate_dcache(void *address, size_t size) -{ - const uintptr_t addr = (uintptr_t)address; - /* DCIMVAC - invalidate by address to the point of coherence */ - for (uintptr_t a = addr; a < addr + size; a += 4) { - asm volatile ("mcr p15, 0, %[a], c7, c6, 1\n" :: [a]"r"(a) : ); - } -} - static inline void clean_dcache_poc(void *address, size_t size) { const uintptr_t addr = (uintptr_t)address; - /* DCCMVAC - clean by address to the point of coherence */ for (uintptr_t a = addr; a < addr + size; a += 4) { + /* DCCMVAC - clean by address to the point of coherence */ asm volatile ("mcr p15, 0, %[a], c7, c10, 1\n" :: [a]"r"(a) : ); } @@ -82,11 +66,4 @@ void bootstrap(void) { - /* Make sure we run in memory code when caches are enabled, - * make sure we read memory data too. This part is ARMv7 specific as - * ARMv7 no longer invalidates caches on restart. - * See chapter B2.2.2 of ARM Architecture Reference Manual p. B2-1263*/ - invalidate_icache(); - invalidate_dcache(&bdata_start, &bdata_end - &bdata_start); - /* Enable MMU and caches */ mmu_start(); @@ -105,5 +82,4 @@ components[i].start, components[i].name, components[i].inflated, components[i].size); - invalidate_dcache(components[i].start, components[i].size); } @@ -148,4 +124,5 @@ halt(); } + /* Make sure data are in the memory, ICache will need them */ clean_dcache_poc(dest[i - 1], components[i - 1].inflated); } Index: boot/arch/arm32/src/mm.c =================================================================== --- boot/arch/arm32/src/mm.c (revision ef9a2a897b47371cfb43b8b8bb95ad044136eccf) +++ boot/arch/arm32/src/mm.c (revision f64fe6e66d56e463f7d0a175dfd25a55757a880f) @@ -37,4 +37,50 @@ #include #include +#include + +#ifdef PROCESSOR_ARCH_armv7_a +static unsigned log2(unsigned val) +{ + unsigned log = 0; + while (val >> log++); + return log - 2; +} + +static void dcache_invalidate_level(unsigned level) +{ + CSSELR_write(level << 1); + const uint32_t ccsidr = CCSIDR_read(); + const unsigned sets = CCSIDR_SETS(ccsidr); + const unsigned ways = CCSIDR_WAYS(ccsidr); + const unsigned line_log = CCSIDR_LINESIZE_LOG(ccsidr); + const unsigned set_shift = line_log; + const unsigned way_shift = 32 - log2(ways); + + for (unsigned k = 0; k < ways; ++k) + for (unsigned j = 0; j < sets; ++j) { + const uint32_t val = (level << 1) | + (j << set_shift) | (k << way_shift); + DCISW_write(val); + } +} + +/** invalidate all dcaches -- armv7 */ +static void cache_invalidate(void) +{ + const uint32_t cinfo = CLIDR_read(); + for (unsigned i = 0; i < 7; ++i) { + switch (CLIDR_CACHE(i, cinfo)) + { + case CLIDR_DCACHE_ONLY: + case CLIDR_SEP_CACHE: + case CLIDR_UNI_CACHE: + dcache_invalidate_level(i); + } + } + asm volatile ( "dsb\n" ); + ICIALLU_write(0); + asm volatile ( "isb\n" ); +} +#endif /** Disable the MMU */ @@ -60,21 +106,16 @@ static inline int section_cacheable(pfn_t section) { + const unsigned long address = section << PTE_SECTION_SHIFT; #ifdef MACHINE_gta02 - unsigned long address = section << PTE_SECTION_SHIFT; - - if (address >= GTA02_IOMEM_START && address < GTA02_IOMEM_END) - return 0; - else + if (address < GTA02_IOMEM_START || address >= GTA02_IOMEM_END) return 1; #elif defined MACHINE_beagleboardxm - const unsigned long address = section << PTE_SECTION_SHIFT; if (address >= BBXM_RAM_START && address < BBXM_RAM_END) return 1; #elif defined MACHINE_beaglebone - const unsigned long address = section << PTE_SECTION_SHIFT; if (address >= AM335x_RAM_START && address < AM335x_RAM_END) return 1; #endif - return 0; + return address * 0; } @@ -95,11 +136,23 @@ { pte->descriptor_type = PTE_DESCRIPTOR_SECTION; - pte->bufferable = 1; - pte->cacheable = section_cacheable(frame); pte->xn = 0; pte->domain = 0; pte->should_be_zero_1 = 0; pte->access_permission_0 = PTE_AP_USER_NO_KERNEL_RW; +#ifdef PROCESSOR_ARCH_armv7_a + /* + * Keeps this setting in sync with memory type attributes in: + * init_boot_pt (boot/arch/arm32/src/mm.c) + * set_pt_level1_flags (kernel/arch/arm32/include/arch/mm/page_armv6.h) + * set_ptl0_addr (kernel/arch/arm32/include/arch/mm/page.h) + */ + pte->tex = section_cacheable(frame) ? 5 : 0; + pte->cacheable = section_cacheable(frame) ? 0 : 0; + pte->bufferable = section_cacheable(frame) ? 1 : 0; +#else + pte->bufferable = 1; + pte->cacheable = section_cacheable(frame); pte->tex = 0; +#endif pte->access_permission_1 = 0; pte->shareable = 0; @@ -113,14 +166,26 @@ static void init_boot_pt(void) { - const pfn_t split_page = PTL0_ENTRIES; - /* Create 1:1 virtual-physical mapping (in lower 2 GB). */ - pfn_t page; - for (page = 0; page < split_page; page++) + /* + * Create 1:1 virtual-physical mapping. + * Physical memory on BBxM a BBone starts at 2GB + * boundary, icp has a memory mirror at 2GB. + * (ARM Integrator Core Module User guide ch. 6.3, p. 6-7) + * gta02 somehow works (probably due to limited address size), + * s3c2442b manual ch. 5, p.5-1: + * "Address space: 128Mbytes per bank (total 1GB/8 banks)" + */ + for (pfn_t page = 0; page < PTL0_ENTRIES; ++page) init_ptl0_section(&boot_pt[page], page); - - asm volatile ( - "mcr p15, 0, %[pt], c2, c0, 0\n" - :: [pt] "r" (boot_pt) - ); + + /* + * Tell MMU page might be cached. Keeps this setting in sync + * with memory type attributes in: + * init_ptl0_section (boot/arch/arm32/src/mm.c) + * set_pt_level1_flags (kernel/arch/arm32/include/arch/mm/page_armv6.h) + * set_ptl0_addr (kernel/arch/arm32/include/arch/mm/page.h) + */ + uint32_t val = (uint32_t)boot_pt & TTBR_ADDR_MASK; + val |= TTBR_RGN_WBWA_CACHE | TTBR_C_FLAG; + TTBR0_write(val); } @@ -141,6 +206,12 @@ * we disable caches before jumping to kernel * so this is safe for all archs. + * Enable VMSAv6 the bit (23) is only writable on ARMv6. + * (and QEMU) */ +#ifdef PROCESSOR_ARCH_armv6 + "ldr r1, =0x00801805\n" +#else "ldr r1, =0x00001805\n" +#endif "orr r0, r0, r1\n" @@ -160,4 +231,11 @@ void mmu_start() { disable_paging(); +#ifdef PROCESSOR_ARCH_armv7_a + /* Make sure we run in memory code when caches are enabled, + * make sure we read memory data too. This part is ARMv7 specific as + * ARMv7 no longer invalidates caches on restart. + * See chapter B2.2.2 of ARM Architecture Reference Manual p. B2-1263*/ + cache_invalidate(); +#endif init_boot_pt(); enable_paging(); Index: boot/arch/ppc32/Makefile.inc =================================================================== --- boot/arch/ppc32/Makefile.inc (revision ef9a2a897b47371cfb43b8b8bb95ad044136eccf) +++ boot/arch/ppc32/Makefile.inc (revision f64fe6e66d56e463f7d0a175dfd25a55757a880f) @@ -42,5 +42,5 @@ $(USPACE_PATH)/srv/hw/bus/cuda_adb/cuda_adb -RD_DRVS += \ +RD_DRVS_ESSENTIAL += \ infrastructure/rootmac \ bus/pci/pciintel \ Index: boot/arch/sparc64/src/asm.S =================================================================== --- boot/arch/sparc64/src/asm.S (revision ef9a2a897b47371cfb43b8b8bb95ad044136eccf) +++ boot/arch/sparc64/src/asm.S (revision f64fe6e66d56e463f7d0a175dfd25a55757a880f) @@ -30,8 +30,10 @@ #include +#if defined(PROCESSOR_us) || defined(PROCESSOR_us3) #define ICACHE_SIZE 8192 #define ICACHE_LINE_SIZE 32 #define ICACHE_SET_BIT (1 << 13) #define ASI_ICACHE_TAG 0x67 +#endif /* PROCESSOR_us || PROCESSOR_us3 */ .register %g2, #scratch @@ -134,4 +136,5 @@ # Flush I-cache icache_flush: +#if defined(PROCESSOR_us) || defined(PROCESSOR_us3) set ((ICACHE_SIZE - ICACHE_LINE_SIZE) | ICACHE_SET_BIT), %g1 stxa %g0, [%g1] ASI_ICACHE_TAG @@ -149,4 +152,9 @@ nop +#else + // TODO: sun4v + retl + nop +#endif /* PROCESSOR_us || PROCESSOR_us3 */ .global ofw