Changes in kernel/arch/mips32/src/interrupt.c [f4bb404:f5dd4a1] in mainline

File:

• kernel/arch/mips32/src/interrupt.c (modified) (5 diffs)

kernel/arch/mips32/src/interrupt.c

@@ -41 +41 @@
 #include <ipc/sysipc.h>
 
+#define IRQ_COUNT   8
+#define TIMER_IRQ   7
+
+function virtual_timer_fnc = NULL;
+static irq_t timer_irq;
+
 // TODO: This is SMP unsafe!!!
 
@@ -46 +52 @@
 static unsigned long nextcount;
 static unsigned long lastcount;
-
-/** Table of interrupt handlers. */
-int_handler_t int_handler[MIPS_INTERRUPTS] = { };
 
 /** Disable interrupts.
@@ -110 +113 @@
 }
 
-static void timer_interrupt_handler(unsigned int intr)
+static irq_ownership_t timer_claim(irq_t *irq)
+{
+        return IRQ_ACCEPT;
+}
+
+static void timer_irq_handler(irq_t *irq)
 {
         if (cp0_count_read() < lastcount)
@@ -127 +135 @@
         cp0_compare_write(nextcount);
 
+        /*
+         * We are holding a lock which prevents preemption.
+         * Release the lock, call clock() and reacquire the lock again.
+         */
+        irq_spinlock_unlock(&irq->lock, false);
         clock();
+        irq_spinlock_lock(&irq->lock, false);
+
+        if (virtual_timer_fnc != NULL)
+                virtual_timer_fnc();
 }
 
@@ -133 +150 @@
 void interrupt_init(void)
 {
-        int_handler[INT_TIMER] = timer_interrupt_handler;
+        irq_init(IRQ_COUNT, IRQ_COUNT);
+
+        irq_initialize(&timer_irq);
+        timer_irq.inr = TIMER_IRQ;
+        timer_irq.claim = timer_claim;
+        timer_irq.handler = timer_irq_handler;
+        irq_register(&timer_irq);
 
         timer_start();
-        cp0_unmask_int(INT_TIMER);
+        cp0_unmask_int(TIMER_IRQ);
 }