Index: arch/mips/src/exception.c
===================================================================
--- arch/mips/src/exception.c	(revision ffc277e3c054a3016b2cfa2ea3b7a295fd2a54c3)
+++ arch/mips/src/exception.c	(revision f3a6c8e593cee3b567dd3356e55e5936fc44ee80)
@@ -52,6 +52,10 @@
 	cp0_status_write(cp0_status_read() & ~ (cp0_status_exl_exception_bit |
 						cp0_status_um_bit));
+
 	/* Save pstate so that the threads can access it */
-	if (THREAD)
+	/* If THREAD->pstate is set, this is nested exception,
+	 * do not rewrite it
+	 */
+	if (THREAD && !THREAD->pstate)
 		THREAD->pstate = pstate;
 
@@ -64,4 +68,11 @@
 		case EXC_TLBS:
 			tlb_invalid(pstate);
+			break;
+ 	 	case EXC_CpU:
+#ifdef FPU_LAZY     
+			scheduler_fpu_lazy_request();
+#else
+			panic("unhandled Coprocessor Unusable Exception\n");
+#endif
 			break;
 		case EXC_Mod:
@@ -88,11 +99,4 @@
 			panic("unhandled Reserved Instruction Exception\n");
 			break;
- 	 	case EXC_CpU:
-#ifdef FPU_LAZY     
-			scheduler_fpu_lazy_request();
-#else
-			panic("unhandled Coprocessor Unusable Exception\n");
-#endif
-			break;
  	 	case EXC_Ov:
 			panic("unhandled Arithmetic Overflow Exception\n");
@@ -118,6 +122,10 @@
 	
 	pstate->epc += epc_shift;
-	/* Probable not needed, but just for sure that nobody 
-	 * will continue accessing it */
+	/* Set to NULL, so that we can still support nested
+	 * exceptions
+	 * TODO: We should probably set EXL bit before this command,
+	 * nesting. On the other hand, if some exception occurs between
+	 * here and ERET, it won't set anything on the pstate anyway.
+	 */
 	if (THREAD)
 		THREAD->pstate = NULL;