Index: uspace/drv/audio/hdaudio/hdaudio.c =================================================================== --- uspace/drv/audio/hdaudio/hdaudio.c (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ uspace/drv/audio/hdaudio/hdaudio.c (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -58,5 +58,5 @@ static int hda_fun_offline(ddf_fun_t *fun); -static void hdaudio_interrupt(ddf_dev_t *, ipc_callid_t, ipc_call_t *); +static void hdaudio_interrupt(ipc_callid_t, ipc_call_t *, ddf_dev_t *); static driver_ops_t driver_ops = { @@ -366,6 +366,6 @@ } -static void hdaudio_interrupt(ddf_dev_t *dev, ipc_callid_t iid, - ipc_call_t *icall) +static void hdaudio_interrupt(ipc_callid_t iid, ipc_call_t *icall, + ddf_dev_t *dev) { hda_t *hda = (hda_t *)ddf_dev_data_get(dev); Index: uspace/drv/audio/sb16/main.c =================================================================== --- uspace/drv/audio/sb16/main.c (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ uspace/drv/audio/sb16/main.c (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -77,5 +77,5 @@ } -static void irq_handler(ddf_dev_t *dev, ipc_callid_t iid, ipc_call_t *call) +static void irq_handler(ipc_callid_t iid, ipc_call_t *call, ddf_dev_t *dev) { sb16_t *sb16_dev = ddf_dev_data_get(dev); Index: uspace/drv/block/ahci/ahci.c =================================================================== --- uspace/drv/block/ahci/ahci.c (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ uspace/drv/block/ahci/ahci.c (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -890,10 +890,10 @@ /** AHCI interrupt handler. * - * @param dev DDF device structure. * @param iid The IPC call id. * @param icall The IPC call structure. - * - */ -static void ahci_interrupt(ddf_dev_t *dev, ipc_callid_t iid, ipc_call_t *icall) + * @param dev DDF device structure. + * + */ +static void ahci_interrupt(ipc_callid_t iid, ipc_call_t *icall, ddf_dev_t *dev) { ahci_dev_t *ahci = dev_ahci_dev(dev); Index: uspace/drv/block/ata_bd/ata_bd.c =================================================================== --- uspace/drv/block/ata_bd/ata_bd.c (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ uspace/drv/block/ata_bd/ata_bd.c (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -54,5 +54,7 @@ #include #include +#include #include +#include #include #include @@ -95,4 +97,5 @@ static int ata_bd_get_block_size(bd_srv_t *, size_t *); static int ata_bd_get_num_blocks(bd_srv_t *, aoff64_t *); +static int ata_bd_sync_cache(bd_srv_t *, aoff64_t, size_t); static int ata_rcmd_read(disk_t *disk, uint64_t ba, size_t cnt, @@ -100,4 +103,5 @@ static int ata_rcmd_write(disk_t *disk, uint64_t ba, size_t cnt, const void *buf); +static int ata_rcmd_flush_cache(disk_t *disk); static int disk_init(ata_ctrl_t *ctrl, disk_t *d, int disk_id); static int ata_identify_dev(disk_t *disk, void *buf); @@ -127,5 +131,6 @@ .write_blocks = ata_bd_write_blocks, .get_block_size = ata_bd_get_block_size, - .get_num_blocks = ata_bd_get_num_blocks + .get_num_blocks = ata_bd_get_num_blocks, + .sync_cache = ata_bd_sync_cache }; @@ -343,5 +348,5 @@ identify_data_t idata; uint8_t model[40]; - ata_inquiry_data_t inq_data; + scsi_std_inquiry_data_t inq_data; size_t isize; uint16_t w; @@ -472,5 +477,5 @@ /* Check device type. */ - if (INQUIRY_PDEV_TYPE(inq_data.pdev_type) != PDEV_TYPE_CDROM) + if (INQUIRY_PDEV_TYPE(inq_data.pqual_devtype) != SCSI_DEV_CD_DVD) ddf_msg(LVL_WARN, "Peripheral device type is not CD-ROM."); @@ -584,4 +589,16 @@ } +/** Flush cache. */ +static int ata_bd_sync_cache(bd_srv_t *bd, uint64_t ba, size_t cnt) +{ + disk_t *disk = bd_srv_disk(bd); + + /* ATA cannot flush just some blocks, we just flush everything. */ + (void)ba; + (void)cnt; + + return ata_rcmd_flush_cache(disk); +} + /** PIO data-in command protocol. */ static int ata_pio_data_in(disk_t *disk, void *obuf, size_t obuf_size, @@ -637,4 +654,19 @@ } } + + if (status & SR_ERR) + return EIO; + + return EOK; +} + +/** PIO non-data command protocol. */ +static int ata_pio_nondata(disk_t *disk) +{ + ata_ctrl_t *ctrl = disk->ctrl; + uint8_t status; + + if (wait_status(ctrl, 0, ~SR_BSY, &status, TIMEOUT_BSY) != EOK) + return EIO; if (status & SR_ERR) @@ -831,13 +863,20 @@ size_t *rcvd_size) { - ata_pcmd_inquiry_t cp; + uint8_t cpb[12]; + scsi_cdb_inquiry_t *cp = (scsi_cdb_inquiry_t *)cpb; int rc; - memset(&cp, 0, sizeof(cp)); - - cp.opcode = PCMD_INQUIRY; - cp.alloc_len = min(obuf_size, 0xff); /* Allocation length */ - - rc = ata_cmd_packet(disk, &cp, sizeof(cp), obuf, obuf_size, rcvd_size); + memset(cpb, 0, sizeof(cpb)); + + /* + * For SFF 8020 compliance the inquiry must be padded to 12 bytes + * and allocation length must fit in one byte. + */ + cp->op_code = SCSI_CMD_INQUIRY; + + /* Allocation length */ + cp->alloc_len = host2uint16_t_be(min(obuf_size, 0xff)); + + rc = ata_cmd_packet(disk, cpb, sizeof(cpb), obuf, obuf_size, rcvd_size); if (rc != EOK) return rc; @@ -894,5 +933,5 @@ void *obuf, size_t obuf_size) { - ata_pcmd_read_12_t cp; + scsi_cdb_read_12_t cp; int rc; @@ -902,7 +941,7 @@ memset(&cp, 0, sizeof(cp)); - cp.opcode = PCMD_READ_12; - cp.ba = host2uint32_t_be(ba); - cp.nblocks = host2uint32_t_be(cnt); + cp.op_code = SCSI_CMD_READ_12; + cp.lba = host2uint32_t_be(ba); + cp.xfer_len = host2uint32_t_be(cnt); rc = ata_cmd_packet(disk, &cp, sizeof(cp), obuf, obuf_size, NULL); @@ -933,20 +972,21 @@ size_t obuf_size) { - ata_pcmd_read_toc_t cp; + uint8_t cpb[12]; + scsi_cdb_read_toc_t *cp = (scsi_cdb_read_toc_t *)cpb; int rc; - memset(&cp, 0, sizeof(cp)); - - cp.opcode = PCMD_READ_TOC; - cp.msf = 0; - cp.format = 0x01; /* 0x01 = multi-session mode */ - cp.start = session; - cp.size = host2uint16_t_be(obuf_size); - cp.oldformat = 0x40; /* 0x01 = multi-session mode (shifted to MSB) */ - - rc = ata_cmd_packet(disk, &cp, sizeof(cp), obuf, obuf_size, NULL); + memset(cpb, 0, sizeof(cpb)); + + cp->op_code = SCSI_CMD_READ_TOC; + cp->msf = 0; + cp->format = 0x01; /* 0x01 = multi-session mode */ + cp->track_sess_no = session; + cp->alloc_len = host2uint16_t_be(obuf_size); + cp->control = 0x40; /* 0x01 = multi-session mode (shifted to MSB) */ + + rc = ata_cmd_packet(disk, cpb, sizeof(cpb), obuf, obuf_size, NULL); if (rc != EOK) return rc; - + return EOK; } @@ -1066,4 +1106,44 @@ rc = ata_pio_data_out(disk, buf, cnt * disk->block_size, disk->block_size, cnt); + + fibril_mutex_unlock(&ctrl->lock); + return rc; +} + +/** Flush cached data to nonvolatile storage. + * + * @param disk Disk + * + * @return EOK on success, EIO on error. + */ +static int ata_rcmd_flush_cache(disk_t *disk) +{ + ata_ctrl_t *ctrl = disk->ctrl; + uint8_t drv_head; + int rc; + + /* New value for Drive/Head register */ + drv_head = + (disk_dev_idx(disk) != 0) ? DHR_DRV : 0; + + fibril_mutex_lock(&ctrl->lock); + + /* Program a Flush Cache operation. */ + + if (wait_status(ctrl, 0, ~SR_BSY, NULL, TIMEOUT_BSY) != EOK) { + fibril_mutex_unlock(&ctrl->lock); + return EIO; + } + + pio_write_8(&ctrl->cmd->drive_head, drv_head); + + if (wait_status(ctrl, SR_DRDY, ~SR_BSY, NULL, TIMEOUT_DRDY) != EOK) { + fibril_mutex_unlock(&ctrl->lock); + return EIO; + } + + pio_write_8(&ctrl->cmd->command, CMD_FLUSH_CACHE); + + rc = ata_pio_nondata(disk); fibril_mutex_unlock(&ctrl->lock); Index: uspace/drv/block/ata_bd/ata_hw.h =================================================================== --- uspace/drv/block/ata_bd/ata_hw.h (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ uspace/drv/block/ata_bd/ata_hw.h (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -136,5 +136,6 @@ CMD_PACKET = 0xA0, CMD_IDENTIFY_PKT_DEV = 0xA1, - CMD_IDENTIFY_DRIVE = 0xEC + CMD_IDENTIFY_DRIVE = 0xEC, + CMD_FLUSH_CACHE = 0xE7 }; @@ -241,71 +242,6 @@ }; -/** ATA packet command codes. */ -enum ata_pkt_command { - PCMD_INQUIRY = 0x12, - PCMD_READ_12 = 0xa8, - PCMD_READ_TOC = 0x43 -}; - -/** ATAPI Inquiry command */ -typedef struct { - uint8_t opcode; /**< Operation code (PCMD_INQUIRY) */ - uint8_t _res0; - uint8_t _res1; - uint8_t _res2; - uint8_t alloc_len; /**< Allocation length */ - uint8_t _res3; - uint8_t _res4; - uint8_t _res5; - uint32_t _res6; -} __attribute__ ((packed)) ata_pcmd_inquiry_t; - -/** ATAPI Read(12) command */ -typedef struct { - uint8_t opcode; /**< Operation code (PCMD_READ_12) */ - uint8_t _res0; - uint32_t ba; /**< Starting block address */ - uint32_t nblocks; /**< Number of blocks to transfer */ - uint8_t _res1; - uint8_t _res2; -} __attribute__ ((packed)) ata_pcmd_read_12_t; - -/** ATAPI Read TOC command */ -typedef struct { - uint8_t opcode; /**< Operation code (PCMD_READ_TOC) */ - uint8_t msf; /**< 0x2 = MSF bit set */ - uint8_t format; /**< low 3 bits */ - uint8_t _res0; - uint8_t _res1; - uint8_t _res2; - uint8_t start; /**< starting track/session number */ - uint16_t size; /**< Allocation length */ - uint8_t oldformat; /**< high 2 bits */ - uint8_t _res3; - uint8_t _res4; -} __attribute__ ((packed)) ata_pcmd_read_toc_t; - -/** Data returned from Inquiry command (mandatory part) */ -typedef struct { - uint8_t pdev_type; /** Reserved, Peripheral device type */ - uint8_t rmb; /** RMB, Reserved */ - uint8_t std_version; /** ISO version, ECMA version, ANSI version */ - uint8_t atapi_ver_rdf; /** ATAPI version, Response data format */ - uint8_t additional_len; /** Additional length */ - uint8_t _res0; - uint8_t _res1; - uint8_t _res2; - uint8_t vendor_id[8]; /** Vendor ID */ - uint8_t product_id[8]; /** Product ID */ - uint8_t product_rev[4]; /** Product revision level */ -} ata_inquiry_data_t; - -/** Extract value of ata_inquiry_data_t.pdev_type */ +/** Extract value of device type from scsi_std_inquiry_data_t.pqual_devtype */ #define INQUIRY_PDEV_TYPE(val) ((val) & 0x1f) - -/** Values for ata_inquiry_data_t.pdev_type */ -enum ata_pdev_type { - PDEV_TYPE_CDROM = 0x05 -}; enum ata_pdev_signature { Index: uspace/drv/bus/usb/ohci/ohci.c =================================================================== --- uspace/drv/bus/usb/ohci/ohci.c (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ uspace/drv/bus/usb/ohci/ohci.c (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -59,12 +59,13 @@ /** IRQ handling callback, identifies device * - * @param[in] dev DDF instance of the device to use. * @param[in] iid (Unused). * @param[in] call Pointer to the call that represents interrupt. - */ -static void irq_handler(ddf_dev_t *dev, ipc_callid_t iid, ipc_call_t *call) + * @param[in] dev DDF instance of the device to use. + * + */ +static void irq_handler(ipc_callid_t iid, ipc_call_t *call, ddf_dev_t *dev) { assert(dev); - + ohci_t *ohci = dev_to_ohci(dev); if (!ohci) { @@ -72,4 +73,5 @@ return; } + const uint16_t status = IPC_GET_ARG1(*call); hc_interrupt(&ohci->hc, status); Index: uspace/drv/bus/usb/uhci/hc.c =================================================================== --- uspace/drv/bus/usb/uhci/hc.c (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ uspace/drv/bus/usb/uhci/hc.c (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -151,5 +151,5 @@ return rc; } - + irq_code_t irq_code = { .rangecount = hc_irq_pio_range_count, @@ -158,13 +158,13 @@ .cmds = irq_cmds }; - - /* Register handler to avoid interrupt lockup */ - rc = register_interrupt_handler(device, irq, handler, &irq_code); - if (rc != EOK) { - usb_log_error("Failed to register interrupt handler: %s.\n", - str_error(rc)); - return rc; - } - + + /* Register handler to avoid interrupt lockup */ + rc = register_interrupt_handler(device, irq, handler, &irq_code); + if (rc != EOK) { + usb_log_error("Failed to register interrupt handler: %s.\n", + str_error(rc)); + return rc; + } + return EOK; } @@ -432,4 +432,6 @@ instance->transfers[USB_SPEED_FULL][USB_TRANSFER_BULK] = &instance->transfers_bulk_full; + instance->transfers[USB_SPEED_LOW][USB_TRANSFER_BULK] = + &instance->transfers_bulk_full; return EOK; Index: uspace/drv/bus/usb/uhci/uhci.c =================================================================== --- uspace/drv/bus/usb/uhci/uhci.c (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ uspace/drv/bus/usb/uhci/uhci.c (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -69,11 +69,13 @@ /** IRQ handling callback, forward status from call to diver structure. * - * @param[in] dev DDF instance of the device to use. * @param[in] iid (Unused). * @param[in] call Pointer to the call from kernel. - */ -static void irq_handler(ddf_dev_t *dev, ipc_callid_t iid, ipc_call_t *call) + * @param[in] dev DDF instance of the device to use. + * + */ +static void irq_handler(ipc_callid_t iid, ipc_call_t *call, ddf_dev_t *dev) { assert(dev); + uhci_t *uhci = dev_to_uhci(dev); if (!uhci) { @@ -81,4 +83,5 @@ return; } + const uint16_t status = IPC_GET_ARG1(*call); hc_interrupt(&uhci->hc, status); Index: uspace/drv/bus/usb/usbmast/main.c =================================================================== --- uspace/drv/bus/usb/usbmast/main.c (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ uspace/drv/bus/usb/usbmast/main.c (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -85,4 +85,5 @@ static int usbmast_bd_close(bd_srv_t *); static int usbmast_bd_read_blocks(bd_srv_t *, aoff64_t, size_t, void *, size_t); +static int usbmast_bd_sync_cache(bd_srv_t *, aoff64_t, size_t); static int usbmast_bd_write_blocks(bd_srv_t *, aoff64_t, size_t, const void *, size_t); static int usbmast_bd_get_block_size(bd_srv_t *, size_t *); @@ -93,4 +94,5 @@ .close = usbmast_bd_close, .read_blocks = usbmast_bd_read_blocks, + .sync_cache = usbmast_bd_sync_cache, .write_blocks = usbmast_bd_write_blocks, .get_block_size = usbmast_bd_get_block_size, @@ -338,4 +340,12 @@ } +/** Synchronize blocks to nonvolatile storage. */ +static int usbmast_bd_sync_cache(bd_srv_t *bd, uint64_t ba, size_t cnt) +{ + usbmast_fun_t *mfun = bd_srv_usbmast(bd); + + return usbmast_sync_cache(mfun, ba, cnt); +} + /** Write blocks to the device. */ static int usbmast_bd_write_blocks(bd_srv_t *bd, uint64_t ba, size_t cnt, Index: uspace/drv/bus/usb/usbmast/scsi_ms.c =================================================================== --- uspace/drv/bus/usb/usbmast/scsi_ms.c (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ uspace/drv/bus/usb/usbmast/scsi_ms.c (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -383,4 +383,51 @@ } +/** Perform SCSI Synchronize Cache command on USB mass storage device. + * + * @param mfun Mass storage function + * @param ba Address of first block + * @param nblocks Number of blocks to read + * @param data Data to write + * + * @return Error code + */ +int usbmast_sync_cache(usbmast_fun_t *mfun, uint64_t ba, size_t nblocks) +{ + scsi_cmd_t cmd; + scsi_cdb_sync_cache_10_t cdb; + int rc; + + if (ba > UINT32_MAX) + return ELIMIT; + + if (nblocks > UINT16_MAX) + return ELIMIT; + + memset(&cdb, 0, sizeof(cdb)); + cdb.op_code = SCSI_CMD_SYNC_CACHE_10; + cdb.lba = host2uint32_t_be(ba); + cdb.numlb = host2uint16_t_be(nblocks); + + memset(&cmd, 0, sizeof(cmd)); + cmd.cdb = &cdb; + cmd.cdb_size = sizeof(cdb); + + rc = usbmast_run_cmd(mfun, &cmd); + + if (rc != EOK) { + usb_log_error("Synchronize Cache (10) transport failed, device %s: %s.\n", + ddf_dev_get_name(mfun->mdev->ddf_dev), str_error(rc)); + return rc; + } + + if (cmd.status != CMDS_GOOD) { + usb_log_error("Synchronize Cache (10) command failed, device %s.\n", + ddf_dev_get_name(mfun->mdev->ddf_dev)); + return EIO; + } + + return EOK; +} + /** * @} Index: uspace/drv/bus/usb/usbmast/scsi_ms.h =================================================================== --- uspace/drv/bus/usb/usbmast/scsi_ms.h (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ uspace/drv/bus/usb/usbmast/scsi_ms.h (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -64,4 +64,5 @@ extern int usbmast_read(usbmast_fun_t *, uint64_t, size_t, void *); extern int usbmast_write(usbmast_fun_t *, uint64_t, size_t, const void *); +extern int usbmast_sync_cache(usbmast_fun_t *, uint64_t, size_t); extern const char *usbmast_scsi_dev_type_str(unsigned); Index: uspace/drv/char/i8042/i8042.c =================================================================== --- uspace/drv/char/i8042/i8042.c (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ uspace/drv/char/i8042/i8042.c (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -2,5 +2,5 @@ * Copyright (c) 2001-2004 Jakub Jermar * Copyright (c) 2006 Josef Cejka - * Copyright (c) 2009 Jiri Svoboda + * Copyright (c) 2014 Jiri Svoboda * Copyright (c) 2011 Jan Vesely * All rights reserved. @@ -39,11 +39,13 @@ */ +#include +#include +#include #include -#include #include #include #include -#include -#include +#include + #include "i8042.h" @@ -64,9 +66,11 @@ #define i8042_KBD_TRANSLATE 0x40 /* Use this to switch to XT scancodes */ -void default_handler(ddf_fun_t *, ipc_callid_t, ipc_call_t *); - -/** Port function operations. */ -static ddf_dev_ops_t ops = { - .default_handler = default_handler, +static void i8042_char_conn(ipc_callid_t, ipc_call_t *, void *); +static int i8042_read(chardev_srv_t *, void *, size_t); +static int i8042_write(chardev_srv_t *, const void *, size_t); + +static chardev_ops_t i8042_chardev_ops = { + .read = i8042_read, + .write = i8042_write }; @@ -106,10 +110,4 @@ }; -/** Get i8042 soft state from device node. */ -static i8042_t *dev_i8042(ddf_dev_t *dev) -{ - return ddf_dev_data_get(dev); -} - /** Wait until it is safe to write to the device. */ static void wait_ready(i8042_t *dev) @@ -123,13 +121,13 @@ * Write new data to the corresponding buffer. * - * @param dev Device that caued the interrupt. * @param iid Call id. * @param call pointerr to call data. - * - */ -static void i8042_irq_handler(ddf_dev_t *dev, ipc_callid_t iid, - ipc_call_t *call) -{ - i8042_t *controller = dev_i8042(dev); + * @param dev Device that caued the interrupt. + * + */ +static void i8042_irq_handler(ipc_callid_t iid, ipc_call_t *call, + ddf_dev_t *dev) +{ + i8042_t *controller = ddf_dev_data_get(dev); const uint8_t status = IPC_GET_ARG1(*call); @@ -186,4 +184,15 @@ }; + dev->kbd = ddf_fun_data_alloc(dev->kbd_fun, sizeof(i8042_port_t)); + if (dev->kbd == NULL) { + rc = ENOMEM; + goto error; + } + + dev->kbd->ctl = dev; + chardev_srvs_init(&dev->kbd->cds); + dev->kbd->cds.ops = &i8042_chardev_ops; + dev->kbd->cds.sarg = dev->kbd; + rc = ddf_fun_add_match_id(dev->kbd_fun, "char/xtkbd", 90); if (rc != EOK) @@ -196,10 +205,21 @@ } + dev->aux = ddf_fun_data_alloc(dev->aux_fun, sizeof(i8042_port_t)); + if (dev->aux == NULL) { + rc = ENOMEM; + goto error; + } + + dev->aux->ctl = dev; + chardev_srvs_init(&dev->aux->cds); + dev->aux->cds.ops = &i8042_chardev_ops; + dev->aux->cds.sarg = dev->aux; + rc = ddf_fun_add_match_id(dev->aux_fun, "char/ps2mouse", 90); if (rc != EOK) goto error; - ddf_fun_set_ops(dev->kbd_fun, &ops); - ddf_fun_set_ops(dev->aux_fun, &ops); + ddf_fun_set_conn_handler(dev->kbd_fun, i8042_char_conn); + ddf_fun_set_conn_handler(dev->aux_fun, i8042_char_conn); buffer_init(&dev->kbd_buffer, dev->kbd_data, BUFFER_SIZE); @@ -298,36 +318,33 @@ } -// FIXME TODO use shared instead this -enum { - IPC_CHAR_READ = DEV_FIRST_CUSTOM_METHOD, - IPC_CHAR_WRITE, -}; - /** Write data to i8042 port. * - * @param fun DDF function. - * @param buffer Data source. - * @param size Data size. + * @param srv Connection-specific data + * @param buffer Data source + * @param size Data size * * @return Bytes written. * */ -static int i8042_write(ddf_fun_t *fun, char *buffer, size_t size) -{ - i8042_t *controller = dev_i8042(ddf_fun_get_dev(fun)); - fibril_mutex_lock(&controller->write_guard); +static int i8042_write(chardev_srv_t *srv, const void *data, size_t size) +{ + i8042_port_t *port = (i8042_port_t *)srv->srvs->sarg; + i8042_t *i8042 = port->ctl; + const char *dp = (const char *)data; + + fibril_mutex_lock(&i8042->write_guard); for (size_t i = 0; i < size; ++i) { - if (controller->aux_fun == fun) { - wait_ready(controller); - pio_write_8(&controller->regs->status, + if (port == i8042->aux) { + wait_ready(i8042); + pio_write_8(&i8042->regs->status, i8042_CMD_WRITE_AUX); } - wait_ready(controller); - pio_write_8(&controller->regs->data, buffer[i]); - } - - fibril_mutex_unlock(&controller->write_guard); + wait_ready(i8042); + pio_write_8(&i8042->regs->data, dp[i]); + } + + fibril_mutex_unlock(&i8042->write_guard); return size; } @@ -335,19 +352,22 @@ /** Read data from i8042 port. * - * @param fun DDF function. - * @param buffer Data place. - * @param size Data place size. + * @param srv Connection-specific data + * @param buffer Data place + * @param size Data place size * * @return Bytes read. * */ -static int i8042_read(ddf_fun_t *fun, char *data, size_t size) -{ - i8042_t *controller = dev_i8042(ddf_fun_get_dev(fun)); - buffer_t *buffer = (fun == controller->aux_fun) ? - &controller->aux_buffer : &controller->kbd_buffer; +static int i8042_read(chardev_srv_t *srv, void *dest, size_t size) +{ + i8042_port_t *port = (i8042_port_t *)srv->srvs->sarg; + i8042_t *i8042 = port->ctl; + uint8_t *destp = (uint8_t *)dest; + + buffer_t *buffer = (port == i8042->aux) ? + &i8042->aux_buffer : &i8042->kbd_buffer; for (size_t i = 0; i < size; ++i) - *data++ = buffer_read(buffer); + *destp++ = buffer_read(buffer); return size; @@ -356,42 +376,13 @@ /** Handle data requests. * - * @param fun ddf_fun_t function. * @param id callid * @param call IPC request. - * - */ -void default_handler(ddf_fun_t *fun, ipc_callid_t id, ipc_call_t *call) -{ - const sysarg_t method = IPC_GET_IMETHOD(*call); - const size_t size = IPC_GET_ARG1(*call); - - switch (method) { - case IPC_CHAR_READ: - if (size <= 4 * sizeof(sysarg_t)) { - sysarg_t message[4] = {}; - - i8042_read(fun, (char *) message, size); - async_answer_4(id, size, message[0], message[1], - message[2], message[3]); - } else - async_answer_0(id, ELIMIT); - break; - - case IPC_CHAR_WRITE: - if (size <= 3 * sizeof(sysarg_t)) { - const sysarg_t message[3] = { - IPC_GET_ARG2(*call), - IPC_GET_ARG3(*call), - IPC_GET_ARG4(*call) - }; - - i8042_write(fun, (char *) message, size); - async_answer_0(id, size); - } else - async_answer_0(id, ELIMIT); - - default: - async_answer_0(id, EINVAL); - } + * @param arg ddf_fun_t function. + */ +void i8042_char_conn(ipc_callid_t iid, ipc_call_t *icall, void *arg) +{ + i8042_port_t *port = ddf_fun_data_get((ddf_fun_t *)arg); + + chardev_conn(iid, icall, &port->cds); } Index: uspace/drv/char/i8042/i8042.h =================================================================== --- uspace/drv/char/i8042/i8042.h (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ uspace/drv/char/i8042/i8042.h (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -40,4 +40,5 @@ #define i8042_H_ +#include #include #include @@ -56,5 +57,11 @@ } __attribute__ ((packed)) i8042_regs_t; -/** i8042 driver structure. */ +/** i8042 Port. */ +typedef struct { + struct i8042 *ctl; /**< Controller */ + chardev_srvs_t cds; /**< Character device server data */ +} i8042_port_t; + +/** i8042 Controller. */ typedef struct i8042 { i8042_regs_t *regs; /**< I/O registers. */ @@ -65,8 +72,11 @@ uint8_t aux_data[BUFFER_SIZE]; /**< Primary port buffer space. */ uint8_t kbd_data[BUFFER_SIZE]; /**< Aux. port buffer space. */ + i8042_port_t *kbd; + i8042_port_t *aux; fibril_mutex_t write_guard; /**< Prevents simultanous port writes.*/ } i8042_t; -int i8042_init(i8042_t *, addr_range_t *, int, int, ddf_dev_t *); + +extern int i8042_init(i8042_t *, addr_range_t *, int, int, ddf_dev_t *); #endif Index: uspace/drv/char/i8042/main.c =================================================================== --- uspace/drv/char/i8042/main.c (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ uspace/drv/char/i8042/main.c (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -157,5 +157,5 @@ * interrupt storms when the default large stacks are used. */ - async_set_interrupt_handler_stack_size(PAGE_SIZE); + async_set_notification_handler_stack_size(PAGE_SIZE); return ddf_driver_main(&i8042_driver); Index: uspace/drv/char/ns8250/ns8250.c =================================================================== --- uspace/drv/char/ns8250/ns8250.c (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ uspace/drv/char/ns8250/ns8250.c (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -764,8 +764,9 @@ * data and reading the line status register. * - * @param dev The serial port device. - */ -static inline void ns8250_interrupt_handler(ddf_dev_t *dev, ipc_callid_t iid, - ipc_call_t *icall) + * @param dev The serial port device. + * + */ +static inline void ns8250_interrupt_handler(ipc_callid_t iid, ipc_call_t *icall, + ddf_dev_t *dev) { ns8250_t *ns = dev_ns8250(dev); Index: uspace/drv/char/pl050/Makefile =================================================================== --- uspace/drv/char/pl050/Makefile (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) +++ uspace/drv/char/pl050/Makefile (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -0,0 +1,37 @@ +# +# Copyright (c) 2014 Jiri Svoboda +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# - Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# - Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# - The name of the author may not be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +USPACE_PREFIX = ../../.. +LIBS = $(LIBDRV_PREFIX)/libdrv.a +EXTRA_CFLAGS += -I$(LIBDRV_PREFIX)/include +BINARY = pl050 + +SOURCES = \ + pl050.c + +include $(USPACE_PREFIX)/Makefile.common Index: uspace/drv/char/pl050/pl050.c =================================================================== --- uspace/drv/char/pl050/pl050.c (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) +++ uspace/drv/char/pl050/pl050.c (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -0,0 +1,383 @@ +/* + * Copyright (c) 2009 Vineeth Pillai + * Copyright (c) 2014 Jiri Svoboda + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @file + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pl050_hw.h" + +#define NAME "pl050" + +enum { + buffer_size = 64 +}; + +static int pl050_dev_add(ddf_dev_t *); +static int pl050_fun_online(ddf_fun_t *); +static int pl050_fun_offline(ddf_fun_t *); +static void pl050_char_conn(ipc_callid_t, ipc_call_t *, void *); +static int pl050_read(chardev_srv_t *, void *, size_t); +static int pl050_write(chardev_srv_t *, const void *, size_t); + +static driver_ops_t driver_ops = { + .dev_add = &pl050_dev_add, + .fun_online = &pl050_fun_online, + .fun_offline = &pl050_fun_offline +}; + +static driver_t pl050_driver = { + .name = NAME, + .driver_ops = &driver_ops +}; + +static chardev_ops_t pl050_chardev_ops = { + .read = pl050_read, + .write = pl050_write +}; + +typedef struct { + async_sess_t *parent_sess; + ddf_dev_t *dev; + char *name; + + ddf_fun_t *fun_a; + chardev_srvs_t cds; + + uintptr_t iobase; + size_t iosize; + kmi_regs_t *regs; + uint8_t buffer[buffer_size]; + size_t buf_rp; + size_t buf_wp; + fibril_condvar_t buf_cv; + fibril_mutex_t buf_lock; +} pl050_t; + +static irq_pio_range_t pl050_ranges[] = { + { + .base = 0, + .size = 9, + } +}; + +static irq_cmd_t pl050_cmds[] = { + { + .cmd = CMD_PIO_READ_8, + .addr = NULL, + .dstarg = 1 + }, + { + .cmd = CMD_AND, + .value = BIT_V(uint8_t, kmi_stat_rxfull), + .srcarg = 1, + .dstarg = 3 + }, + { + .cmd = CMD_PREDICATE, + .value = 2, + .srcarg = 3 + }, + { + .cmd = CMD_PIO_READ_8, + .addr = NULL, /* Will be patched in run-time */ + .dstarg = 2 + }, + { + .cmd = CMD_ACCEPT + } +}; + +static irq_code_t pl050_irq_code = { + sizeof(pl050_ranges) / sizeof(irq_pio_range_t), + pl050_ranges, + sizeof(pl050_cmds) / sizeof(irq_cmd_t), + pl050_cmds +}; + +static pl050_t *pl050_from_fun(ddf_fun_t *fun) +{ + return (pl050_t *)ddf_dev_data_get(ddf_fun_get_dev(fun)); +} + +static void pl050_interrupt(ipc_callid_t iid, ipc_call_t *call, ddf_dev_t *dev) +{ + pl050_t *pl050 = (pl050_t *)ddf_dev_data_get(dev); + size_t nidx; + + fibril_mutex_lock(&pl050->buf_lock); + nidx = (pl050->buf_wp + 1) % buffer_size; + if (nidx == pl050->buf_rp) { + /** Buffer overrunt */ + ddf_msg(LVL_WARN, "Buffer overrun."); + fibril_mutex_unlock(&pl050->buf_lock); + return; + } + + pl050->buffer[pl050->buf_wp] = IPC_GET_ARG2(*call); + pl050->buf_wp = nidx; + fibril_condvar_broadcast(&pl050->buf_cv); + fibril_mutex_unlock(&pl050->buf_lock); +} + +static int pl050_init(pl050_t *pl050) +{ + hw_res_list_parsed_t res; + void *regs; + int rc; + + fibril_mutex_initialize(&pl050->buf_lock); + fibril_condvar_initialize(&pl050->buf_cv); + pl050->buf_rp = pl050->buf_wp = 0; + + pl050->parent_sess = ddf_dev_parent_sess_create(pl050->dev, + EXCHANGE_SERIALIZE); + if (pl050->parent_sess == NULL) { + ddf_msg(LVL_ERROR, "Failed connecitng parent driver."); + rc = ENOMEM; + goto error; + } + + hw_res_list_parsed_init(&res); + rc = hw_res_get_list_parsed(pl050->parent_sess, &res, 0); + if (rc != EOK) { + ddf_msg(LVL_ERROR, "Failed getting resource list."); + goto error; + } + + if (res.mem_ranges.count != 1) { + ddf_msg(LVL_ERROR, "Expected exactly one memory range."); + rc = EINVAL; + goto error; + } + + pl050->iobase = RNGABS(res.mem_ranges.ranges[0]); + pl050->iosize = RNGSZ(res.mem_ranges.ranges[0]); + + pl050_irq_code.ranges[0].base = pl050->iobase; + kmi_regs_t *regsphys = (kmi_regs_t *) pl050->iobase; + pl050_irq_code.cmds[0].addr = ®sphys->stat; + pl050_irq_code.cmds[3].addr = ®sphys->data; + + if (res.irqs.count != 1) { + ddf_msg(LVL_ERROR, "Expected exactly one IRQ."); + rc = EINVAL; + goto error; + } + + ddf_msg(LVL_DEBUG, "iobase=%p irq=%d", (void *)pl050->iobase, + res.irqs.irqs[0]); + + rc = pio_enable((void *)pl050->iobase, sizeof(kmi_regs_t), ®s); + if (rc != EOK) { + ddf_msg(LVL_ERROR, "Error enabling PIO"); + goto error; + } + + pl050->regs = regs; + + rc = register_interrupt_handler(pl050->dev, res.irqs.irqs[0], + pl050_interrupt, &pl050_irq_code); + if (rc != EOK) { + ddf_msg(LVL_ERROR, "Failed registering interrupt handler. (%d)", + rc); + goto error; + } + + rc = irc_enable_interrupt(res.irqs.irqs[0]); + if (rc != EOK) { + ddf_msg(LVL_ERROR, "Failed enabling interrupt. (%d)", rc); + goto error; + } + + pio_write_8(&pl050->regs->cr, + BIT_V(uint8_t, kmi_cr_enable) | + BIT_V(uint8_t, kmi_cr_rxintr)); + + return EOK; +error: + return rc; +} + +static int pl050_read(chardev_srv_t *srv, void *buffer, size_t size) +{ + pl050_t *pl050 = (pl050_t *)srv->srvs->sarg; + uint8_t *bp = buffer; + size_t left; + + fibril_mutex_lock(&pl050->buf_lock); + + left = size; + while (left > 0) { + while (pl050->buf_rp == pl050->buf_wp) + fibril_condvar_wait(&pl050->buf_cv, &pl050->buf_lock); + *bp++ = pl050->buffer[pl050->buf_rp]; + --left; + pl050->buf_rp = (pl050->buf_rp + 1) % buffer_size; + } + + fibril_mutex_unlock(&pl050->buf_lock); + + return size; +} + +static int pl050_write(chardev_srv_t *srv, const void *data, size_t size) +{ + pl050_t *pl050 = (pl050_t *)srv->srvs->sarg; + uint8_t *dp = (uint8_t *)data; + uint8_t status; + size_t i; + + ddf_msg(LVL_NOTE, "%s/pl050_write(%zu bytes)", pl050->name, size); + for (i = 0; i < size; i++) { + while (true) { + status = pio_read_8(&pl050->regs->stat); + if ((status & BIT_V(uint8_t, kmi_stat_txempty)) != 0) + break; + } + pio_write_8(&pl050->regs->data, dp[i]); + } + ddf_msg(LVL_NOTE, "%s/pl050_write() success", pl050->name); + + return size; +} + +void pl050_char_conn(ipc_callid_t iid, ipc_call_t *icall, void *arg) +{ + pl050_t *pl050 = pl050_from_fun((ddf_fun_t *)arg); + + chardev_conn(iid, icall, &pl050->cds); +} + +/** Add device. */ +static int pl050_dev_add(ddf_dev_t *dev) +{ + ddf_fun_t *fun_a; + pl050_t *pl050 = NULL; + const char *mname; + int rc; + + ddf_msg(LVL_DEBUG, "pl050_dev_add()"); + + pl050 = ddf_dev_data_alloc(dev, sizeof(pl050_t)); + if (pl050 == NULL) { + ddf_msg(LVL_ERROR, "Failed allocating soft state.\n"); + rc = ENOMEM; + goto error; + } + + pl050->name = (char *)ddf_dev_get_name(dev); + if (pl050->name == NULL) { + rc = ENOMEM; + goto error; + } + + fun_a = ddf_fun_create(dev, fun_inner, "a"); + if (fun_a == NULL) { + ddf_msg(LVL_ERROR, "Failed creating function 'a'."); + rc = ENOMEM; + goto error; + } + + pl050->fun_a = fun_a; + pl050->dev = dev; + + rc = pl050_init(pl050); + if (rc != EOK) + goto error; + + if (str_cmp(pl050->name, "kbd") == 0) + mname = "char/xtkbd"; + else + mname = "char/ps2mouse"; + + rc = ddf_fun_add_match_id(fun_a, mname, 10); + if (rc != EOK) { + ddf_msg(LVL_ERROR, "Failed adding match IDs to function %s", + "char/xtkbd"); + goto error; + } + + chardev_srvs_init(&pl050->cds); + pl050->cds.ops = &pl050_chardev_ops; + pl050->cds.sarg = pl050; + + ddf_fun_set_conn_handler(fun_a, pl050_char_conn); + + rc = ddf_fun_bind(fun_a); + if (rc != EOK) { + ddf_msg(LVL_ERROR, "Failed binding function 'a'. (%d)", rc); + ddf_fun_destroy(fun_a); + goto error; + } + + ddf_msg(LVL_DEBUG, "Device added."); + return EOK; +error: + if (pl050 != NULL) + free(pl050->name); + return rc; +} + +static int pl050_fun_online(ddf_fun_t *fun) +{ + ddf_msg(LVL_DEBUG, "pl050_fun_online()"); + return ddf_fun_online(fun); +} + +static int pl050_fun_offline(ddf_fun_t *fun) +{ + ddf_msg(LVL_DEBUG, "pl050_fun_offline()"); + return ddf_fun_offline(fun); +} + +int main(int argc, char *argv[]) +{ + int rc; + + printf(NAME ": HelenOS pl050 serial device driver\n"); + rc = ddf_log_init(NAME); + if (rc != EOK) { + printf(NAME ": Error connecting logging service."); + return 1; + } + + return ddf_driver_main(&pl050_driver); +} + Index: uspace/drv/char/pl050/pl050.ma =================================================================== --- uspace/drv/char/pl050/pl050.ma (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) +++ uspace/drv/char/pl050/pl050.ma (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -0,0 +1,1 @@ +10 arm/pl050 Index: uspace/drv/char/pl050/pl050_hw.h =================================================================== --- uspace/drv/char/pl050/pl050_hw.h (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) +++ uspace/drv/char/pl050/pl050_hw.h (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2009 Vineeth Pillai + * Copyright (c) 2014 Jiri Svoboda + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup pl050 + * @{ + */ +/** @file ARM PrimeCell PS2 Keyboard/Mouse Interface (PL050) registers + */ + +#ifndef PL050_HW_H +#define PL050_HW_H + +#include + +typedef struct { + /** Control register */ + uint8_t cr; + /** Padding */ + uint8_t pad1[3]; + /** Status register */ + uint8_t stat; + /** Padding */ + uint8_t pad5[3]; + /** Received data */ + uint8_t data; + /** Padding */ + uint8_t pad9[3]; + /** Clock divisor */ + uint8_t clkdiv; + /** Padding */ + uint8_t pad13[3]; + /** Interrupt status register */ + uint8_t ir; + /** Padding */ + uint8_t pad17[3]; +} kmi_regs_t; + +typedef enum { + /** 0 = PS2 mode, 1 = No line control bit mode */ + kmi_cr_type = 5, + /** Enable receiver interrupt */ + kmi_cr_rxintr = 4, + /** Enable transmitter interrupt */ + kmi_cr_txintr = 3, + /** Enable PrimeCell KMI */ + kmi_cr_enable = 2, + /** Force KMI data LOW */ + kmi_cr_forcedata = 1, + /** Force KMI clock LOW */ + kmi_cr_forceclock = 0 +} kmi_cr_bits_t; + +typedef enum { + kmi_stat_txempty = 6, + kmi_stat_txbusy = 5, + kmi_stat_rxfull = 4, + kmi_stat_rxbusy = 3, + kmi_stat_rxparity = 2, + kmi_stat_clkin = 1, + kmi_stat_datain = 0 +} kmi_stat_bits_t; + +#endif + +/** @} + */ Index: uspace/drv/char/ps2mouse/Makefile =================================================================== --- uspace/drv/char/ps2mouse/Makefile (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ uspace/drv/char/ps2mouse/Makefile (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -33,5 +33,4 @@ SOURCES = \ - chardev.c \ main.c \ ps2mouse.c Index: uspace/drv/char/ps2mouse/chardev.c =================================================================== --- uspace/drv/char/ps2mouse/chardev.c (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ (revision ) @@ -1,68 +1,0 @@ -/* - * Copyright (c) 2011 Jan Vesely - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include - -#include "chardev.h" - -// TODO make this shared -enum { - IPC_CHAR_READ = DEV_FIRST_CUSTOM_METHOD, - IPC_CHAR_WRITE, -}; - -ssize_t chardev_read(async_exch_t *exch, void *data, size_t size) -{ - if (!exch) - return EBADMEM; - if (size > 4 * sizeof(sysarg_t)) - return ELIMIT; - - sysarg_t message[4] = { 0 }; - const ssize_t ret = async_req_1_4(exch, IPC_CHAR_READ, size, - &message[0], &message[1], &message[2], &message[3]); - if (ret > 0 && (size_t)ret <= size) - memcpy(data, message, size); - return ret; -} - -ssize_t chardev_write(async_exch_t *exch, const void *data, size_t size) -{ - if (!exch) - return EBADMEM; - if (size > 3 * sizeof(sysarg_t)) - return ELIMIT; - - sysarg_t message[3] = { 0 }; - memcpy(message, data, size); - return async_req_4_0(exch, IPC_CHAR_WRITE, size, - message[0], message[1], message[2]); -} Index: uspace/drv/char/ps2mouse/chardev.h =================================================================== --- uspace/drv/char/ps2mouse/chardev.h (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ (revision ) @@ -1,47 +1,0 @@ -/* - * Copyright (c) 2011 Jan Vesely - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** @addtogroup drvmouse - * @{ - */ -/** @file - * @brief ps/2 mouse driver. - */ - -#ifndef _CHARDEV_H_ -#define _CHARDEV_H_ - -#include -#include - -ssize_t chardev_read(async_exch_t *, void *, size_t); -ssize_t chardev_write(async_exch_t *, const void *, size_t); - -#endif -/** - * @} - */ Index: uspace/drv/char/ps2mouse/ps2mouse.c =================================================================== --- uspace/drv/char/ps2mouse/ps2mouse.c (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ uspace/drv/char/ps2mouse/ps2mouse.c (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -37,4 +37,5 @@ #include #include +#include #include #include @@ -42,5 +43,4 @@ #include "ps2mouse.h" -#include "chardev.h" #define PS2_MOUSE_GET_DEVICE_ID 0xf2 Index: uspace/drv/char/xtkbd/Makefile =================================================================== --- uspace/drv/char/xtkbd/Makefile (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ uspace/drv/char/xtkbd/Makefile (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -33,5 +33,4 @@ SOURCES = \ - chardev.c \ main.c \ xtkbd.c Index: uspace/drv/char/xtkbd/chardev.c =================================================================== --- uspace/drv/char/xtkbd/chardev.c (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ (revision ) @@ -1,68 +1,0 @@ -/* - * Copyright (c) 2011 Jan Vesely - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include - -#include "chardev.h" - -// TODO make this shared -enum { - IPC_CHAR_READ = DEV_FIRST_CUSTOM_METHOD, - IPC_CHAR_WRITE, -}; - -ssize_t chardev_read(async_exch_t *exch, void *data, size_t size) -{ - if (!exch) - return EBADMEM; - if (size > 4 * sizeof(sysarg_t)) - return ELIMIT; - - sysarg_t message[4] = { 0 }; - const ssize_t ret = async_req_1_4(exch, IPC_CHAR_READ, size, - &message[0], &message[1], &message[2], &message[3]); - if (ret > 0 && (size_t)ret <= size) - memcpy(data, message, size); - return ret; -} - -ssize_t chardev_write(async_exch_t *exch, const void *data, size_t size) -{ - if (!exch) - return EBADMEM; - if (size > 3 * sizeof(sysarg_t)) - return ELIMIT; - - sysarg_t message[3] = { 0 }; - memcpy(message, data, size); - return async_req_4_0(exch, IPC_CHAR_WRITE, size, - message[0], message[1], message[2]); -} Index: uspace/drv/char/xtkbd/chardev.h =================================================================== --- uspace/drv/char/xtkbd/chardev.h (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ (revision ) @@ -1,47 +1,0 @@ -/* - * Copyright (c) 2011 Jan Vesely - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** @addtogroup drvkbd - * @{ - */ -/** @file - * @brief ps/2 mouse driver. - */ - -#ifndef _CHARDEV_H_ -#define _CHARDEV_H_ - -#include -#include - -ssize_t chardev_read(async_exch_t *, void *, size_t); -ssize_t chardev_write(async_exch_t *, const void *, size_t); - -#endif -/** - * @} - */ Index: uspace/drv/char/xtkbd/xtkbd.c =================================================================== --- uspace/drv/char/xtkbd/xtkbd.c (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ uspace/drv/char/xtkbd/xtkbd.c (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -36,9 +36,9 @@ #include #include +#include #include #include #include -#include "chardev.h" #include "xtkbd.h" @@ -159,5 +159,5 @@ static const int scanmap_e0[] = { [0x38] = KC_RALT, - [0x1d] = KC_RSHIFT, + [0x1d] = KC_RCTRL, [0x37] = KC_PRTSCR, @@ -199,5 +199,5 @@ * @param dev DDF device structure. * - * Connects to parent, creates mouse function, starts polling fibril. + * Connects to parent, creates keyboard function, starts polling fibril. */ int xt_kbd_init(xt_kbd_t *kbd, ddf_dev_t *dev) @@ -207,9 +207,12 @@ kbd->client_sess = NULL; kbd->parent_sess = ddf_dev_parent_sess_create(dev, EXCHANGE_SERIALIZE); - if (!kbd->parent_sess) - return ENOMEM; + if (!kbd->parent_sess) { + ddf_msg(LVL_ERROR, "Failed creating parent session."); + return EIO; + } kbd->kbd_fun = ddf_fun_create(dev, fun_exposed, "kbd"); if (!kbd->kbd_fun) { + ddf_msg(LVL_ERROR, "Failed creating function 'kbd'."); return ENOMEM; } @@ -218,10 +221,13 @@ int ret = ddf_fun_bind(kbd->kbd_fun); if (ret != EOK) { + ddf_msg(LVL_ERROR, "Failed binding function 'kbd'."); ddf_fun_destroy(kbd->kbd_fun); - return ENOMEM; + return EEXIST; } ret = ddf_fun_add_to_category(kbd->kbd_fun, "keyboard"); if (ret != EOK) { + ddf_msg(LVL_ERROR, "Failed adding function 'kbd' to category " + "'keyboard'."); ddf_fun_unbind(kbd->kbd_fun); ddf_fun_destroy(kbd->kbd_fun); @@ -231,8 +237,10 @@ kbd->polling_fibril = fibril_create(polling, kbd); if (!kbd->polling_fibril) { + ddf_msg(LVL_ERROR, "Failed creating polling fibril."); ddf_fun_unbind(kbd->kbd_fun); ddf_fun_destroy(kbd->kbd_fun); return ENOMEM; } + fibril_add_ready(kbd->polling_fibril); return EOK; @@ -241,5 +249,5 @@ /** Get data and parse scancodes. * @param arg Pointer to xt_kbd_t structure. - * @return Never. + * @return EIO on error. */ int polling(void *arg) @@ -259,4 +267,6 @@ uint8_t code = 0; ssize_t size = chardev_read(parent_exch, &code, 1); + if (size != 1) + return EIO; /** Ignore AT command reply */ @@ -269,12 +279,9 @@ map_size = sizeof(scanmap_e0) / sizeof(int); size = chardev_read(parent_exch, &code, 1); + if (size != 1) + return EIO; + // TODO handle print screen } - - /* Invalid read. */ - if (size != 1) { - continue; - } - /* Bit 7 indicates press/release */ Index: uspace/drv/infrastructure/root/Makefile =================================================================== --- uspace/drv/infrastructure/root/Makefile (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ (revision ) @@ -1,37 +1,0 @@ -# -# Copyright (c) 2010 Lenka Trochtova -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# - Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# - Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# - The name of the author may not be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# - -USPACE_PREFIX = ../../.. -LIBS = $(LIBDRV_PREFIX)/libdrv.a -EXTRA_CFLAGS += -I$(LIBDRV_PREFIX)/include -BINARY = root - -SOURCES = \ - root.c - -include $(USPACE_PREFIX)/Makefile.common Index: uspace/drv/infrastructure/root/root.c =================================================================== --- uspace/drv/infrastructure/root/root.c (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ (revision ) @@ -1,248 +1,0 @@ -/* - * Copyright (c) 2010 Lenka Trochtova - * Copyright (c) 2010 Vojtech Horky - * Copyright (c) 2011 Jiri Svoboda - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** - * @defgroup root Root device driver. - * @brief HelenOS root device driver. - * @{ - */ - -/** @file - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#define NAME "root" - -#define PLATFORM_FUN_NAME "hw" -#define PLATFORM_FUN_MATCH_ID_FMT "platform/%s" -#define PLATFORM_FUN_MATCH_SCORE 100 - -#define VIRTUAL_FUN_NAME "virt" -#define VIRTUAL_FUN_MATCH_ID "rootvirt" -#define VIRTUAL_FUN_MATCH_SCORE 100 - -static int root_dev_add(ddf_dev_t *dev); -static int root_fun_online(ddf_fun_t *fun); -static int root_fun_offline(ddf_fun_t *fun); - -/** The root device driver's standard operations. */ -static driver_ops_t root_ops = { - .dev_add = &root_dev_add, - .fun_online = &root_fun_online, - .fun_offline = &root_fun_offline -}; - -/** The root device driver structure. */ -static driver_t root_driver = { - .name = NAME, - .driver_ops = &root_ops -}; - -/** Create the function which represents the root of virtual device tree. - * - * @param dev Device - * @return EOK on success or negative error code - */ -static int add_virtual_root_fun(ddf_dev_t *dev) -{ - const char *name = VIRTUAL_FUN_NAME; - ddf_fun_t *fun; - int rc; - - ddf_msg(LVL_DEBUG, "Adding new function for virtual devices. " - "Function node is `%s' (%d %s)", name, - VIRTUAL_FUN_MATCH_SCORE, VIRTUAL_FUN_MATCH_ID); - - fun = ddf_fun_create(dev, fun_inner, name); - if (fun == NULL) { - ddf_msg(LVL_ERROR, "Failed creating function %s", name); - return ENOMEM; - } - - rc = ddf_fun_add_match_id(fun, VIRTUAL_FUN_MATCH_ID, - VIRTUAL_FUN_MATCH_SCORE); - if (rc != EOK) { - ddf_msg(LVL_ERROR, "Failed adding match IDs to function %s", - name); - ddf_fun_destroy(fun); - return rc; - } - - rc = ddf_fun_bind(fun); - if (rc != EOK) { - ddf_msg(LVL_ERROR, "Failed binding function %s: %s", name, - str_error(rc)); - ddf_fun_destroy(fun); - return rc; - } - - return EOK; -} - -/** Create the function which represents the root of HW device tree. - * - * @param dev Device - * @return EOK on success or negative error code - */ -static int add_platform_fun(ddf_dev_t *dev) -{ - char *match_id; - char *platform; - size_t platform_size; - - const char *name = PLATFORM_FUN_NAME; - ddf_fun_t *fun; - int rc; - - /* Get platform name from sysinfo. */ - platform = sysinfo_get_data("platform", &platform_size); - if (platform == NULL) { - ddf_msg(LVL_ERROR, "Failed to obtain platform name."); - return ENOENT; - } - - /* Null-terminate string. */ - platform = realloc(platform, platform_size + 1); - if (platform == NULL) { - ddf_msg(LVL_ERROR, "Memory allocation failed."); - return ENOMEM; - } - - platform[platform_size] = '\0'; - - /* Construct match ID. */ - if (asprintf(&match_id, PLATFORM_FUN_MATCH_ID_FMT, platform) == -1) { - ddf_msg(LVL_ERROR, "Memory allocation failed."); - free(platform); - return ENOMEM; - } - - free(platform); - - /* Add function. */ - ddf_msg(LVL_DEBUG, "Adding platform function. Function node is `%s' " - " (%d %s)", PLATFORM_FUN_NAME, PLATFORM_FUN_MATCH_SCORE, - match_id); - - fun = ddf_fun_create(dev, fun_inner, name); - if (fun == NULL) { - ddf_msg(LVL_ERROR, "Error creating function %s", name); - free(match_id); - return ENOMEM; - } - - rc = ddf_fun_add_match_id(fun, match_id, PLATFORM_FUN_MATCH_SCORE); - if (rc != EOK) { - ddf_msg(LVL_ERROR, "Failed adding match IDs to function %s", - name); - free(match_id); - ddf_fun_destroy(fun); - return rc; - } - - free(match_id); - - rc = ddf_fun_bind(fun); - if (rc != EOK) { - ddf_msg(LVL_ERROR, "Failed binding function %s: %s", name, - str_error(rc)); - ddf_fun_destroy(fun); - return rc; - } - - return EOK; -} - -/** Get the root device. - * - * @param dev The device which is root of the whole device tree (both - * of HW and pseudo devices). - */ -static int root_dev_add(ddf_dev_t *dev) -{ - ddf_msg(LVL_DEBUG, "root_dev_add, device handle=%" PRIun, - ddf_dev_get_handle(dev)); - - /* - * Register virtual devices root. - * We warn on error occurrence because virtual devices shall not be - * vital for the system. - */ - int res = add_virtual_root_fun(dev); - if (res != EOK) - ddf_msg(LVL_WARN, "Failed to add virtual child."); - - /* Register root device's children. */ - res = add_platform_fun(dev); - if (EOK != res) - ddf_msg(LVL_ERROR, "Failed adding child device for platform."); - - return res; -} - -static int root_fun_online(ddf_fun_t *fun) -{ - ddf_msg(LVL_DEBUG, "root_fun_online()"); - return ddf_fun_online(fun); -} - -static int root_fun_offline(ddf_fun_t *fun) -{ - ddf_msg(LVL_DEBUG, "root_fun_offline()"); - return ddf_fun_offline(fun); -} - -int main(int argc, char *argv[]) -{ - printf(NAME ": HelenOS root device driver\n"); - - ddf_log_init(NAME); - return ddf_driver_main(&root_driver); -} - -/** - * @} - */ - Index: uspace/drv/infrastructure/root/root.ma =================================================================== --- uspace/drv/infrastructure/root/root.ma (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ (revision ) @@ -1,1 +1,0 @@ -10 root Index: uspace/drv/infrastructure/rootamdm37x/Makefile =================================================================== --- uspace/drv/infrastructure/rootamdm37x/Makefile (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ (revision ) @@ -1,38 +1,0 @@ -# -# Copyright (c) 2012 Jan Vesely -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# - Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# - Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# - The name of the author may not be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# - -USPACE_PREFIX = ../../.. -LIBS = $(LIBDRV_PREFIX)/libdrv.a -EXTRA_CFLAGS += -I$(LIBDRV_PREFIX)/include -BINARY = rootamdm37x - -SOURCES = \ - amdm37x.c \ - rootamdm37x.c - -include $(USPACE_PREFIX)/Makefile.common Index: uspace/drv/infrastructure/rootamdm37x/amdm37x.c =================================================================== --- uspace/drv/infrastructure/rootamdm37x/amdm37x.c (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ (revision ) @@ -1,404 +1,0 @@ -/* - * Copyright (c) 2012 Jan Vesely - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** - * @defgroup root_amdm37x TI AM/DM37x platform driver. - * @brief HelenOS TI AM/DM37x platform driver. - * @{ - */ - -/** @file - */ - -#include "amdm37x.h" - -#include -#include -#include -#include -#include - -static void log(const volatile void *place, uint32_t val, volatile void* base, size_t size, void *data, bool write) -{ - printf("PIO %s: %p(%p) %#"PRIx32"\n", write ? "WRITE" : "READ", - (place - base) + data, place, val); -} - - -int amdm37x_init(amdm37x_t *device, bool trace) -{ - assert(device); - int ret = EOK; - - ret = pio_enable((void*)USBHOST_CM_BASE_ADDRESS, USBHOST_CM_SIZE, - (void**)&device->cm.usbhost); - if (ret != EOK) - return ret; - - ret = pio_enable((void*)CORE_CM_BASE_ADDRESS, CORE_CM_SIZE, - (void**)&device->cm.core); - if (ret != EOK) - return ret; - - ret = pio_enable((void*)CLOCK_CONTROL_CM_BASE_ADDRESS, - CLOCK_CONTROL_CM_SIZE, (void**)&device->cm.clocks); - if (ret != EOK) - return ret; - - ret = pio_enable((void*)MPU_CM_BASE_ADDRESS, - MPU_CM_SIZE, (void**)&device->cm.mpu); - if (ret != EOK) - return ret; - - ret = pio_enable((void*)IVA2_CM_BASE_ADDRESS, - IVA2_CM_SIZE, (void**)&device->cm.iva2); - if (ret != EOK) - return ret; - - ret = pio_enable((void*)CLOCK_CONTROL_PRM_BASE_ADDRESS, - CLOCK_CONTROL_PRM_SIZE, (void**)&device->prm.clocks); - if (ret != EOK) - return ret; - - ret = pio_enable((void*)GLOBAL_REG_PRM_BASE_ADDRESS, - GLOBAL_REG_PRM_SIZE, (void**)&device->prm.global); - if (ret != EOK) - return ret; - - ret = pio_enable((void*)AMDM37x_USBTLL_BASE_ADDRESS, - AMDM37x_USBTLL_SIZE, (void**)&device->tll); - if (ret != EOK) - return ret; - - ret = pio_enable((void*)AMDM37x_UHH_BASE_ADDRESS, - AMDM37x_UHH_SIZE, (void**)&device->uhh); - if (ret != EOK) - return ret; - - if (trace) { - pio_trace_enable(device->tll, AMDM37x_USBTLL_SIZE, log, (void*)AMDM37x_USBTLL_BASE_ADDRESS); - pio_trace_enable(device->cm.clocks, CLOCK_CONTROL_CM_SIZE, log, (void*)CLOCK_CONTROL_CM_BASE_ADDRESS); - pio_trace_enable(device->cm.core, CORE_CM_SIZE, log, (void*)CORE_CM_BASE_ADDRESS); - pio_trace_enable(device->cm.mpu, MPU_CM_SIZE, log, (void*)MPU_CM_BASE_ADDRESS); - pio_trace_enable(device->cm.iva2, IVA2_CM_SIZE, log, (void*)IVA2_CM_BASE_ADDRESS); - pio_trace_enable(device->cm.usbhost, USBHOST_CM_SIZE, log, (void*)USBHOST_CM_BASE_ADDRESS); - pio_trace_enable(device->uhh, AMDM37x_UHH_SIZE, log, (void*)AMDM37x_UHH_BASE_ADDRESS); - pio_trace_enable(device->prm.clocks, CLOCK_CONTROL_PRM_SIZE, log, (void*)CLOCK_CONTROL_PRM_BASE_ADDRESS); - pio_trace_enable(device->prm.global, GLOBAL_REG_PRM_SIZE, log, (void*)GLOBAL_REG_PRM_BASE_ADDRESS); - } - return EOK; -} - - -/** Set DPLLs 1,2,3,4,5 to ON (locked) and autoidle. - * @param device Register map. - * - * The idea is to get all DPLLs running and make hw control their power mode, - * based on the module requirements (module ICLKs and FCLKs). - */ -void amdm37x_setup_dpll_on_autoidle(amdm37x_t *device) -{ - assert(device); - /* Get SYS_CLK value, it is used as reference clock by all DPLLs, - * NFI who sets this or why it is set to specific value. */ - const unsigned osc_clk = pio_read_32(&device->prm.clocks->clksel) - & CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_MASK; - const unsigned clk_reg = pio_read_32(&device->prm.global->clksrc_ctrl); - const unsigned base_freq = sys_clk_freq_kHz(osc_clk) - / GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKDIV_GET(clk_reg); - ddf_msg(LVL_NOTE, "Base frequency: %d.%dMhz", - base_freq / 1000, base_freq % 1000); - - - /* DPLL1 provides MPU(CPU) clock. - * It uses SYS_CLK as reference clock and core clock (DPLL3) as - * high frequency bypass (MPU then runs on L3 interconnect freq). - * It should be setup by fw or u-boot.*/ - mpu_cm_regs_t *mpu = device->cm.mpu; - - /* Current MPU frequency. */ - if (pio_read_32(&mpu->clkstst) & MPU_CM_CLKSTST_CLKACTIVITY_MPU_ACTIVE_FLAG) { - if (pio_read_32(&mpu->idlest_pll) & MPU_CM_IDLEST_PLL_ST_MPU_CLK_LOCKED_FLAG) { - /* DPLL active and locked */ - const uint32_t reg = pio_read_32(&mpu->clksel1_pll); - const unsigned multiplier = - (reg & MPU_CM_CLKSEL1_PLL_MPU_DPLL_MULT_MASK) - >> MPU_CM_CLKSEL1_PLL_MPU_DPLL_MULT_SHIFT; - const unsigned divisor = - (reg & MPU_CM_CLKSEL1_PLL_MPU_DPLL_DIV_MASK) - >> MPU_CM_CLKSEL1_PLL_MPU_DPLL_DIV_SHIFT; - const unsigned divisor2 = - (pio_read_32(&mpu->clksel2_pll) - & MPU_CM_CLKSEL2_PLL_MPU_DPLL_CLKOUT_DIV_MASK); - if (multiplier && divisor && divisor2) { - /** See AMDM37x TRM p. 300 for the formula */ - const unsigned freq = - ((base_freq * multiplier) / (divisor + 1)) - / divisor2; - ddf_msg(LVL_NOTE, "MPU running at %d.%d MHz", - freq / 1000, freq % 1000); - } else { - ddf_msg(LVL_WARN, "Frequency divisor and/or " - "multiplier value invalid: %d %d %d", - multiplier, divisor, divisor2); - } - } else { - /* DPLL in LP bypass mode */ - const unsigned divisor = - MPU_CM_CLKSEL1_PLL_MPU_CLK_SRC_VAL( - pio_read_32(&mpu->clksel1_pll)); - ddf_msg(LVL_NOTE, "MPU DPLL in bypass mode, running at" - " CORE CLK / %d MHz", divisor); - } - } else { - ddf_msg(LVL_WARN, "MPU clock domain is not active, we should not be running..."); - } - // TODO: Enable this (automatic MPU downclocking): -#if 0 - /* Enable low power bypass mode, this will take effect the next lock or - * relock sequence. */ - //TODO: We might need to force re-lock after enabling this - pio_set_32(&mpu->clken_pll, MPU_CM_CLKEN_PLL_EN_MPU_DPLL_LP_MODE_FLAG, 5); - /* Enable automatic relocking */ - pio_change_32(&mpu->autoidle_pll, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_ENABLED, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_MASK, 5); -#endif - - /* DPLL2 provides IVA(video acceleration) clock. - * It uses SYS_CLK as reference clokc and core clock (DPLL3) as - * high frequency bypass (IVA runs on L3 freq). - */ - // TODO: We can probably turn this off entirely. IVA is left unused. - /* Enable low power bypass mode, this will take effect the next lock or - * relock sequence. */ - //TODO: We might need to force re-lock after enabling this - pio_set_32(&device->cm.iva2->clken_pll, MPU_CM_CLKEN_PLL_EN_MPU_DPLL_LP_MODE_FLAG, 5); - /* Enable automatic relocking */ - pio_change_32(&device->cm.iva2->autoidle_pll, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_ENABLED, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_MASK, 5); - - /* DPLL3 provides tons of clocks: - * CORE_CLK, COREX2_CLK, DSS_TV_CLK, 12M_CLK, 48M_CLK, 96M_CLK, L3_ICLK, - * and L4_ICLK. It uses SYS_CLK as reference clock and low frequency - * bypass. It should be setup by fw or u-boot as it controls critical - * interconnects. - */ - if (pio_read_32(&device->cm.clocks->idlest_ckgen) & CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_CORE_CLK_FLAG) { - /* DPLL active and locked */ - const uint32_t reg = - pio_read_32(&device->cm.clocks->clksel1_pll); - const unsigned multiplier = - CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_MULT_GET(reg); - const unsigned divisor = - CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_DIV_GET(reg); - const unsigned divisor2 = - CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_CLKOUT_DIV_GET(reg); - if (multiplier && divisor && divisor2) { - /** See AMDM37x TRM p. 300 for the formula */ - const unsigned freq = - ((base_freq * multiplier) / (divisor + 1)) / divisor2; - ddf_msg(LVL_NOTE, "CORE CLK running at %d.%d MHz", - freq / 1000, freq % 1000); - const unsigned l3_div = - pio_read_32(&device->cm.core->clksel) - & CORE_CM_CLKSEL_CLKSEL_L3_MASK; - if (l3_div == CORE_CM_CLKSEL_CLKSEL_L3_DIVIDED1 || - l3_div == CORE_CM_CLKSEL_CLKSEL_L3_DIVIDED2) { - ddf_msg(LVL_NOTE, "L3 interface at %d.%d MHz", - (freq / l3_div) / 1000, - (freq / l3_div) % 1000); - } else { - ddf_msg(LVL_WARN,"L3 interface clock divisor is" - " invalid: %d", l3_div); - } - } else { - ddf_msg(LVL_WARN, "DPLL3 frequency divisor and/or " - "multiplier value invalid: %d %d %d", - multiplier, divisor, divisor2); - } - } else { - ddf_msg(LVL_WARN, "CORE CLK in bypass mode, fruunig at SYS_CLK" - " frreq of %d.%d MHz", base_freq / 1000, base_freq % 1000); - } - - /* Set DPLL3 to automatic to save power */ - pio_change_32(&device->cm.clocks->autoidle_pll, - CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_AUTOMATIC, - CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_MASK, 5); - - /* DPLL4 provides peripheral domain clocks: - * CAM_MCLK, EMU_PER_ALWON_CLK, DSS1_ALWON_FCLK, and 96M_ALWON_FCLK. - * It uses SYS_CLK as reference clock and low frequency bypass. - * 96M clock is used by McBSP[1,5], MMC[1,2,3], I2C[1,2,3], so - * we can probably turn this off entirely (DSS is still non-functional). - */ - /* Set DPLL4 to automatic to save power */ - pio_change_32(&device->cm.clocks->autoidle_pll, - CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_AUTOMATIC, - CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_MASK, 5); - - /* DPLL5 provide peripheral domain clocks: 120M_FCLK. - * It uses SYS_CLK as reference clock and low frequency bypass. - * 120M clock is used by HS USB and USB TLL. - */ - // TODO setup DPLL5 - if ((pio_read_32(&device->cm.clocks->clken2_pll) - & CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_MASK) - != CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_LOCK) { - /* Compute divisors and multiplier - * See AMDM37x TRM p. 300 for the formula */ - // TODO: base_freq does not have to be rounded to Mhz - // (that's why I used KHz as unit). - const unsigned mult = 120; - const unsigned div = (base_freq / 1000) - 1; - const unsigned div2 = 1; - if ( ((base_freq % 1000) != 0) || (div > 127)) { - ddf_msg(LVL_ERROR, "Rounding error, or divisor to big " - "freq: %d, div: %d", base_freq, div); - return; - }; - assert(div <= 127); - - /* Set multiplier */ - pio_change_32(&device->cm.clocks->clksel4_pll, - CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT_CREATE(mult), - CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT_MASK, 10); - - /* Set DPLL divisor */ - pio_change_32(&device->cm.clocks->clksel4_pll, - CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV_CREATE(div), - CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV_MASK, 10); - - /* Set output clock divisor */ - pio_change_32(&device->cm.clocks->clksel5_pll, - CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M_CREATE(div2), - CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M_MASK, 10); - - /* Start DPLL5 */ - pio_change_32(&device->cm.clocks->clken2_pll, - CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_LOCK, - CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_MASK, 10); - - } - /* Set DPLL5 to automatic to save power */ - pio_change_32(&device->cm.clocks->autoidle2_pll, - CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_AUTOMATIC, - CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_MASK, 5); -} - -/** Enable/disable function and interface clocks for USBTLL and USBHOST. - * @param device Register map. - * @param on True to switch clocks on. - */ -void amdm37x_usb_clocks_set(amdm37x_t *device, bool enabled) -{ - if (enabled) { - /* Enable interface and function clock for USB TLL */ - pio_set_32(&device->cm.core->fclken3, - CORE_CM_FCLKEN3_EN_USBTLL_FLAG, 5); - pio_set_32(&device->cm.core->iclken3, - CORE_CM_ICLKEN3_EN_USBTLL_FLAG, 5); - - /* Enable interface and function clock for USB hosts */ - pio_set_32(&device->cm.usbhost->fclken, - USBHOST_CM_FCLKEN_EN_USBHOST1_FLAG | - USBHOST_CM_FCLKEN_EN_USBHOST2_FLAG, 5); - pio_set_32(&device->cm.usbhost->iclken, - USBHOST_CM_ICLKEN_EN_USBHOST, 5); -#if 0 - printf("DPLL5 (and everything else) should be on: %" - PRIx32" %"PRIx32".\n", - pio_read_32(&device->cm.clocks->idlest_ckgen), - pio_read_32(&device->cm.clocks->idlest2_ckgen)); -#endif - } else { - /* Disable interface and function clock for USB hosts */ - pio_clear_32(&device->cm.usbhost->iclken, - USBHOST_CM_ICLKEN_EN_USBHOST, 5); - pio_clear_32(&device->cm.usbhost->fclken, - USBHOST_CM_FCLKEN_EN_USBHOST1_FLAG | - USBHOST_CM_FCLKEN_EN_USBHOST2_FLAG, 5); - - /* Disable interface and function clock for USB TLL */ - pio_clear_32(&device->cm.core->iclken3, - CORE_CM_ICLKEN3_EN_USBTLL_FLAG, 5); - pio_clear_32(&device->cm.core->fclken3, - CORE_CM_FCLKEN3_EN_USBTLL_FLAG, 5); - } -} - -/** Initialize USB TLL port connections. - * - * Different modes are on page 3312 of the Manual Figure 22-34. - * Select mode than can operate in FS/LS. - */ -int amdm37x_usb_tll_init(amdm37x_t *device) -{ - /* Check access */ - if (pio_read_32(&device->cm.core->idlest3) & CORE_CM_IDLEST3_ST_USBTLL_FLAG) { - ddf_msg(LVL_ERROR, "USB TLL is not accessible"); - return EIO; - } - - /* Reset USB TLL */ - pio_set_32(&device->tll->sysconfig, TLL_SYSCONFIG_SOFTRESET_FLAG, 5); - ddf_msg(LVL_DEBUG2, "Waiting for USB TLL reset"); - while (!(pio_read_32(&device->tll->sysstatus) & TLL_SYSSTATUS_RESET_DONE_FLAG)); - ddf_msg(LVL_DEBUG, "USB TLL Reset done."); - - /* Setup idle mode (smart idle) */ - pio_change_32(&device->tll->sysconfig, - TLL_SYSCONFIG_CLOCKACTIVITY_FLAG | TLL_SYSCONFIG_AUTOIDLE_FLAG | - TLL_SYSCONFIG_SIDLE_MODE_SMART, TLL_SYSCONFIG_SIDLE_MODE_MASK, 5); - - /* Smart idle for UHH */ - pio_change_32(&device->uhh->sysconfig, - UHH_SYSCONFIG_CLOCKACTIVITY_FLAG | UHH_SYSCONFIG_AUTOIDLE_FLAG | - UHH_SYSCONFIG_SIDLE_MODE_SMART, UHH_SYSCONFIG_SIDLE_MODE_MASK, 5); - - /* Set all ports to go through TLL(UTMI) - * Direct connection can only work in HS mode */ - pio_set_32(&device->uhh->hostconfig, - UHH_HOSTCONFIG_P1_ULPI_BYPASS_FLAG | - UHH_HOSTCONFIG_P2_ULPI_BYPASS_FLAG | - UHH_HOSTCONFIG_P3_ULPI_BYPASS_FLAG, 5); - - /* What is this? */ - pio_set_32(&device->tll->shared_conf, TLL_SHARED_CONF_FCLK_IS_ON_FLAG, 5); - - for (unsigned i = 0; i < 3; ++i) { - /* Serial mode is the only one capable of FS/LS operation. - * Select FS/LS mode, no idea what the difference is - * one of bidirectional modes might be good choice - * 2 = 3pin bidi phy. */ - pio_change_32(&device->tll->channel_conf[i], - TLL_CHANNEL_CONF_CHANMODE_UTMI_SERIAL_MODE | - TLL_CHANNEL_CONF_FSLSMODE_3PIN_BIDI_PHY, - TLL_CHANNEL_CONF_CHANMODE_MASK | - TLL_CHANNEL_CONF_FSLSMODE_MASK, 5); - } - return EOK; -} Index: uspace/drv/infrastructure/rootamdm37x/amdm37x.h =================================================================== --- uspace/drv/infrastructure/rootamdm37x/amdm37x.h (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ (revision ) @@ -1,76 +1,0 @@ -/* - * Copyright (c) 2012 Jan Vesely - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup amdm37xdrv - * @{ - */ -/** @file - * @brief AM/DM 37x device. - */ -#ifndef AMDM37x_H -#define AMDM37x_H - -#include "uhh.h" -#include "usbtll.h" - -#include "cm/core.h" -#include "cm/clock_control.h" -#include "cm/usbhost.h" -#include "cm/mpu.h" -#include "cm/iva2.h" - -#include "prm/clock_control.h" -#include "prm/global_reg.h" - -#include - -typedef struct { - uhh_regs_t *uhh; - tll_regs_t *tll; - struct { - mpu_cm_regs_t *mpu; - iva2_cm_regs_t *iva2; - core_cm_regs_t *core; - clock_control_cm_regs_t *clocks; - usbhost_cm_regs_t *usbhost; - } cm; - struct { - clock_control_prm_regs_t *clocks; - global_reg_prm_regs_t *global; - } prm; -} amdm37x_t; - -int amdm37x_init(amdm37x_t *device, bool trace_io); -int amdm37x_usb_tll_init(amdm37x_t *device); -void amdm37x_setup_dpll_on_autoidle(amdm37x_t *device); -void amdm37x_usb_clocks_set(amdm37x_t *device, bool enabled); - -#endif -/** - * @} - */ Index: uspace/drv/infrastructure/rootamdm37x/cm/clock_control.h =================================================================== --- uspace/drv/infrastructure/rootamdm37x/cm/clock_control.h (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ (revision ) @@ -1,161 +1,0 @@ -/* - * Copyright (c) 2012 Jan Vesely - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup amdm37xdrvclockcontrolcm - * @{ - */ -/** @file - * @brief Clock Control Clock Management IO register structure. - */ -#ifndef AMDM37x_CLOCK_CONTROL_CM_H -#define AMDM37x_CLOCK_CONTROL_CM_H -#include -#include - -/* AM/DM37x TRM p.485 */ -#define CLOCK_CONTROL_CM_BASE_ADDRESS 0x48004d00 -#define CLOCK_CONTROL_CM_SIZE 8192 - -/** Clock control register map - * - * Periph DPLL == DPLL4 - * Core DPLL == DPLL3 - */ -typedef struct { - ioport32_t clken_pll; -#define CLOCK_CONTROL_CM_CLKEN_PLL_PWRDN_EMU_PERIPH_FLAG (1 << 31) -#define CLOCK_CONTROL_CM_CLKEN_PLL_PWRDN_CAM_FLAG (1 << 30) -#define CLOCK_CONTROL_CM_CLKEN_PLL_PWRDN_DSS1_FLAG (1 << 29) -#define CLOCK_CONTROL_CM_CLKEN_PLL_PWRDN_TV_FLAG (1 << 28) -#define CLOCK_CONTROL_CM_CLKEN_PLL_PWRDN_96M_FLAG (1 << 27) -#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH_DPLL_DRIFTGUARD_FLAG (1 << 19) -#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH_DPLL_MASK (0x7 << 16) -#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH_DPLL_LP_STOP (0x1 << 16) -#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH_DPLL_LOCK (0x7 << 16) -#define CLOCK_CONTROL_CM_CLKEN_PLL_PWRDN_EMU_CORE_FLAG (1 << 12) -#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_CORE_DPLL_LPMODE_FLAG (1 << 10) -#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_CORE_DPLL_DRIFTGUARD_FLAG (1 << 3) -#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_CORE_DPLL_MASK (0x7) -#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_CORE_DPLL_LP_BYPASS (0x5) -#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_CORE_DPLL_FAST_RELOCK (0x6) -#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_CORE_DPLL_LOCK (0x7) - - ioport32_t clken2_pll; -#define CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_LPMODE_FLAG (1 << 10) -#define CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_DRIFTGUARD_FLAG (1 << 3) -#define CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_MASK (0x7) -#define CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_LP_STOP (0x1) -#define CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_LOCK (0x7) - - PADD32[6]; - - const ioport32_t idlest_ckgen; -#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_EMU_PERIPH_CLK_FLAG (1 << 13) -#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_CAM_CLK_FLAG (1 << 12) -#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_DSS1_CLK_FLAG (1 << 11) -#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_TV_CLK_FLAG (1 << 10) -#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_FUNC96M_CLK_FLAG (1 << 9) -#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_EMU_CORE_CLK_FLAG (1 << 8) -#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_54M_CLK_FLAG (1 << 5) -#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_12M_CLK_FLAG (1 << 4) -#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_48M_CLK_FLAG (1 << 3) -#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_96M_CLK_FLAG (1 << 2) -#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_PERIPH_CLK_FLAG (1 << 1) -#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_CORE_CLK_FLAG (1 << 0) - - const ioport32_t idlest2_ckgen; -#define CLOCK_CONTROL_CM_IDLEST2_CKGEN_ST_FUNC120M_CLK_FLAG (1 << 3) -#define CLOCK_CONTROL_CM_IDLEST2_CKGEN_ST_120M_CLK_FLAG (1 << 1) -#define CLOCK_CONTROL_CM_IDLEST2_CKGEN_ST_PERIPH2_CLK_FLAG (1 << 0) - - PADD32[2]; - - ioport32_t autoidle_pll; -#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_MASK (0x7 << 3) -#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_DISABLED (0x0 << 3) -#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_AUTOMATIC (0x1 << 3) -#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_MASK (0x7) -#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_DISABLED (0x0) -#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_AUTOMATIC (0x1) -#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_AUTOMATIC_BYPASS (0x5) - - ioport32_t autoidle2_pll; -#define CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_MASK (0x7) -#define CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_DISABLED (0x0) -#define CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_AUTOMATIC (0x1) - - PADD32[2]; - - ioport32_t clksel1_pll; -#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27) -#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_CLKOUT_DIV_CREATE(x) (((x) & 0x1f) << 27) -#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_CLKOUT_DIV_GET(x) (((x) >> 27) & 0x1f) -#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_MULT_MASK (0x7ff << 16) -#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_MULT_CREATE(x) (((x) & 0x7ff) << 16) -#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_MULT_GET(x) (((x) >> 16) & 0x7ff) -#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_DIV_MASK (0x7f << 8) -#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_DIV_CREATE(x) (((x) & 0x7f) << 8) -#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_DIV_GET(x) (((x) >> 8) & 0x7f) -#define CLOCK_CONTROL_CM_CLKSEL1_PLL_SOURCE_96M_FLAG (1 << 6) -#define CLOCK_CONTROL_CM_CLKSEL1_PLL_SOURCE_54M_FLAG (1 << 5) -#define CLOCK_CONTROL_CM_CLKSEL1_PLL_SOURCE_48M_FLAG (1 << 3) - - ioport32_t clksel2_pll; -#define CLOCK_CONTROL_CM_CLKSEL2_PLL_SD_DIV_MASK (0xff << 24) -#define CLOCK_CONTROL_CM_CLKSEL2_PLL_SD_DIV_(x) (((x) & 0xff) << 24) -#define CLOCK_CONTROL_CM_CLKSEL2_PLL_DCO_SEL_MASK (0x7 << 21) -#define CLOCK_CONTROL_CM_CLKSEL2_PLL_DCO_SEL_500 (0x2 << 21) -#define CLOCK_CONTROL_CM_CLKSEL2_PLL_DCO_SEL_1000 (0x4 << 21) -#define CLOCK_CONTROL_CM_CLKSEL2_PLL_PERIPH_DPLL_MULT_MASK (0xfff << 8) -#define CLOCK_CONTROL_CM_CLKSEL2_PLL_PERIPH_DPLL_MULT(x) (((x) & 0xfff) << 8) -#define CLOCK_CONTROL_CM_CLKSEL2_PLL_PERIPH_DPLL_DIV_MASK (0x7f) -#define CLOCK_CONTROL_CM_CLKSEL2_PLL_PERIPH_DPLL_DIV(x) ((x) & 0x7f) - - ioport32_t clksel3_pll; -#define CLOCK_CONTROL_CM_CLKSEL3_PLL_DIV_96M_MASK (0xf) -#define CLOCK_CONTROL_CM_CLKSEL3_PLL_DIV_96M(x) ((x) & 0xf) - - ioport32_t clksel4_pll; -#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT_MASK (0x7ff << 8) -#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT_CREATE(x) (((x) & 0x7ff) << 8) -#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT_GET(x) (((x) >> 8) & 0x7ff) -#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV_MASK (0x7f) -#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV_CREATE(x) ((x) & 0x7f) -#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV_GET(x) ((x) & 0x7f) - - ioport32_t clksel5_pll; -#define CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M_MASK (0x1f) -#define CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M_CREATE(x) ((x) & 0x1f) -#define CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M_GET(x) ((x) & 0x1f) -} clock_control_cm_regs_t; - -#endif -/** - * @} - */ - Index: uspace/drv/infrastructure/rootamdm37x/cm/core.h =================================================================== --- uspace/drv/infrastructure/rootamdm37x/cm/core.h (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ (revision ) @@ -1,188 +1,0 @@ -/* - * Copyright (c) 2012 Jan Vesely - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup amdm37xdrvcorecm - * @{ - */ -/** @file - * @brief CORE Clock Management IO register structure. - */ -#ifndef AMDM37x_CORE_CM_H -#define AMDM37x_CORE_CM_H -#include -#include - -/* AM/DM37x TRM p.447 */ -#define CORE_CM_BASE_ADDRESS 0x48004a00 -#define CORE_CM_SIZE 8192 - -typedef struct { - ioport32_t fclken1; -#define CORE_CM_FCLKEN1_EN_MCBSP1_FLAG (1 << 9) -#define CORE_CM_FCLKEN1_EN_MCBSP5_FLAG (1 << 10) -#define CORE_CM_FCLKEN1_EN_GPT10_FLAG (1 << 11) -#define CORE_CM_FCLKEN1_EN_GPT11_FLAG (1 << 12) -#define CORE_CM_FCLKEN1_EN_UART1_FLAG (1 << 13) -#define CORE_CM_FCLKEN1_EN_UART2_FLAG (1 << 14) -#define CORE_CM_FCLKEN1_EN_I2C1_FLAG (1 << 15) -#define CORE_CM_FCLKEN1_EN_I2C2_FLAG (1 << 16) -#define CORE_CM_FCLKEN1_EN_I2C3_FLAG (1 << 17) -#define CORE_CM_FCLKEN1_EN_MCSPI1_FLAG (1 << 18) -#define CORE_CM_FCLKEN1_EN_MCSPI2_FLAG (1 << 19) -#define CORE_CM_FCLKEN1_EN_MCSPI3_FLAG (1 << 20) -#define CORE_CM_FCLKEN1_EN_MCSPI4_FLAG (1 << 21) -#define CORE_CM_FCLKEN1_EN_HDQ_FLAG (1 << 22) -#define CORE_CM_FCLKEN1_EN_MMC1_FLAG (1 << 24) -#define CORE_CM_FCLKEN1_EN_MMC2_FLAG (1 << 25) -#define CORE_CM_FCLKEN1_EN_MMC3_FLAG (1 << 30) - - PADD32; - ioport32_t fclken3; -#define CORE_CM_FCLKEN3_EN_TS_FLAG (1 << 1) -#define CORE_CM_FCLKEN3_EN_USBTLL_FLAG (1 << 2) - - PADD32; - ioport32_t iclken1; -#define CORE_CM_ICLKEN1_EN_SDRC_FLAG (1 << 1) -#define CORE_CM_ICLKEN1_EN_HSOTGUSB_FLAG (1 << 4) -#define CORE_CM_ICLKEN1_EN_SCMCTRL_FLAG (1 << 6) -#define CORE_CM_ICLKEN1_EN_MAILBOXES_FLAG (1 << 7) -#define CORE_CM_ICLKEN1_EN_MCBSP1_FLAG (1 << 9) -#define CORE_CM_ICLKEN1_EN_MCBSP5_FLAG (1 << 10) -#define CORE_CM_ICLKEN1_EN_GPT10_FLAG (1 << 11) -#define CORE_CM_ICLKEN1_EN_GPT11_FLAG (1 << 12) -#define CORE_CM_ICLKEN1_EN_UART1_FLAG (1 << 13) -#define CORE_CM_ICLKEN1_EN_UART2_FLAG (1 << 14) -#define CORE_CM_ICLKEN1_EN_I2C1_FLAG (1 << 15) -#define CORE_CM_ICLKEN1_EN_I2C2_FLAG (1 << 16) -#define CORE_CM_ICLKEN1_EN_I2C3_FLAG (1 << 17) -#define CORE_CM_ICLKEN1_EN_MCSPI1_FLAG (1 << 18) -#define CORE_CM_ICLKEN1_EN_MCSPI2_FLAG (1 << 19) -#define CORE_CM_ICLKEN1_EN_MCSPI3_FLAG (1 << 20) -#define CORE_CM_ICLKEN1_EN_MCSPI4_FLAG (1 << 21) -#define CORE_CM_ICLKEN1_EN_HDQ_FLAG (1 << 22) -#define CORE_CM_ICLKEN1_EN_MMC1_FLAG (1 << 24) -#define CORE_CM_ICLKEN1_EN_MMC2_FLAG (1 << 25) -#define CORE_CM_ICLKEN1_EN_ICR_FLAG (1 << 29) -#define CORE_CM_ICLKEN1_EN_MMC3_FLAG (1 << 30) - - ioport32_t reserved1; - ioport32_t iclken3; -#define CORE_CM_ICLKEN3_EN_USBTLL_FLAG (1 << 2) - - PADD32; - const ioport32_t idlest1; -#define CORE_CM_IDLEST1_ST_SDRC_FLAG (1 << 1) -#define CORE_CM_IDLEST1_ST_SDMA_FLAG (1 << 2) -#define CORE_CM_IDLEST1_ST_HSOTGUSB_STBY_FLAG (1 << 4) -#define CORE_CM_IDLEST1_ST_HSOTGUSB_IDLE_FLAG (1 << 5) -#define CORE_CM_IDLEST1_ST_SCMCTRL_FLAG (1 << 6) -#define CORE_CM_IDLEST1_ST_MAILBOXES_FLAG (1 << 7) -#define CORE_CM_IDLEST1_ST_MCBSP1_FLAG (1 << 9) -#define CORE_CM_IDLEST1_ST_MCBSP5_FLAG (1 << 10) -#define CORE_CM_IDLEST1_ST_GPT10_FLAG (1 << 11) -#define CORE_CM_IDLEST1_ST_GPT11_FLAG (1 << 12) -#define CORE_CM_IDLEST1_ST_UART1_FLAG (1 << 13) -#define CORE_CM_IDLEST1_ST_UART2_FLAG (1 << 14) -#define CORE_CM_IDLEST1_ST_I2C1_FLAG (1 << 15) -#define CORE_CM_IDLEST1_ST_I2C2_FLAG (1 << 16) -#define CORE_CM_IDLEST1_ST_I2C3_FLAG (1 << 17) -#define CORE_CM_IDLEST1_ST_MCSPI1_FLAG (1 << 18) -#define CORE_CM_IDLEST1_ST_MCSPI2_FLAG (1 << 19) -#define CORE_CM_IDLEST1_ST_MCSPI3_FLAG (1 << 20) -#define CORE_CM_IDLEST1_ST_MCSPI4_FLAG (1 << 21) -#define CORE_CM_IDLEST1_ST_HDQ_FLAG (1 << 22) -#define CORE_CM_IDLEST1_ST_MMC1_FLAG (1 << 24) -#define CORE_CM_IDLEST1_ST_MMC2_FLAG (1 << 25) -#define CORE_CM_IDLEST1_ST_ICR_FLAG (1 << 29) -#define CORE_CM_IDLEST1_ST_MMC3_FLAG (1 << 30) - - const ioport32_t reserved2; - const ioport32_t idlest3; -#define CORE_CM_IDLEST3_ST_USBTLL_FLAG (1 << 2) - - PADD32; - ioport32_t autoidle1; -#define CORE_CM_AUTOIDLE1_AUTO_HSOTGUSB_FLAG (1 << 4) -#define CORE_CM_AUTOIDLE1_AUTO_SCMCTRL_FLAG (1 << 6) -#define CORE_CM_AUTOIDLE1_AUTO_MAILBOXES_FLAG (1 << 7) -#define CORE_CM_AUTOIDLE1_AUTO_MCBSP1_FLAG (1 << 9) -#define CORE_CM_AUTOIDLE1_AUTO_MCBSP5_FLAG (1 << 10) -#define CORE_CM_AUTOIDLE1_AUTO_GPT10_FLAG (1 << 11) -#define CORE_CM_AUTOIDLE1_AUTO_GPT11_FLAG (1 << 12) -#define CORE_CM_AUTOIDLE1_AUTO_UART1_FLAG (1 << 13) -#define CORE_CM_AUTOIDLE1_AUTO_UART2_FLAG (1 << 14) -#define CORE_CM_AUTOIDLE1_AUTO_I2C1_FLAG (1 << 15) -#define CORE_CM_AUTOIDLE1_AUTO_I2C2_FLAG (1 << 16) -#define CORE_CM_AUTOIDLE1_AUTO_I2C3_FLAG (1 << 17) -#define CORE_CM_AUTOIDLE1_AUTO_MCSPI1_FLAG (1 << 18) -#define CORE_CM_AUTOIDLE1_AUTO_MCSPI2_FLAG (1 << 19) -#define CORE_CM_AUTOIDLE1_AUTO_MCSPI3_FLAG (1 << 20) -#define CORE_CM_AUTOIDLE1_AUTO_MCSPI4_FLAG (1 << 21) -#define CORE_CM_AUTOIDLE1_AUTO_HDQ_FLAG (1 << 22) -#define CORE_CM_AUTOIDLE1_AUTO_MMC1_FLAG (1 << 24) -#define CORE_CM_AUTOIDLE1_AUTO_MMC2_FLAG (1 << 25) -#define CORE_CM_AUTOIDLE1_AUTO_ICR_FLAG (1 << 29) -#define CORE_CM_AUTOIDLE1_AUTO_MMC3_FLAG (1 << 30) - - ioport32_t reserved3; - ioport32_t autoidle3; -#define CORE_CM_AUTOIDLE3_AUTO_USBTLL_FLAG (1 << 2) - - PADD32; - ioport32_t clksel; -#define CORE_CM_CLKSEL_CLKSEL_L3_MASK (0x3 << 0) -#define CORE_CM_CLKSEL_CLKSEL_L3_DIVIDED1 (0x1 << 0) -#define CORE_CM_CLKSEL_CLKSEL_L3_DIVIDED2 (0x2 << 0) -#define CORE_CM_CLKSEL_CLKSEL_L4_MASK (0x3 << 2) -#define CORE_CM_CLKSEL_CLKSEL_L4_DIVIDED1 (0x1 << 2) -#define CORE_CM_CLKSEL_CLKSEL_L4_DIVIDED2 (0x2 << 2) -#define CORE_CM_CLKSEL_CLKSEL_96M_MASK (0x3 << 12) -#define CORE_CM_CLKSEL_CLKSEL_96M_DIVIDED1 (0x1 << 12) -#define CORE_CM_CLKSEL_CLKSEL_96M_DIVIDED2 (0x2 << 12) -#define CORE_CM_CLKSEL_CLKSEL_GPT10_FLAG (1 << 6) -#define CORE_CM_CLKSEL_CLKSEL_GPT11_FLAG (1 << 7) - - PADD32; - ioport32_t clkstctrl; -#define CORE_CM_CLKCTRL_CLKCTRL_L3_MASK (0x3 << 0) -#define CORE_CM_CLKCTRL_CLKCTRL_L3_AUTO_EN (0x0 << 0) -#define CORE_CM_CLKCTRL_CLKCTRL_L3_AUTO_DIS (0x3 << 0) -#define CORE_CM_CLKCTRL_CLKCTRL_L4_MASK (0x3 << 2) -#define CORE_CM_CLKCTRL_CLKCTRL_L4_AUTO_EN (0x0 << 2) -#define CORE_CM_CLKCTRL_CLKCTRL_L4_AUTO_DIS (0x3 << 2) - - const ioport32_t clkstst; -#define CORE_CM_CLKSTST_CLKACTIVITY_L3_FLAG (1 << 0) -#define CORE_CM_CLKSTST_CLKACTIVITY_L4_FLAG (1 << 1) -} core_cm_regs_t; - -#endif -/** - * @} - */ Index: uspace/drv/infrastructure/rootamdm37x/cm/iva2.h =================================================================== --- uspace/drv/infrastructure/rootamdm37x/cm/iva2.h (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ (revision ) @@ -1,101 +1,0 @@ -/* - * Copyright (c) 2012 Jan Vesely - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup amdm37xdrvcm - * @{ - */ -/** @file - * @brief MPU Clock Management IO register structure. - */ -#ifndef AMDM37x_IVA2_CM_H -#define AMDM37x_IVA2_CM_H -#include -#include - -/* AM/DM37x TRM p.446 */ -#define IVA2_CM_BASE_ADDRESS 0x48004000 -#define IVA2_CM_SIZE 8192 - -typedef struct { - ioport32_t fclken; -#define IVA2_CM_FCLKEN_EN_IVA2_FLAG (1 << 0) - - ioport32_t clken_pll; -#define IVA2_CM_CLKEN_PLL_EN_IVA2_DPLL_LP_MODE_FLAG (1 << 10) -#define IVA2_CM_CLKEN_PLL_EN_IVA2_DPLL_DRIFTGUARD (1 << 3) -#define IVA2_CM_CLKEN_PLL_EN_IVA2_DPLL_EN_IVA2_DPLL_MASK (0x7) -#define IVA2_CM_CLKEN_PLL_EN_IVA2_DPLL_EN_IVA2_DPLL_LP_STOP (0x1) -#define IVA2_CM_CLKEN_PLL_EN_IVA2_DPLL_EN_IVA2_DPLL_LP_BYPASS (0x5) -#define IVA2_CM_CLKEN_PLL_EN_IVA2_DPLL_EN_IVA2_DPLL_LOCKED (0x7) - - PADD32[6]; - const ioport32_t idlest; -#define IVA2_CM_IDLEST_ST_IVA2_STANDBY_FLAG (1 << 0) - - const ioport32_t idlest_pll; -#define IVA2_CM_IDLEST_PLL_ST_IVA2_CLK_LOCKED_FLAG (1 << 0) - - PADD32[3]; - ioport32_t autoidle_pll; -#define IVA2_CM_AUTOIDLE_PLL_AUTO_IVA2_DPLL_MASK (0x7) -#define IVA2_CM_AUTOIDLE_PLL_AUTO_IVA2_DPLL_DISABLED (0x0) -#define IVA2_CM_AUTOIDLE_PLL_AUTO_IVA2_DPLL_ENABLED (0x1) - - PADD32[2]; - ioport32_t clksel1_pll; -#define IVA2_CM_CLKSEL1_PLL_IVA2_CLK_SRC_MASK (0x7 << 19) -#define IVA2_CM_CLKSEL1_PLL_IVA2_CLK_SRC_SHIFT (19) -#define IVA2_CM_CLKSEL1_PLL_IVA2_CLK_SRC_VAL(x) ((x >> 19) & 0x7) -#define IVA2_CM_CLKSEL1_PLL_IVA2_CLK_SRC_CORE_DIV_1 (0x1 << 19) -#define IVA2_CM_CLKSEL1_PLL_IVA2_CLK_SRC_CORE_DIV_2 (0x2 << 19) -#define IVA2_CM_CLKSEL1_PLL_IVA2_CLK_SRC_CORE_DIV_4 (0x4 << 19) -#define IVA2_CM_CLKSEL1_PLL_IVA2_DPLL_MULT_MASK (0x7ff << 8) -#define IVA2_CM_CLKSEL1_PLL_IVA2_DPLL_MULT_SHIFT (8) -#define IVA2_CM_CLKSEL1_PLL_IVA2_DPLL_DIV_MASK (0x7f << 0) -#define IVA2_CM_CLKSEL1_PLL_IVA2_DPLL_DIV_SHIFT (0) - - ioport32_t clksel2_pll; -#define IVA2_CM_CLKSEL2_PLL_IVA2_DPLL_CLKOUT_DIV_MASK (0x1f) - - ioport32_t clkstctrl; -#define IVA2_CM_CLKSCTRL_CLKTRCTRL_IVA2_MASK (0x3) -#define IVA2_CM_CLKSCTRL_CLKTRCTRL_IVA2_DISABLED (0x0) -#define IVA2_CM_CLKSCTRL_CLKTRCTRL_IVA2_START_SLEEP (0x2) -#define IVA2_CM_CLKSCTRL_CLKTRCTRL_IVA2_START_WAKEUP (0x2) -#define IVA2_CM_CLKSCTRL_CLKTRCTRL_IVA2_AUTOMATIC (0x3) - - const ioport32_t clkstst; -#define IVA2_CM_CLKSTST_CLKACTIVITY_IVA2_ACTIVE_FLAG (1 << 0) - -} iva2_cm_regs_t; - -#endif -/** - * @} - */ - Index: uspace/drv/infrastructure/rootamdm37x/cm/mpu.h =================================================================== --- uspace/drv/infrastructure/rootamdm37x/cm/mpu.h (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ (revision ) @@ -1,97 +1,0 @@ -/* - * Copyright (c) 2012 Jan Vesely - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup amdm37xdrvcm - * @{ - */ -/** @file - * @brief MPU Clock Management IO register structure. - */ -#ifndef AMDM37x_MPU_CM_H -#define AMDM37x_MPU_CM_H -#include -#include - -/* AM/DM37x TRM p.455 */ -#define MPU_CM_BASE_ADDRESS 0x48004900 -#define MPU_CM_SIZE 8192 - -typedef struct { - PADD32; - ioport32_t clken_pll; -#define MPU_CM_CLKEN_PLL_EN_MPU_DPLL_LP_MODE_FLAG (1 << 10) -#define MPU_CM_CLKEN_PLL_EN_MPU_DPLL_DRIFTGUARD (1 << 3) -#define MPU_CM_CLKEN_PLL_EN_MPU_DPLL_EN_MPU_DPLL_MASK (0x7) -#define MPU_CM_CLKEN_PLL_EN_MPU_DPLL_EN_MPU_DPLL_LP_BYPASS (0x5) -#define MPU_CM_CLKEN_PLL_EN_MPU_DPLL_EN_MPU_DPLL_LOCKED (0x7) - - PADD32[6]; - const ioport32_t idlest; -#define MPU_CM_IDLEST_ST_MPU_STANDBY_FLAG (1 << 0) - - const ioport32_t idlest_pll; -#define MPU_CM_IDLEST_PLL_ST_MPU_CLK_LOCKED_FLAG (1 << 0) - - PADD32[3]; - ioport32_t autoidle_pll; -#define MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_MASK (0x7) -#define MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_DISABLED (0x0) -#define MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_ENABLED (0x1) - - PADD32[2]; - ioport32_t clksel1_pll; -#define MPU_CM_CLKSEL1_PLL_MPU_CLK_SRC_MASK (0x7 << 19) -#define MPU_CM_CLKSEL1_PLL_MPU_CLK_SRC_SHIFT (19) -#define MPU_CM_CLKSEL1_PLL_MPU_CLK_SRC_VAL(x) ((x >> 19) & 0x7) -#define MPU_CM_CLKSEL1_PLL_MPU_CLK_SRC_CORE_DIV_1 (0x1 << 19) -#define MPU_CM_CLKSEL1_PLL_MPU_CLK_SRC_CORE_DIV_2 (0x2 << 19) -#define MPU_CM_CLKSEL1_PLL_MPU_CLK_SRC_CORE_DIV_4 (0x4 << 19) -#define MPU_CM_CLKSEL1_PLL_MPU_DPLL_MULT_MASK (0x7ff << 8) -#define MPU_CM_CLKSEL1_PLL_MPU_DPLL_MULT_SHIFT (8) -#define MPU_CM_CLKSEL1_PLL_MPU_DPLL_DIV_MASK (0x7f << 0) -#define MPU_CM_CLKSEL1_PLL_MPU_DPLL_DIV_SHIFT (0) - - ioport32_t clksel2_pll; -#define MPU_CM_CLKSEL2_PLL_MPU_DPLL_CLKOUT_DIV_MASK (0x1f) - - ioport32_t clkstctrl; -#define MPU_CM_CLKSCTRL_CLKTRCTRL_MPU_MASK (0x3) -#define MPU_CM_CLKSCTRL_CLKTRCTRL_MPU_DISABLED (0x0) -#define MPU_CM_CLKSCTRL_CLKTRCTRL_MPU_START_WAKEUP (0x2) -#define MPU_CM_CLKSCTRL_CLKTRCTRL_MPU_AUTOMATIC (0x3) - - const ioport32_t clkstst; -#define MPU_CM_CLKSTST_CLKACTIVITY_MPU_ACTIVE_FLAG (1 << 0) - -} mpu_cm_regs_t; - -#endif -/** - * @} - */ - Index: uspace/drv/infrastructure/rootamdm37x/cm/usbhost.h =================================================================== --- uspace/drv/infrastructure/rootamdm37x/cm/usbhost.h (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ (revision ) @@ -1,82 +1,0 @@ -/* - * Copyright (c) 2012 Jan Vesely - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup amdm37xdrvusbhostcm - * @{ - */ -/** @file - * @brief USBHOST Clock Management IO register structure. - */ -#ifndef AMDM37x_USBHOST_CM_H -#define AMDM37x_USBHOST_CM_H -#include -#include - -/* AM/DM37x TRM p.447 */ -#define USBHOST_CM_BASE_ADDRESS 0x48005400 -#define USBHOST_CM_SIZE 8192 - -typedef struct { - ioport32_t fclken; -#define USBHOST_CM_FCLKEN_EN_USBHOST1_FLAG (1 << 0) -#define USBHOST_CM_FCLKEN_EN_USBHOST2_FLAG (1 << 1) - - PADD32[3]; - ioport32_t iclken; -#define USBHOST_CM_ICLKEN_EN_USBHOST (1 << 0) - - PADD32[3]; - const ioport32_t idlest; -#define USBHOST_CM_IDLEST_ST_USBHOST_STDBY_FLAG (1 << 0) -#define USBHOST_CM_IDLEST_ST_USBHOST_IDLE_FLAG (1 << 1) - - PADD32[3]; - ioport32_t autoidle; -#define USBHOST_CM_AUTOIDLE_AUTO_USBHOST_FLAG (1 << 0) - - PADD32[4]; - ioport32_t sleepdep; -#define USBHOST_CM_SLEEPDEP_EN_MPU_FLAG (1 << 1) -#define USBHOST_CM_SLEEPDEP_EN_IVA2_FLAG (1 << 2) - - ioport32_t clkstctrl; -#define USBHOST_CM_CLKSTCTRL_CLKSTCTRL_USBHOST_MASK (0x3 << 0) -#define USBHOST_CM_CLKSTCTRL_CLKSTCTRL_USBHOST_AUTO_DIS (0x0 << 0) -#define USBHOST_CM_CLKSTCTRL_CLKSTCTRL_USBHOST_SUPERVISED_SLEEP (0x1 << 0) -#define USBHOST_CM_CLKSTCTRL_CLKSTCTRL_USBHOST_SUPERVISED_WAKEUP (0x2 << 0) -#define USBHOST_CM_CLKSTCTRL_CLKSTCTRL_USBHOST_AUTO_EN (0x3 << 0) - - ioport32_t clkstst; -#define USBHOST_CM_CLKSTCTRL_CLKSTST_CLKACTIVITY_USBHOST (1 << 0) -} usbhost_cm_regs_t; - -#endif -/** - * @} - */ - Index: uspace/drv/infrastructure/rootamdm37x/prm/clock_control.h =================================================================== --- uspace/drv/infrastructure/rootamdm37x/prm/clock_control.h (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ (revision ) @@ -1,81 +1,0 @@ -/* - * Copyright (c) 2012 Jan Vesely - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup amdm37xdrvprm - * @{ - */ -/** @file - * @brief Clock Control Clock Management IO register structure. - */ -#ifndef AMDM37X_PRM_CLOCK_CONTROL_H -#define AMDM37X_PRM_CLOCK_CONTROL_H -#include -#include - -/* AM/DM37x TRM p.536 and p.589 */ -#define CLOCK_CONTROL_PRM_BASE_ADDRESS 0x48306d00 -#define CLOCK_CONTROL_PRM_SIZE 8192 - -/** Clock control PRM register map - */ -typedef struct { - PADD32[16]; - ioport32_t clksel; -#define CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_MASK (0x7) -#define CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_12M (0x0) -#define CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_13M (0x1) -#define CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_19_2M (0x2) -#define CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_26M (0x3) -#define CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_38_4M (0x4) -#define CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_16_8M (0x5) - - PADD32[12]; - ioport32_t clkout_ctrl; -#define CLOCK_CONTROL_PRM_CLKOUT_CTRL_CLKOUOUT_EN_FLAG (1 << 7) - -} clock_control_prm_regs_t; - -static inline unsigned sys_clk_freq_kHz(unsigned reg_val) -{ - switch(reg_val) - { - case CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_12M: return 12000; - case CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_13M: return 13000; - case CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_19_2M: return 19200; - case CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_26M: return 26000; - case CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_38_4M: return 38400; - case CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_16_8M: return 16800; - } - return 0; -} - - -#endif -/** - * @} - */ Index: uspace/drv/infrastructure/rootamdm37x/prm/global_reg.h =================================================================== --- uspace/drv/infrastructure/rootamdm37x/prm/global_reg.h (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ (revision ) @@ -1,300 +1,0 @@ -/* - * Copyright (c) 2012 Jan Vesely - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup amdm37xdrvprm - * @{ - */ -/** @file - * @brief Clock Control Clock Management IO register structure. - */ -#ifndef AMDM37X_PRM_GLOBAL_REG_H -#define AMDM37X_PRM_GLOBAL_REG_H -#include -#include - -/* AM/DM37x TRM p.536 and p.615 */ -#define GLOBAL_REG_PRM_BASE_ADDRESS 0x48307200 -#define GLOBAL_REG_PRM_SIZE 65536 - -/** Global Reg PRM register map - */ -typedef struct { - PADD32[8]; - struct { - ioport32_t smps_sa; -#define GLOBAL_REG_PRM_VC_SMPS_SA_SA0_MASK (0x7f << 0) -#define GLOBAL_REG_PRM_VC_SMPS_SA_SA0_CREATE(x) (((x) & 0x7f) << 0) -#define GLOBAL_REG_PRM_VC_SMPS_SA_SA0_GET(r) (r & 0x7f) -#define GLOBAL_REG_PRM_VC_SMPS_SA_SA1_MASK (0x7f << 16) -#define GLOBAL_REG_PRM_VC_SMPS_SA_SA1_CREATE(x) (((x) & 0x7f) << 16) -#define GLOBAL_REG_PRM_VC_SMPS_SA_SA1_GET(r) (((r) >> 16 ) & 0x7f) - - ioport32_t smps_vol_ra; -#define GLOBAL_REG_PRM_VC_SMPS_VOL_RA_VOLRA0_MASK (0xff << 0) -#define GLOBAL_REG_PRM_VC_SMPS_VOL_RA_VOLRA0_CREATE(x) (((x) & 0xff) << 0) -#define GLOBAL_REG_PRM_VC_SMPS_VOL_RA_VOLRA0_GET(r) (r & 0xff) -#define GLOBAL_REG_PRM_VC_SMPS_VOL_RA_VOLRA1_MASK (0xff << 16) -#define GLOBAL_REG_PRM_VC_SMPS_VOL_RA_VOLRA1_CREATE(x) (((x) & 0xff) << 16) -#define GLOBAL_REG_PRM_VC_SMPS_VOL_RA_VOLRA1_GET(r) (((r) >> 16 ) & 0xff) - - ioport32_t smps_cmd_ra; -#define GLOBAL_REG_PRM_VC_SMPS_CMD_RA_CMDRA0_MASK (0xff << 0) -#define GLOBAL_REG_PRM_VC_SMPS_CMD_RA_CMDRA0_CREATE(x) (((x) & 0xff) << 0) -#define GLOBAL_REG_PRM_VC_SMPS_CMD_RA_CMDRA0_GET(r) (r & 0xff) -#define GLOBAL_REG_PRM_VC_SMPS_CMD_RA_CMDRA1_MASK (0xff << 16) -#define GLOBAL_REG_PRM_VC_SMPS_CMD_RA_CMDRA1_CREATE(x) (((x) & 0xff) << 16) -#define GLOBAL_REG_PRM_VC_SMPS_CMD_RA_CMDRA1_GET(r) (((r) >> 16 ) & 0xff) - - ioport32_t cmd_val_0; -#define GLOBAL_REG_PRM_VC_CMD_VAL_0_ON_MASK (0xff << 24) -#define GLOBAL_REG_PRM_VC_CMD_VAL_0_ON_CREATE(x) (((x) & 0xff) << 24) -#define GLOBAL_REG_PRM_VC_CMD_VAL_0_ON_GET(r) (((x) >> 24) & 0xff) -#define GLOBAL_REG_PRM_VC_CMD_VAL_0_ONLP_MASK (0xff << 24) -#define GLOBAL_REG_PRM_VC_CMD_VAL_0_ONLP_CREATE(x) (((x) & 0xff) << 24) -#define GLOBAL_REG_PRM_VC_CMD_VAL_0_ONLP_GET(r) (((x) >> 24) & 0xff) -#define GLOBAL_REG_PRM_VC_CMD_VAL_0_RET_MASK (0xff << 24) -#define GLOBAL_REG_PRM_VC_CMD_VAL_0_RET_CREATE(x) (((x) & 0xff) << 24) -#define GLOBAL_REG_PRM_VC_CMD_VAL_0_RET_GET(r) (((x) >> 24) & 0xff) -#define GLOBAL_REG_PRM_VC_CMD_VAL_0_OFF_MASK (0xff << 24) -#define GLOBAL_REG_PRM_VC_CMD_VAL_0_OFF_CREATE(x) (((x) & 0xff) << 24) -#define GLOBAL_REG_PRM_VC_CMD_VAL_0_OFF_GET(r) (((x) >> 24) & 0xff) - - ioport32_t cmd_val_1; -#define GLOBAL_REG_PRM_VC_CMD_VAL_1_ON_MASK (0xff << 24) -#define GLOBAL_REG_PRM_VC_CMD_VAL_1_ON_CREATE(x) (((x) & 0xff) << 24) -#define GLOBAL_REG_PRM_VC_CMD_VAL_1_ON_GET(r) (((x) >> 24) & 0xff) -#define GLOBAL_REG_PRM_VC_CMD_VAL_1_ONLP_MASK (0xff << 24) -#define GLOBAL_REG_PRM_VC_CMD_VAL_1_ONLP_CREATE(x) (((x) & 0xff) << 24) -#define GLOBAL_REG_PRM_VC_CMD_VAL_1_ONLP_GET(r) (((x) >> 24) & 0xff) -#define GLOBAL_REG_PRM_VC_CMD_VAL_1_RET_MASK (0xff << 24) -#define GLOBAL_REG_PRM_VC_CMD_VAL_1_RET_CREATE(x) (((x) & 0xff) << 24) -#define GLOBAL_REG_PRM_VC_CMD_VAL_1_RET_GET(r) (((x) >> 24) & 0xff) -#define GLOBAL_REG_PRM_VC_CMD_VAL_1_OFF_MASK (0xff << 24) -#define GLOBAL_REG_PRM_VC_CMD_VAL_1_OFF_CREATE(x) (((x) & 0xff) << 24) -#define GLOBAL_REG_PRM_VC_CMD_VAL_1_OFF_GET(r) (((x) >> 24) & 0xff) - - ioport32_t ch_conf; -#define GLOBAL_REG_PRM_VC_CH_CONF_CMD1_FLAG (1 << 20) -#define GLOBAL_REG_PRM_VC_CH_CONF_RACEN1_FLAG (1 << 19) -#define GLOBAL_REG_PRM_VC_CH_CONF_RAC1_FLAG (1 << 18) -#define GLOBAL_REG_PRM_VC_CH_CONF_RAV1_FLAG (1 << 17) -#define GLOBAL_REG_PRM_VC_CH_CONF_SA1_FLAG (1 << 16) -#define GLOBAL_REG_PRM_VC_CH_CONF_CMD0_FLAG (1 << 4) -#define GLOBAL_REG_PRM_VC_CH_CONF_RACEN0_FLAG (1 << 3) -#define GLOBAL_REG_PRM_VC_CH_CONF_RAC0_FLAG (1 << 2) -#define GLOBAL_REG_PRM_VC_CH_CONF_RAV0_FLAG (1 << 1) -#define GLOBAL_REG_PRM_VC_CH_CONF_SA0_FLAG (1 << 0) - - ioport32_t i2c_cfg; -#define GLOBAL_REG_PRM_VC_I2C_CFG_HSMASTER_FLAG (1 << 5) -#define GLOBAL_REG_PRM_VC_I2C_CFG_SREN_FLAG (1 << 4) -#define GLOBAL_REG_PRM_VC_I2C_CFG_HSEN_FLAG (1 << 3) -#define GLOBAL_REG_PRM_VC_I2C_CFG_MCODE_MASK (0x3 << 0) -#define GLOBAL_REG_PRM_VC_I2C_CFG_MCODE_CREATE(x) ((x) & 0x3) -#define GLOBAL_REG_PRM_VC_I2C_CFG_MCODE_GET(r) ((r) & 0x3) - - ioport32_t bypass_val; -#define GLOBAL_REG_PRM_VC_BYPASS_VAL_VALID_FLAG (1 << 24) -#define GLOBAL_REG_PRM_VC_BYPASS_VAL_DATA_MASK (0xff << 16) -#define GLOBAL_REG_PRM_VC_BYPASS_VAL_DATA_CREATE(x) (((x) & 0xff) << 16) -#define GLOBAL_REG_PRM_VC_BYPASS_VAL_DATA_GET(r) (((r) >> 16) & 0xff) -#define GLOBAL_REG_PRM_VC_BYPASS_VAL_REGADDR_MASK (0xff << 8) -#define GLOBAL_REG_PRM_VC_BYPASS_VAL_REGADDR_CREATE(x) (((x) & 0xff) << 8) -#define GLOBAL_REG_PRM_VC_BYPASS_VAL_REGADDR_GET(r) (((r) >> 8) & 0xff) -#define GLOBAL_REG_PRM_VC_BYPASS_VAL_SLAVEADDR_MASK (0x7f << 0) -#define GLOBAL_REG_PRM_VC_BYPASS_VAL_SLAVEADDR_CREATE(x) (((x) & 0x7f) << 0) -#define GLOBAL_REG_PRM_VC_BYPASS_VAL_SLAVEADDR_GET(r) (((r) >> 0) & 0x7f) - } vc; - - PADD32[4]; - ioport32_t rstctrl; -#define GLOBAL_REG_PRM_RSTCTRL_RST_DPLL3_FLAG (1 << 2) -#define GLOBAL_REG_PRM_RSTCTRL_RST_GS_FLAG (1 << 1) - - ioport32_t rsttime; -#define GLOBAL_REG_PRM_RSTTIME_RSTTIME2_MASK (0x1f << 8) -#define GLOBAL_REG_PRM_RSTTIME_RSTTIME2_CREATE(x) (((x) & 0x1f) << 8) -#define GLOBAL_REG_PRM_RSTTIME_RSTTIME2_GET(r) (((r) >> 8) & 0x1f) -#define GLOBAL_REG_PRM_RSTTIME_RSTTIME1_MASK (0xff << 0) -#define GLOBAL_REG_PRM_RSTTIME_RSTTIME1_CREATE(x) (((x) & 0xff) << 0) -#define GLOBAL_REG_PRM_RSTTIME_RSTTIME1_GET(r) (((r) >> 0) & 0xff) - - ioport32_t rstst; -#define GLOBAL_REG_PRM_RSTST_ICECRUSHER_RST_FLAG (1 << 10) -#define GLOBAL_REG_PRM_RSTST_ICEPICK_RST_FLAG (1 << 9) -#define GLOBAL_REG_PRM_RSTST_VDD2_VOLTAGE_MGR_RST_FLAG (1 << 8) -#define GLOBAL_REG_PRM_RSTST_VDD1_VOLTAGE_MGR_RST_FLAG (1 << 7) -#define GLOBAL_REG_PRM_RSTST_EXTERNAL_WARM_REST_FLAG (1 << 6) -#define GLOBAL_REG_PRM_RSTST_MPU_WD_RST_FLAG (1 << 4) -#define GLOBAL_REG_PRM_RSTST_GLOBAL_SW_RST_FLAG (1 << 1) -#define GLOBAL_REG_PRM_RSTST_GLOABL_COLD_RST_FLAG (1 << 0) - - PADD32; - ioport32_t volctrl; -#define GLOBAL_REG_PRM_VOLCTRL_SEL_VMODE_FLAG (1 << 4) -#define GLOBAL_REG_PRM_VOLCTRL_SEL_OFF_FLAG (1 << 3) -#define GLOBAL_REG_PRM_VOLCTRL_AUTO_OFF_FLAG (1 << 2) -#define GLOBAL_REG_PRM_VOLCTRL_AUTO_RET_FLAG (1 << 1) -#define GLOBAL_REG_PRM_VOLCTRL_AUTO_SLEEP_FLAG (1 << 0) - - ioport32_t sram_pcharge; -#define GLOBAL_REG_PRM_SRAM_PCHARGE_PCHARGE_TIME_MASK (0xff) -#define GLOBAL_REG_PRM_SRAM_PCHARGE_PCHARGE_TIME_CREATE(x) ((x) & 0xff) -#define GLOBAL_REG_PRM_SRAM_PCHARGE_PCHARGE_TIME_GET(r) ((r) & 0xff) - - PADD32[2]; - ioport32_t clksrc_ctrl; -#define GLOBAL_REG_PRM_CLKSRC_CTRL_DPLL4_CLKINP_DIV_65_FLAG (1 << 8) -#define GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKDIV_MASK (0x3 << 6) -#define GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKDIV_1 (0x1 << 6) -#define GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKDIV_2 (0x2 << 6) -#define GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKDIV_GET(r) (((r) >> 6) & 0x3) -#define GLOBAL_REG_PRM_CLKSRC_CTRL_AUTOEXTCLKMODE_MASK (0x3 << 3) -#define GLOBAL_REG_PRM_CLKSRC_CTRL_AUTOEXTCLKMODE_ON (0x0 << 3) -#define GLOBAL_REG_PRM_CLKSRC_CTRL_AUTOEXTCLKMODE_SLEEP (0x1 << 3) -#define GLOBAL_REG_PRM_CLKSRC_CTRL_AUTOEXTCLKMODE_RET (0x2 << 3) -#define GLOBAL_REG_PRM_CLKSRC_CTRL_AUTOEXTCLKMODE_OFF (0x3 << 3) -#define GLOBAL_REG_PRM_CLKSRC_CTRL_AUTOEXTCLKMODE_GET(r) (((r) >> 3) & 0x3) -#define GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKSEL_MASK (0x3 << 0) -#define GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKSEL_BYPASS (0x0 << 0) -#define GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKSEL_OSCILLATOR (0x1 << 0) -#define GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKSEL_UNKNOWN (0x3 << 0) -#define GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKSEL_GET(r) (((r) >> 0) & 0x3) - - PADD32[3]; - const ioport32_t obs; -#define GLOBAL_REG_PRM_OBS_OBS_BUS_MASK (0x3ff) - - PADD32[3]; - ioport32_t voltsetup1; -#define GLOBAL_REG_PRM_VOLTSETUP1_SETUPTIME2_MASK (0xff << 16) -#define GLOBAL_REG_PRM_VOLTSETUP1_SETUPTIME2_CREATE(x) (((x) & 0xff) << 16) -#define GLOBAL_REG_PRM_VOLTSETUP1_SETUPTIME2_GET(r) (((r) >> 16) & 0xff) -#define GLOBAL_REG_PRM_VOLTSETUP1_SETUPTIME1_MASK (0xff << 0) -#define GLOBAL_REG_PRM_VOLTSETUP1_SETUPTIME1_CREATE(x) (((x) & 0xff) << 0) -#define GLOBAL_REG_PRM_VOLTSETUP1_SETUPTIME1_GET(r) (((r) >> 0) & 0xff) - - ioport32_t voltoffset; -#define GLOBAL_REG_PRM_VOLTOFFSET_OFFSET_TIME_MASK (0xffff << 0) -#define GLOBAL_REG_PRM_VOLTOFFSET_OFFSET_TIME_CREATE(x) (((x) & 0xffff) << 0) -#define GLOBAL_REG_PRM_VOLTOFFSET_OFFSET_TIME_GET(r) (((r) >> 0) & 0xffff) - - ioport32_t clksetup; -#define GLOBAL_REG_PRM_CLKSETUP_SETUP_TIME_MASK (0xffff << 0) -#define GLOBAL_REG_PRM_CLKSETUP_SETUP_TIME_CREATE(x) (((x) & 0xffff) << 0) -#define GLOBAL_REG_PRM_CLKSETUP_SETUP_TIME_GET(r) (((r) >> 0) & 0xffff) - - ioport32_t polctrl; -#define GLOBAL_REG_PRM_POLCTRL_OFFMODE_POL_FLAG (1 << 3) -#define GLOBAL_REG_PRM_POLCTRL_CLKOUT_POL_FLAG (1 << 2) -#define GLOBAL_REG_PRM_POLCTRL_CLKREG_POL_FLAG (1 << 1) -#define GLOBAL_REG_PRM_POLCTRL_EXTVOL_POL_FLAG (1 << 0) - - ioport32_t voltsetup2; -#define GLOBAL_REG_PRM_VOLTSETUP2_OFFMODESETUPTIME_MASK (0xffff << 0) -#define GLOBAL_REG_PRM_VOLTSETUP2_OFFMODESETUPTIME_CREATE(x) (((x) & 0xffff) << 0) -#define GLOBAL_REG_PRM_VOLTSETUP2_OFFMODESETUPTIME_GET(r) (((r) >> 0) & 0xffff) - - PADD32[3]; - struct { - ioport32_t config; -#define GLOBAL_REG_PRM_VP_CONFIG_ERROROFFSET_MASK (0xff << 24) -#define GLOBAL_REG_PRM_VP_CONFIG_ERROROFFSET_CREATE(x) (((x) & 0xff) << 24) -#define GLOBAL_REG_PRM_VP_CONFIG_ERROROFFSET_GET(r) (((r) >> 0xff << 24) -#define GLOBAL_REG_PRM_VP_CONFIG_ERRORGAIN_MASK (0xff << 16) -#define GLOBAL_REG_PRM_VP_CONFIG_ERRORGAIN_CREATE(x) (((x) & 0xff) << 16) -#define GLOBAL_REG_PRM_VP_CONFIG_ERRORGAIN_GET(r) (((r) >> 0xff << 16) -#define GLOBAL_REG_PRM_VP_CONFIG_INITVOLTAGE_MASK (0xff << 8) -#define GLOBAL_REG_PRM_VP_CONFIG_INITVOLTAGE_CREATE(x) (((x) & 0xff) << 8) -#define GLOBAL_REG_PRM_VP_CONFIG_INITVOLTAGE_GET(r) (((r) >> 0xff << 8) -#define GLOBAL_REG_PRM_VP_CONFIG_TIMEOUTEN_FLAG (1 << 3) -#define GLOBAL_REG_PRM_VP_CONFIG_INITVDD_FLAG (1 << 2) -#define GLOBAL_REG_PRM_VP_CONFIG_FORCEUPDATE_FLAG (1 << 1) -#define GLOBAL_REG_PRM_VP_CONFIG_VPENABLE_FLAG (1 << 0) - - ioport32_t vstepmin; -#define GLOBAL_REG_PRM_VP_VSTEPMIN_SMPSWAITTIMEMIN_MASK (0xffff << 8) -#define GLOBAL_REG_PRM_VP_VSTEPMIN_SMPSWAITTIMEMIN_CREATE(x) (((x)0xffff << 8) -#define GLOBAL_REG_PRM_VP_VSTEPMIN_SMPSWAITTIMEMIN_GET(r) (((r) >> 8) & 0xffff) -#define GLOBAL_REG_PRM_VP_VSTEPMIN_VSTEPMIN_MASK (0xff << 0) -#define GLOBAL_REG_PRM_VP_VSTEPMIN_VSTEPMIN_CREATE(x) (((x)0xff << 0) -#define GLOBAL_REG_PRM_VP_VSTEPMIN_VSTEPMIN_GET(r) (((r) >> 0) & 0xff) - - ioport32_t vstepmax; -#define GLOBAL_REG_PRM_VP_VSTEPMAX_SMPSWAITTIMEMIN_MASK (0xffff << 8) -#define GLOBAL_REG_PRM_VP_VSTEPMAX_SMPSWAITTIMEMIN_CREATE(x) (((x)0xffff << 8) -#define GLOBAL_REG_PRM_VP_VSTEPMAX_SMPSWAITTIMEMIN_GET(r) (((r) >> 8) & 0xffff) -#define GLOBAL_REG_PRM_VP_VSTEPMAX_VSTEPMIN_MASK (0xff << 0) -#define GLOBAL_REG_PRM_VP_VSTEPMAX_VSTEPMIN_CREATE(x) (((x)0xff << 0) -#define GLOBAL_REG_PRM_VP_VSTEPMAX_VSTEPMIN_GET(r) (((r) >> 0) & 0xff) - - ioport32_t vlimitto; -#define GLOBAL_REG_PRM_VP_VLIMITTO_VDDMAX_MASK (0xff << 24) -#define GLOBAL_REG_PRM_VP_VLIMITTO_VDDMAX_CREATE(x) (((x)0xff << 24) -#define GLOBAL_REG_PRM_VP_VLIMITTO_VDDMAX_GET(r) (((r) >> 24) & 0xff) -#define GLOBAL_REG_PRM_VP_VLIMITTO_VDDMIN_MASK (0xff << 16) -#define GLOBAL_REG_PRM_VP_VLIMITTO_VDDMIN_CREATE(x) (((x)0xff << 16) -#define GLOBAL_REG_PRM_VP_VLIMITTO_VDDMIN_GET(r) (((r) >> 16) & 0xff) -#define GLOBAL_REG_PRM_VP_VLIMITTO_TIMEOUT_MASK (0xffff << 0) -#define GLOBAL_REG_PRM_VP_VLIMITTO_TIMEOUT_CREATE(x) (((x)0xffff << 0) -#define GLOBAL_REG_PRM_VP_VLIMITTO_TIMEOUT_GET(r) (((r) >> 0) & 0xffff) - - const ioport32_t voltage; -#define GLOBAL_REG_PRM_VP_VOLTAGE_VPVOLTAGE_MASK (0xff) -#define GLOBAL_REG_PRM_VP_VOLTAGE_VPVOLTAGE_GET(r) ((r) & 0xff) - - const ioport32_t status; -#define GLOBAL_REG_PRM_VP_STATUS_VPINIDLE_FLAG (1 << 0) - - PADD32[2]; - } vp[2]; - - ioport32_t ldo_abb_setup; -#define GLOBAL_REG_PRM_LDO_ABB_SETUP_SR2_IN_TRANSITION (1 << 6) -#define GLOBAL_REG_PRM_LDO_ABB_SETUP_SR2_STATUS_MASK (0x3 << 3) -#define GLOBAL_REG_PRM_LDO_ABB_SETUP_SR2_STATUS_BYPASS (0x0 << 3) -#define GLOBAL_REG_PRM_LDO_ABB_SETUP_SR2_STATUS_FBB (0x2 << 3) -#define GLOBAL_REG_PRM_LDO_ABB_SETUP_SR2_OPP_CHANGE_FLAG (1 << 2) -#define GLOBAL_REG_PRM_LDO_ABB_SETUP_OPP_SEL_MASK (0x3 << 0) -#define GLOBAL_REG_PRM_LDO_ABB_SETUP_OPP_SEL_DEFAULT (0x0 << 0) -#define GLOBAL_REG_PRM_LDO_ABB_SETUP_OPP_SEL_FAST (0x1 << 0) -#define GLOBAL_REG_PRM_LDO_ABB_SETUP_OPP_SEL_NOMINAL (0x2 << 0) -#define GLOBAL_REG_PRM_LDO_ABB_SETUP_OPP_SEL_SLOW (0x3 << 0) - - ioport32_t ldo_abb_ctrl; -#define GLOBAL_REG_PRM_LDO_ABB_CTRL_SR2_WTCNT_VALUE_MASK (0xff << 8) -#define GLOBAL_REG_PRM_LDO_ABB_CTRL_SR2_WTCNT_VALUE_CREATE(x) (((x) & 0xff) << 8) -#define GLOBAL_REG_PRM_LDO_ABB_CTRL_SR2_WTCNT_VALUE_GET(r) (((r) >> 8) & 0xff) -#define GLOBAL_REG_PRM_LDO_ABB_CTRL_ACTIVE_FBB_SEL_FLAG (1 << 2) -#define GLOBAL_REG_PRM_LDO_ABB_CTRL_SR2EN (1 << 0) -} global_reg_prm_regs_t; - -#endif -/** - * @} - */ Index: uspace/drv/infrastructure/rootamdm37x/prm/usbhost.h =================================================================== --- uspace/drv/infrastructure/rootamdm37x/prm/usbhost.h (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ (revision ) @@ -1,111 +1,0 @@ -/* - * Copyright (c) 2012 Jan Vesely - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup amdm37xdrvprm - * @{ - */ -/** @file - * @brief Clock Control Clock Management IO register structure. - */ -#ifndef AMDM37X_PRM_CLOCK_CONTROL_H -#define AMDM37X_PRM_CLOCK_CONTROL_H -#include -#include - -/* AM/DM37x TRM p.536 and p.589 */ -#define CLOCK_CONTROL_CM_BASE_ADDRESS 0x48307400 -#define CLOCK_CONTROL_CM_SIZE 8192 - -/** Clock control PRM register map - * - * Periph DPLL == DPLL4 - * Core DPLL == DPLL3 - */ -typedef struct { - PADD32[22]; - ioport32_t rm_rstst; -#define USBHOST_PRM_RM_RSTST_COREDOMAINWKUP_RST_FLAG (1 << 3) -#define USBHOST_PRM_RM_RSTST_DOMAINWKUP_RST_FLAG (1 << 2) -#define USBHOST_PRM_RM_RSTST_GLOBALWARM_RST_FLAG (1 << 1) -#define USBHOST_PRM_RM_RSTST_GLOBALCOLD_RST_FLAG (1 << 0) - - PADD32[18]; - ioport32_t pm_wken; -#define USBHOST_PRM_PM_WKEN_EN_USBHOST_FLAG (1 << 0) - - ioport32_t pm_mpugrpsel; -#define USBHOST_PRM_PM_MPUGRPSEL_GRPSEL_USBHOST_FLAG (1 << 0) - - ioport32_t pm_iva2grpsel; -#define USBHOST_PRM_PM_IVA2GRPSEL_GRPSEL_USBHOST_FLAG (1 << 0) - - PADD32; - ioport32_t pm_wkst; -#define USBHOST_PRM_PM_WKST_ST_USBHOST_FLAG (1 << 0) - - PADD32[5]; - ioport32_t pm_wkdep; -#define USBHOST_PRM_PM_WKDEP_EN_WKUP_FLAG (1 << 4) -#define USBHOST_PRM_PM_WKDEP_EN_IVA2_FLAG (1 << 2) -#define USBHOST_PRM_PM_WKDEP_EN_MPU_FLAG (1 << 1) -#define USBHOST_PRM_PM_WKDEP_EN_CORE_FLAG (1 << 0) - - PADD32[5]; - ioport32_t pm_pwstctrl; -#define USBHOST_PRM_PM_PWSTCTRL_MEMONSTATE_MASK (0x3 << 16) -#define USBHOST_PRM_PM_PWSTCTRL_MEMONSTATE_ALWAYS_ON (0x3 << 16) -#define USBHOST_PRM_PM_PWSTCTRL_MEMRETSTATE_FLAG (1 << 8) -#define USBHOST_PRM_PM_PWSTCTRL_SAVEANDRESTORE_FLAG (1 << 4) -#define USBHOST_PRM_PM_PWSTCTRL_LOGICRESTATE_FLAG (1 << 2) -#define USBHOST_PRM_PM_PWSTCTRL_POWERSTATE_MASK (0x3 << 0) -#define USBHOST_PRM_PM_PWSTCTRL_POWERSTATE_OFF (0x0 << 0) -#define USBHOST_PRM_PM_PWSTCTRL_POWERSTATE_RETENTION (0x1 << 0) -#define USBHOST_PRM_PM_PWSTCTRL_POWERSTATE_ON (0x3 << 0) - - const ioport32_t pm_pwstst; -#define USBHOST_PRM_PM_PWSTST_INTRANSITION_FLAG (1 << 20) -#define USBHOST_PRM_PM_PWSTST_POWERSTATEST_MASK (0x3 << 0) -#define USBHOST_PRM_PM_PWSTST_POWERSTATEST_OFF (0x0 << 0) -#define USBHOST_PRM_PM_PWSTST_POWERSTATEST_RETENTION (0x1 << 0) -#define USBHOST_PRM_PM_PWSTST_POWERSTATEST_INACTIVE (0x2 << 0) -#define USBHOST_PRM_PM_PWSTST_POWERSTATEST_ON (0x3 << 0) - - ioport32_t pm_prepwstst; -#define USBHOST_PRM_PM_PREPWSTST_LASTPOWERSTATEENTERED_MASK (0x3 << 0) -#define USBHOST_PRM_PM_PREPWSTST_LASTPOWERSTATEENTERED_OFF (0x0 << 0) -#define USBHOST_PRM_PM_PREPWSTST_LASTPOWERSTATEENTERED_RETENTION (0x1 << 0) -#define USBHOST_PRM_PM_PREPWSTST_LASTPOWERSTATEENTERED_INACTIVE (0x2 << 0) -#define USBHOST_PRM_PM_PREPWSTST_LASTPOWERSTATEENTERED_ON (0x3 << 0) - -} usbhost_prm_regs_t; - -#endif -/** - * @} - */ - Index: uspace/drv/infrastructure/rootamdm37x/rootamdm37x.c =================================================================== --- uspace/drv/infrastructure/rootamdm37x/rootamdm37x.c (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ (revision ) @@ -1,282 +1,0 @@ -/* - * Copyright (c) 2012 Jan Vesely - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** - * @defgroup root_amdm37x TI AM/DM37x platform driver. - * @brief HelenOS TI AM/DM37x platform driver. - * @{ - */ - -/** @file - */ - -#define DEBUG_CM 0 - -#include -#include -#include -#include - -#include "amdm37x.h" - -#define NAME "rootamdm37x" - -typedef struct { - const char *name; - match_id_t match_id; - hw_resource_list_t hw_resources; -} rootamdm37x_fun_t; - -/* See amdm37x TRM page 3316 for these values */ -#define OHCI_BASE_ADDRESS 0x48064400 -#define OHCI_SIZE 1024 -#define EHCI_BASE_ADDRESS 0x48064800 -#define EHCI_SIZE 1024 - -/* See amdm37x TRM page 1813 for these values */ -#define DSS_BASE_ADDRESS 0x48050000 -#define DSS_SIZE 512 -#define DISPC_BASE_ADDRESS 0x48050400 -#define DISPC_SIZE 1024 -#define VIDEO_ENC_BASE_ADDRESS 0x48050C00 -#define VIDEO_ENC_SIZE 256 - - -static hw_resource_t ohci_res[] = { - { - .type = MEM_RANGE, - .res.io_range = { - .address = OHCI_BASE_ADDRESS, - .size = OHCI_SIZE, - .endianness = LITTLE_ENDIAN - }, - }, - { - .type = INTERRUPT, - .res.interrupt = { .irq = 76 }, - }, -}; - -static hw_resource_t ehci_res[] = { - { - .type = MEM_RANGE, - /* See amdm37x TRM page. 3316 for these values */ - .res.io_range = { - .address = EHCI_BASE_ADDRESS, - .size = EHCI_SIZE, - .endianness = LITTLE_ENDIAN - }, - }, - { - .type = INTERRUPT, - .res.interrupt = { .irq = 77 }, - }, -}; - -static hw_resource_t disp_res[] = { - { - .type = MEM_RANGE, - .res.io_range = { - .address = DSS_BASE_ADDRESS, - .size = DSS_SIZE, - .endianness = LITTLE_ENDIAN - }, - }, - { - .type = MEM_RANGE, - .res.io_range = { - .address = DISPC_BASE_ADDRESS, - .size = DISPC_SIZE, - .endianness = LITTLE_ENDIAN - }, - }, - { - .type = MEM_RANGE, - .res.io_range = { - .address = VIDEO_ENC_BASE_ADDRESS, - .size = VIDEO_ENC_SIZE, - .endianness = LITTLE_ENDIAN - }, - }, - { - .type = INTERRUPT, - .res.interrupt = { .irq = 25 }, - }, -}; - -static const rootamdm37x_fun_t amdm37x_funcs[] = { -{ - .name = "ohci", - .match_id = { .id = "usb/host=ohci", .score = 90 }, - .hw_resources = { .resources = ohci_res, .count = ARRAY_SIZE(ohci_res) } -}, -{ - .name = "ehci", - .match_id = { .id = "usb/host=ehci", .score = 90 }, - .hw_resources = { .resources = ehci_res, .count = ARRAY_SIZE(ehci_res) } -}, -{ - .name = "fb", - .match_id = { .id = "amdm37x&dispc", .score = 90 }, - .hw_resources = { .resources = disp_res, .count = ARRAY_SIZE(disp_res) } -}, -}; - - -static hw_resource_list_t *rootamdm37x_get_resources(ddf_fun_t *fnode); -static bool rootamdm37x_enable_interrupt(ddf_fun_t *fun); - -static hw_res_ops_t fun_hw_res_ops = { - .get_resource_list = &rootamdm37x_get_resources, - .enable_interrupt = &rootamdm37x_enable_interrupt, -}; - -static ddf_dev_ops_t rootamdm37x_fun_ops = { - .interfaces[HW_RES_DEV_IFACE] = &fun_hw_res_ops -}; - -static int rootamdm37x_add_fun(ddf_dev_t *dev, const rootamdm37x_fun_t *fun) -{ - assert(dev); - assert(fun); - - ddf_msg(LVL_DEBUG, "Adding new function '%s'.", fun->name); - - /* Create new device function. */ - ddf_fun_t *fnode = ddf_fun_create(dev, fun_inner, fun->name); - if (fnode == NULL) - return ENOMEM; - - /* Add match id */ - int ret = ddf_fun_add_match_id(fnode, - fun->match_id.id, fun->match_id.score); - if (ret != EOK) { - ddf_fun_destroy(fnode); - return ret; - } - - /* Alloc needed data */ - rootamdm37x_fun_t *rf = - ddf_fun_data_alloc(fnode, sizeof(rootamdm37x_fun_t)); - if (!rf) { - ddf_fun_destroy(fnode); - return ENOMEM; - } - *rf = *fun; - - /* Set provided operations to the device. */ - ddf_fun_set_ops(fnode, &rootamdm37x_fun_ops); - - /* Register function. */ - ret = ddf_fun_bind(fnode); - if (ret != EOK) { - ddf_msg(LVL_ERROR, "Failed binding function %s.", fun->name); - ddf_fun_destroy(fnode); - return ret; - } - - return EOK; -} - -/** Add the root device. - * - * @param dev Device which is root of the whole device tree - * (both of HW and pseudo devices). - * - * @return Zero on success, negative error number otherwise. - * - */ -static int rootamdm37x_dev_add(ddf_dev_t *dev) -{ - assert(dev); - amdm37x_t *device = ddf_dev_data_alloc(dev, sizeof(amdm37x_t)); - if (!device) - return ENOMEM; - int ret = amdm37x_init(device, DEBUG_CM); - if (ret != EOK) { - ddf_msg(LVL_FATAL, "Failed to setup hw access!.\n"); - return ret; - } - - /* Set dplls to ON and automatic */ - amdm37x_setup_dpll_on_autoidle(device); - - /* Enable function and interface clocks */ - amdm37x_usb_clocks_set(device, true); - - /* Init TLL */ - ret = amdm37x_usb_tll_init(device); - if (ret != EOK) { - ddf_msg(LVL_FATAL, "Failed to init USB TLL!.\n"); - amdm37x_usb_clocks_set(device, false); - return ret; - } - - /* Register functions */ - for (unsigned i = 0; i < ARRAY_SIZE(amdm37x_funcs); ++i) { - if (rootamdm37x_add_fun(dev, &amdm37x_funcs[i]) != EOK) - ddf_msg(LVL_ERROR, "Failed to add %s function for " - "BeagleBoard-xM platform.", amdm37x_funcs[i].name); - } - return EOK; -} - -/** The root device driver's standard operations. */ -static driver_ops_t rootamdm37x_ops = { - .dev_add = &rootamdm37x_dev_add -}; - -/** The root device driver structure. */ -static driver_t rootamdm37x_driver = { - .name = NAME, - .driver_ops = &rootamdm37x_ops -}; - -static hw_resource_list_t * rootamdm37x_get_resources(ddf_fun_t *fnode) -{ - rootamdm37x_fun_t *fun = ddf_fun_data_get(fnode); - assert(fun != NULL); - return &fun->hw_resources; -} - -static bool rootamdm37x_enable_interrupt(ddf_fun_t *fun) -{ - //TODO: Implement - return false; -} - -int main(int argc, char *argv[]) -{ - printf("%s: HelenOS AM/DM37x(OMAP37x) platform driver\n", NAME); - ddf_log_init(NAME); - return ddf_driver_main(&rootamdm37x_driver); -} - -/** - * @} - */ Index: uspace/drv/infrastructure/rootamdm37x/rootamdm37x.ma =================================================================== --- uspace/drv/infrastructure/rootamdm37x/rootamdm37x.ma (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ (revision ) @@ -1,1 +1,0 @@ -10 platform/beagleboardxm Index: uspace/drv/infrastructure/rootamdm37x/uhh.h =================================================================== --- uspace/drv/infrastructure/rootamdm37x/uhh.h (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ (revision ) @@ -1,97 +1,0 @@ -/* - * Copyright (c) 2012 Jan Vesely - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup amdm37xdrvuhh - * @{ - */ -/** @file - * @brief UHH IO register structure. - */ -#ifndef AMDM37x_UHH_H -#define AMDM37x_UHH_H -#include -#include - -#define AMDM37x_UHH_BASE_ADDRESS 0x48064000 -#define AMDM37x_UHH_SIZE 1024 - -typedef struct { - const ioport32_t revision; -#define UHH_REVISION_MINOR_MASK 0x0f -#define UHH_REVISION_MAJOR_MASK 0xf0 - - PADD32[3]; - ioport32_t sysconfig; -#define UHH_SYSCONFIG_AUTOIDLE_FLAG (1 << 0) -#define UHH_SYSCONFIG_SOFTRESET_FLAG (1 << 1) -#define UHH_SYSCONFIG_ENWAKEUP_FLAG (1 << 2) -#define UHH_SYSCONFIG_SIDLE_MODE_MASK (0x3 << 3) -#define UHH_SYSCONFIG_SIDLE_MODE_FORCE (0x0 << 3) -#define UHH_SYSCONFIG_SIDLE_MODE_NO (0x1 << 3) -#define UHH_SYSCONFIG_SIDLE_MODE_SMART (0x2 << 3) -#define UHH_SYSCONFIG_CLOCKACTIVITY_FLAG (1 << 8) -#define UHH_SYSCONFIG_MIDLE_MODE_MASK (0x3 << 12) -#define UHH_SYSCONFIG_MIDLE_MODE_FORCE (0x0 << 12) -#define UHH_SYSCONFIG_MIDLE_MODE_NO (0x1 << 12) -#define UHH_SYSCONFIG_MIDLE_MODE_SMART (0x2 << 12) - - const ioport32_t sysstatus; -#define UHH_SYSSTATUS_RESETDONE_FLAG (1 << 0) -#define UHH_SYSSTATUS_OHCI_RESETDONE_FLAG (1 << 1) -#define UHH_SYSSTATUS_EHCI_RESETDONE_FLAG (1 << 2) - - PADD32[10]; - ioport32_t hostconfig; -#define UHH_HOSTCONFIG_P1_ULPI_BYPASS_FLAG (1 << 0) -#define UHH_HOSTCONFIG_AUTOPPD_ON_OVERCUR_EN_FLAG (1 << 1) -#define UHH_HOSTCONFIG_ENA_INCR4_FLAG (1 << 2) -#define UHH_HOSTCONFIG_ENA_INCR8_FLAG (1 << 3) -#define UHH_HOSTCONFIG_ENA_INCR16_FLA (1 << 4) -#define UHH_HOSTCONFIG_ENA_INCR_ALIGN_FLAG (1 << 5) -#define UHH_HOSTCONFIG_P1_CONNECT_STATUS_FLAG (1 << 8) -#define UHH_HOSTCONFIG_P2_CONNECT_STATUS_FLAG (1 << 9) -#define UHH_HOSTCONFIG_P3_CONNECT_STATUS_FLAG (1 << 10) -#define UHH_HOSTCONFIG_P2_ULPI_BYPASS_FLAG (1 << 11) -#define UHH_HOSTCONFIG_P3_ULPI_BYPASS_FLAG (1 << 12) - - ioport32_t debug_csr; -#define UHH_DEBUG_CSR_EHCI_FLADJ_MASK (0x3f << 0) -#define UHH_DEBUG_CSR_EHCI_FLADJ(x) ((x) & 0x3f) -#define UHH_DEBUG_CSR_EHCI_SIMULATION_MODE_FLAG (1 << 6) -#define UHH_DEBUG_CSR_OHCI_CNTSEL_FLAG (1 << 7) -#define UHH_DEBUG_CSR_OHCI_GLOBAL_SUSPEND_FLAG (1 << 16) -#define UHH_DEBUG_CSR_OHCI_CCS1_FLAG (1 << 17) -#define UHH_DEBUG_CSR_OHCI_CCS2_FLAG (1 << 18) -#define UHH_DEBUG_CSR_OHCI_CCS3_FLAG (1 << 19) - -} uhh_regs_t; - -#endif -/** - * @} - */ Index: uspace/drv/infrastructure/rootamdm37x/usbtll.h =================================================================== --- uspace/drv/infrastructure/rootamdm37x/usbtll.h (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ (revision ) @@ -1,129 +1,0 @@ -/* - * Copyright (c) 2012 Jan Vesely - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup amdm37xdrvusbtll - * @{ - */ -/** @file - * @brief USBTLL IO register structure. - */ -#ifndef AMDM37x_USBTLL_H -#define AMDM37x_USBTLL_H -#include -#include - -#define AMDM37x_USBTLL_BASE_ADDRESS 0x48062000 -#define AMDM37x_USBTLL_SIZE 4096 - -typedef struct { - const ioport32_t revision; -#define TLL_REVISION_MINOR_MASK 0x0f -#define TLL_REVISION_MAJOR_MASK 0xf0 - - PADD32[3]; - ioport32_t sysconfig; -#define TLL_SYSCONFIG_AUTOIDLE_FLAG (1 << 0) -#define TLL_SYSCONFIG_SOFTRESET_FLAG (1 << 1) -#define TLL_SYSCONFIG_ENWAKEUP_FLAG (1 << 2) -#define TLL_SYSCONFIG_SIDLE_MODE_MASK (0x3 << 3) -#define TLL_SYSCONFIG_SIDLE_MODE_FORCE (0x0 << 3) -#define TLL_SYSCONFIG_SIDLE_MODE_NO (0x1 << 3) -#define TLL_SYSCONFIG_SIDLE_MODE_SMART (0x2 << 3) -#define TLL_SYSCONFIG_CLOCKACTIVITY_FLAG (1 << 8) - - const ioport32_t sysstatus; -#define TLL_SYSSTATUS_RESET_DONE_FLAG (1 << 0) - - const ioport32_t irqstatus; -#define TLL_IRQSTATUS_FCLK_START_FLAG (1 << 0) -#define TLL_IRQSTATUS_FCLK_END_FLAG (1 << 1) -#define TLL_IRQSTATUS_ACCESS_ERROR_FLAG (1 << 2) - - ioport32_t irqenable; -#define TLL_IRQSTATUS_FCLK_START_EN_FLAG (1 << 0) -#define TLL_IRQSTATUS_FCLK_END_EN_FLAG (1 << 1) -#define TLL_IRQSTATUS_ACCESS_ERROR_EN_FLAG (1 << 2) - - PADD32[4]; - ioport32_t shared_conf; -#define TLL_SHARED_CONF_FCLK_IS_ON_FLAG (1 << 0) -#define TLL_SHARED_CONF_FCLK_REQ_FLAG (1 << 1) -#define TLL_SHARED_CONF_USB_DIVRATIO_MASK (0x7 << 2) -#define TLL_SHARED_CONF_USB_DIVRATIO(x) (((x) & 0x7) << 2) -#define TLL_SHARED_CONF_USB_180D_SDR_EN_FLAG (1 << 5) -#define TLL_SHARED_CONF_USB_90D_DDR_EN_FLAG (1 << 6) - - PADD32[3]; - ioport32_t channel_conf[3]; -#define TLL_CHANNEL_CONF_CHANEN_FLAG (1 << 0) -#define TLL_CHANNEL_CONF_CHANMODE_MASK (0x3 << 1) -#define TLL_CHANNEL_CONF_CHANMODE_UTMI_ULPI_MODE (0x0 << 1) -#define TLL_CHANNEL_CONF_CHANMODE_UTMI_SERIAL_MODE (0x1 << 1) -#define TLL_CHANNEL_CONF_CHANMODE_UTMI_TRANS_MODE (0x2 << 1) -#define TLL_CHANNEL_CONF_CHANMODE_NO_MODE (0x3 << 1) -#define TLL_CHANNEL_CONF_UTMIISADEV_FLAG (1 << 3) -#define TLL_CHANNEL_CONF_TLLATTACH_FLAG (1 << 4) -#define TLL_CHANNEL_CONF_TLLCONNECT_FLAG (1 << 5) -#define TLL_CHANNEL_CONF_TLLFULLSPEED_FLAG (1 << 6) -#define TLL_CHANNEL_CONF_ULPIOUTCLKMODE_FLAG (1 << 7) -#define TLL_CHANNEL_CONF_ULPIDDRMODE_FLAG (1 << 8) -#define TLL_CHANNEL_CONF_UTMIAUTOIDLE_FLAG (1 << 9) -#define TLL_CHANNEL_CONF_ULPIAUTOIDLE_FLAG (1 << 10) -#define TLL_CHANNEL_CONF_ULPINOBITSTUFF_FLAG (1 << 11) -#define TLL_CHANNEL_CONF_CHRGVBUS_FLAG (1 << 15) -#define TLL_CHANNEL_CONF_DRVVBUS_FLAG (1 << 16) -#define TLL_CHANNEL_CONF_TESTEN_FLAG (1 << 17) -#define TLL_CHANNEL_CONF_TESTTXEN_FLAG (1 << 18) -#define TLL_CHANNEL_CONF_TESTTXDAT_FLAG (1 << 19) -#define TLL_CHANNEL_CONF_TESTTXSE0_FLAG (1 << 20) -#define TLL_CHANNEL_CONF_FSLSMODE_MASK (0xf << 24) -#define TLL_CHANNEL_CONF_FSLSMODE_6PIN_UNI_PHY_TX_DATSE0 (0x0 << 24) -#define TLL_CHANNEL_CONF_FSLSMODE_6PIN_UNI_PHY_TX_DPDM (0x1 << 24) -#define TLL_CHANNEL_CONF_FSLSMODE_3PIN_BIDI_PHY (0x2 << 24) -#define TLL_CHANNEL_CONF_FSLSMODE_4PIN_BIDI_PHY (0x3 << 24) -#define TLL_CHANNEL_CONF_FSLSMODE_6PIN_UNI_TLL_TX_DATSE0 (0x4 << 24) -#define TLL_CHANNEL_CONF_FSLSMODE_6PIN_UNI_TLL_TX_DPDM (0x5 << 24) -#define TLL_CHANNEL_CONF_FSLSMODE_3PIN_BIDI_TLL (0x6 << 24) -#define TLL_CHANNEL_CONF_FSLSMODE_4PIN_BIDI_TLL (0x7 << 24) -#define TLL_CHANNEL_CONF_FSLSMODE_2PIN_BIDI_TLL_DATSE0 (0xa << 24) -#define TLL_CHANNEL_CONF_FSLSMODE_2PIN_BIDI_TLL_DPDM (0xb << 24) - -#define TLL_CHANNEL_CONF_FSLSLINESTATE_MASK (0x3 << 28) -#define TLL_CHANNEL_CONF_FSLSLINESTATE_SE0 (0x0 << 28) -#define TLL_CHANNEL_CONF_FSLSLINESTATE_FS_J (0x1 << 28) -#define TLL_CHANNEL_CONF_FSLSLINESTATE_FS_K (0x2 << 28) -#define TLL_CHANNEL_CONF_FSLSLINESTATE_SE1 (0x3 << 28) - - /* The rest are 8bit ULPI registers */ -} tll_regs_t; - -#endif -/** - * @} - */ - Index: uspace/drv/infrastructure/rootleon3/Makefile =================================================================== --- uspace/drv/infrastructure/rootleon3/Makefile (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ (revision ) @@ -1,37 +1,0 @@ -# -# Copyright (c) 2012 Jan Vesely -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# - Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# - Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# - The name of the author may not be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# - -USPACE_PREFIX = ../../.. -LIBS = $(LIBDRV_PREFIX)/libdrv.a -EXTRA_CFLAGS += -I$(LIBDRV_PREFIX)/include -BINARY = rootleon3 - -SOURCES = \ - rootleon3.c - -include $(USPACE_PREFIX)/Makefile.common Index: uspace/drv/infrastructure/rootleon3/rootleon3.c =================================================================== --- uspace/drv/infrastructure/rootleon3/rootleon3.c (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ (revision ) @@ -1,195 +1,0 @@ -/* - * Copyright (c) 2012 Jan Vesely - * Copyright (c) 2013 Jakub Klama - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** - * @defgroup root_leon3 SPARC LEON3 platform driver. - * @brief HelenOS SPARC LEON3 platform driver. - * @{ - */ -/** @file - */ - -#include -#include -#include -#include -#include "rootleon3.h" - -#define NAME "rootleon3" - -typedef struct { - const char *name; - match_id_t match_id; - hw_resource_list_t hw_resources; -} rootleon3_fun_t; - -static hw_resource_t amba_res[] = { - { - .type = MEM_RANGE, - .res.mem_range = { - .address = AMBAPP_MASTER_AREA, - .size = AMBAPP_MASTER_SIZE, - .endianness = BIG_ENDIAN - } - }, - { - .type = MEM_RANGE, - .res.mem_range = { - .address = AMBAPP_SLAVE_AREA, - .size = AMBAPP_SLAVE_SIZE, - .endianness = BIG_ENDIAN, - } - } -}; - -static const rootleon3_fun_t leon3_func = { - .name = "leon_amba", - .match_id = { - .id = "leon_amba", - .score = 90 - }, - .hw_resources = { - .count = 2, - .resources = amba_res - } -}; - -static hw_resource_list_t *rootleon3_get_resources(ddf_fun_t *); -static bool rootleon3_enable_interrupt(ddf_fun_t *); - -static hw_res_ops_t fun_hw_res_ops = { - .get_resource_list = &rootleon3_get_resources, - .enable_interrupt = &rootleon3_enable_interrupt -}; - -static ddf_dev_ops_t rootleon3_fun_ops = { - .interfaces[HW_RES_DEV_IFACE] = &fun_hw_res_ops -}; - -static int rootleon3_add_fun(ddf_dev_t *dev, const rootleon3_fun_t *fun) -{ - assert(dev); - assert(fun); - - ddf_msg(LVL_DEBUG, "Adding new function '%s'.", fun->name); - - /* Create new device function. */ - ddf_fun_t *fnode = ddf_fun_create(dev, fun_inner, fun->name); - if (fnode == NULL) - return ENOMEM; - - /* Add match id */ - int ret = ddf_fun_add_match_id(fnode, fun->match_id.id, - fun->match_id.score); - if (ret != EOK) { - ddf_fun_destroy(fnode); - return ret; - } - - /* Allocate needed data */ - rootleon3_fun_t *rf = - ddf_fun_data_alloc(fnode, sizeof(rootleon3_fun_t)); - if (!rf) { - ddf_fun_destroy(fnode); - return ENOMEM; - } - *rf = *fun; - - /* Set provided operations to the device. */ - ddf_fun_set_ops(fnode, &rootleon3_fun_ops); - - /* Register function. */ - ret = ddf_fun_bind(fnode); - if (ret != EOK) { - ddf_msg(LVL_ERROR, "Failed binding function %s.", fun->name); - ddf_fun_destroy(fnode); - return ret; - } - - return EOK; -} - -/** Add the root device. - * - * @param dev Device which is root of the whole device tree - * (both of HW and pseudo devices). - * - * @return Zero on success, negative error number otherwise. - * - */ -static int rootleon3_dev_add(ddf_dev_t *dev) -{ - assert(dev); - - /* Register functions */ - if (rootleon3_add_fun(dev, &leon3_func) != EOK) { - ddf_msg(LVL_ERROR, "Failed to add %s function for " - "LEON3 platform.", leon3_func.name); - } - - return EOK; -} - -/** The root device driver's standard operations. */ -static driver_ops_t rootleon3_ops = { - .dev_add = &rootleon3_dev_add -}; - -/** The root device driver structure. */ -static driver_t rootleon3_driver = { - .name = NAME, - .driver_ops = &rootleon3_ops -}; - -static hw_resource_list_t *rootleon3_get_resources(ddf_fun_t *fnode) -{ - rootleon3_fun_t *fun = ddf_fun_data_get(fnode); - assert(fun != NULL); - - printf("rootleon3_get_resources() called\n"); - - return &fun->hw_resources; -} - -static bool rootleon3_enable_interrupt(ddf_fun_t *fun) -{ - // FIXME TODO - return false; -} - -int main(int argc, char *argv[]) -{ - printf("%s: HelenOS SPARC LEON3 platform driver\n", NAME); - ddf_log_init(NAME); - return ddf_driver_main(&rootleon3_driver); -} - -/** - * @} - */ Index: uspace/drv/infrastructure/rootleon3/rootleon3.h =================================================================== --- uspace/drv/infrastructure/rootleon3/rootleon3.h (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ (revision ) @@ -1,48 +1,0 @@ -/* - * Copyright (c) 2013 Jakub Klama - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup leon3drv - * @{ - */ -/** @file - * @brief LEON3 root device. - */ - -#ifndef ROOTLEON3_H -#define ROOTLEON3_H - -#define AMBAPP_MASTER_AREA 0xfffff000 -#define AMBAPP_SLAVE_AREA 0xfffff800 -#define AMBAPP_MASTER_SIZE 0x800 -#define AMBAPP_SLAVE_SIZE 0x800 - -#endif - -/** - * @} - */ Index: uspace/drv/infrastructure/rootleon3/rootleon3.ma =================================================================== --- uspace/drv/infrastructure/rootleon3/rootleon3.ma (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ (revision ) @@ -1,1 +1,0 @@ -100 platform/leon3 Index: uspace/drv/infrastructure/rootmac/Makefile =================================================================== --- uspace/drv/infrastructure/rootmac/Makefile (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ (revision ) @@ -1,37 +1,0 @@ -# -# Copyright (c) 2010 Lenka Trochtova -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# - Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# - Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# - The name of the author may not be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# - -USPACE_PREFIX = ../../.. -LIBS = $(LIBDRV_PREFIX)/libdrv.a -EXTRA_CFLAGS += -I$(LIBDRV_PREFIX)/include -BINARY = rootmac - -SOURCES = \ - rootmac.c - -include $(USPACE_PREFIX)/Makefile.common Index: uspace/drv/infrastructure/rootmac/rootmac.c =================================================================== --- uspace/drv/infrastructure/rootmac/rootmac.c (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ (revision ) @@ -1,190 +1,0 @@ -/* - * Copyright (c) 2011 Martin Decky - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** - * @defgroup root_mac Mac platform driver. - * @brief HelenOS Mac platform driver. - * @{ - */ - -/** @file - */ - -#include -#include -#include -#include -#include - -#define NAME "rootmac" - -typedef struct { - hw_resource_list_t hw_resources; -} rootmac_fun_t; - -static hw_resource_t pci_conf_regs[] = { - { - .type = IO_RANGE, - .res.io_range = { - .address = 0xfec00000, - .size = 4, - .relative = false, - .endianness = LITTLE_ENDIAN - } - }, - { - .type = IO_RANGE, - .res.io_range = { - .address = 0xfee00000, - .size = 4, - .relative = false, - .endianness = LITTLE_ENDIAN - } - } -}; - -static rootmac_fun_t pci_data = { - .hw_resources = { - 2, - pci_conf_regs - } -}; - -static ddf_dev_ops_t rootmac_fun_ops; - -/** Obtain function soft-state from DDF function node */ -static rootmac_fun_t *rootmac_fun(ddf_fun_t *fnode) -{ - return ddf_fun_data_get(fnode); -} - -static bool rootmac_add_fun(ddf_dev_t *dev, const char *name, - const char *str_match_id, rootmac_fun_t *fun_proto) -{ - ddf_msg(LVL_DEBUG, "Adding new function '%s'.", name); - - ddf_fun_t *fnode = NULL; - int rc; - - /* Create new device. */ - fnode = ddf_fun_create(dev, fun_inner, name); - if (fnode == NULL) - goto failure; - - rootmac_fun_t *fun = ddf_fun_data_alloc(fnode, sizeof(rootmac_fun_t)); - *fun = *fun_proto; - - /* Add match ID */ - rc = ddf_fun_add_match_id(fnode, str_match_id, 100); - if (rc != EOK) - goto failure; - - /* Set provided operations to the device. */ - ddf_fun_set_ops(fnode, &rootmac_fun_ops); - - /* Register function. */ - if (ddf_fun_bind(fnode) != EOK) { - ddf_msg(LVL_ERROR, "Failed binding function %s.", name); - goto failure; - } - - return true; - -failure: - if (fnode != NULL) - ddf_fun_destroy(fnode); - - ddf_msg(LVL_ERROR, "Failed adding function '%s'.", name); - - return false; -} - -/** Get the root device. - * - * @param dev Device which is root of the whole device tree - * (both of HW and pseudo devices). - * - * @return Zero on success, negative error number otherwise. - * - */ -static int rootmac_dev_add(ddf_dev_t *dev) -{ -#if 0 - /* Register functions */ - if (!rootmac_add_fun(dev, "pci0", "intel_pci", &pci_data)) - ddf_msg(LVL_ERROR, "Failed to add functions for Mac platform."); -#else - (void)pci_data; - (void)rootmac_add_fun; -#endif - - return EOK; -} - -/** The root device driver's standard operations. */ -static driver_ops_t rootmac_ops = { - .dev_add = &rootmac_dev_add -}; - -/** The root device driver structure. */ -static driver_t rootmac_driver = { - .name = NAME, - .driver_ops = &rootmac_ops -}; - -static hw_resource_list_t *rootmac_get_resources(ddf_fun_t *fnode) -{ - rootmac_fun_t *fun = rootmac_fun(fnode); - assert(fun != NULL); - - return &fun->hw_resources; -} - -static bool rootmac_enable_interrupt(ddf_fun_t *fun) -{ - /* TODO */ - - return false; -} - -static hw_res_ops_t fun_hw_res_ops = { - .get_resource_list = &rootmac_get_resources, - .enable_interrupt = &rootmac_enable_interrupt -}; - -int main(int argc, char *argv[]) -{ - printf("%s: HelenOS Mac platform driver\n", NAME); - ddf_log_init(NAME); - rootmac_fun_ops.interfaces[HW_RES_DEV_IFACE] = &fun_hw_res_ops; - return ddf_driver_main(&rootmac_driver); -} - -/** - * @} - */ Index: uspace/drv/infrastructure/rootmac/rootmac.ma =================================================================== --- uspace/drv/infrastructure/rootmac/rootmac.ma (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ (revision ) @@ -1,1 +1,0 @@ -10 platform/mac Index: uspace/drv/infrastructure/rootmalta/Makefile =================================================================== --- uspace/drv/infrastructure/rootmalta/Makefile (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ (revision ) @@ -1,37 +1,0 @@ -# -# Copyright (c) 2010 Lenka Trochtova -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# - Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# - Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# - The name of the author may not be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# - -USPACE_PREFIX = ../../.. -LIBS = $(LIBDRV_PREFIX)/libdrv.a -EXTRA_CFLAGS += -I$(LIBDRV_PREFIX)/include -BINARY = rootmalta - -SOURCES = \ - rootmalta.c - -include $(USPACE_PREFIX)/Makefile.common Index: uspace/drv/infrastructure/rootmalta/rootmalta.c =================================================================== --- uspace/drv/infrastructure/rootmalta/rootmalta.c (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ (revision ) @@ -1,273 +1,0 @@ -/* - * Copyright (c) 2010 Lenka Trochtova - * Copyright (c) 2013 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** - * @defgroup root_malta Malta board platform driver. - * @brief HelenOS Malta board platform driver. - * @{ - */ - -/** @file - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#define NAME "rootmalta" - -#define GT_BASE UINT32_C(0x1be00000) -#define GT_SIZE (2 * 1024 * 1024) - -#define GT_PCI_CMD 0xc00 -#define GT_PCI_CONFADDR 0xcf8 -#define GT_PCI_CONFDATA 0xcfc - -#define GT_PCI_CMD_MBYTESWAP 0x1 - -#define GT_PCI_MEMBASE UINT32_C(0x10000000) -#define GT_PCI_MEMSIZE UINT32_C(0x08000000) - -#define GT_PCI_IOBASE UINT32_C(0x18000000) -#define GT_PCI_IOSIZE UINT32_C(0x00200000) - -typedef struct rootmalta_fun { - hw_resource_list_t hw_resources; - pio_window_t pio_window; -} rootmalta_fun_t; - -static int rootmalta_dev_add(ddf_dev_t *dev); -static void root_malta_init(void); - -/** The root device driver's standard operations. */ -static driver_ops_t rootmalta_ops = { - .dev_add = &rootmalta_dev_add -}; - -/** The root device driver structure. */ -static driver_t rootmalta_driver = { - .name = NAME, - .driver_ops = &rootmalta_ops -}; - -static hw_resource_t pci_conf_regs[] = { - { - .type = IO_RANGE, - .res.io_range = { - .address = GT_BASE + GT_PCI_CONFADDR, - .size = 4, - .relative = false, - .endianness = LITTLE_ENDIAN - } - }, - { - .type = IO_RANGE, - .res.io_range = { - .address = GT_BASE + GT_PCI_CONFDATA, - .size = 4, - .relative = false, - .endianness = LITTLE_ENDIAN - } - } -}; - -static rootmalta_fun_t pci_data = { - .hw_resources = { - sizeof(pci_conf_regs) / sizeof(pci_conf_regs[0]), - pci_conf_regs - }, - .pio_window = { - .mem = { - .base = GT_PCI_MEMBASE, - .size = GT_PCI_MEMSIZE - }, - .io = { - .base = GT_PCI_IOBASE, - .size = GT_PCI_IOSIZE - } - } -}; - -/** Obtain function soft-state from DDF function node */ -static rootmalta_fun_t *rootmalta_fun(ddf_fun_t *fnode) -{ - return ddf_fun_data_get(fnode); -} - -static hw_resource_list_t *rootmalta_get_resources(ddf_fun_t *fnode) -{ - rootmalta_fun_t *fun = rootmalta_fun(fnode); - - assert(fun != NULL); - return &fun->hw_resources; -} - -static bool rootmalta_enable_interrupt(ddf_fun_t *fun) -{ - /* TODO */ - - return false; -} - -static pio_window_t *rootmalta_get_pio_window(ddf_fun_t *fnode) -{ - rootmalta_fun_t *fun = rootmalta_fun(fnode); - - assert(fun != NULL); - return &fun->pio_window; -} - -static hw_res_ops_t fun_hw_res_ops = { - .get_resource_list = &rootmalta_get_resources, - .enable_interrupt = &rootmalta_enable_interrupt, -}; - -static pio_window_ops_t fun_pio_window_ops = { - .get_pio_window = &rootmalta_get_pio_window -}; - -/* Initialized in root_malta_init() function. */ -static ddf_dev_ops_t rootmalta_fun_ops; - -static bool -rootmalta_add_fun(ddf_dev_t *dev, const char *name, const char *str_match_id, - rootmalta_fun_t *fun_proto) -{ - ddf_msg(LVL_DEBUG, "Adding new function '%s'.", name); - - ddf_fun_t *fnode = NULL; - int rc; - - /* Create new device. */ - fnode = ddf_fun_create(dev, fun_inner, name); - if (fnode == NULL) - goto failure; - - rootmalta_fun_t *fun = ddf_fun_data_alloc(fnode, sizeof(rootmalta_fun_t)); - *fun = *fun_proto; - - /* Add match ID */ - rc = ddf_fun_add_match_id(fnode, str_match_id, 100); - if (rc != EOK) - goto failure; - - /* Set provided operations to the device. */ - ddf_fun_set_ops(fnode, &rootmalta_fun_ops); - - /* Register function. */ - if (ddf_fun_bind(fnode) != EOK) { - ddf_msg(LVL_ERROR, "Failed binding function %s.", name); - goto failure; - } - - return true; - -failure: - if (fnode != NULL) - ddf_fun_destroy(fnode); - - ddf_msg(LVL_ERROR, "Failed adding function '%s'.", name); - - return false; -} - -static bool rootmalta_add_functions(ddf_dev_t *dev) -{ - return rootmalta_add_fun(dev, "pci0", "intel_pci", &pci_data); -} - -/** Get the root device. - * - * @param dev The device which is root of the whole device tree (both - * of HW and pseudo devices). - * @return Zero on success, negative error number otherwise. - */ -static int rootmalta_dev_add(ddf_dev_t *dev) -{ - ioport32_t *gt; - uint32_t val; - int ret; - - ddf_msg(LVL_DEBUG, "rootmalta_dev_add, device handle = %d", - (int)ddf_dev_get_handle(dev)); - - /* - * We need to disable byte swapping of the outgoing and incoming - * PCI data, because the PCI driver assumes no byte swapping behind - * the scenes and takes care of it itself. - */ - ret = pio_enable((void *) GT_BASE, GT_SIZE, (void **) >); - if (ret != EOK) - return ret; - val = uint32_t_le2host(pio_read_32( - >[GT_PCI_CMD / sizeof(ioport32_t)])); - val |= GT_PCI_CMD_MBYTESWAP; - pio_write_32( - >[GT_PCI_CMD / sizeof(ioport32_t)], host2uint32_t_le(val)); - - - /* Register functions. */ - if (!rootmalta_add_functions(dev)) { - ddf_msg(LVL_ERROR, "Failed to add functions for the Malta platform."); - } - - return EOK; -} - -static void root_malta_init(void) -{ - ddf_log_init(NAME); - rootmalta_fun_ops.interfaces[HW_RES_DEV_IFACE] = &fun_hw_res_ops; - rootmalta_fun_ops.interfaces[PIO_WINDOW_DEV_IFACE] = &fun_pio_window_ops; -} - -int main(int argc, char *argv[]) -{ - printf(NAME ": HelenOS Malta platform driver\n"); - root_malta_init(); - return ddf_driver_main(&rootmalta_driver); -} - -/** - * @} - */ Index: uspace/drv/infrastructure/rootmalta/rootmalta.ma =================================================================== --- uspace/drv/infrastructure/rootmalta/rootmalta.ma (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ (revision ) @@ -1,1 +1,0 @@ -10 platform/malta Index: uspace/drv/infrastructure/rootpc/Makefile =================================================================== --- uspace/drv/infrastructure/rootpc/Makefile (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ (revision ) @@ -1,37 +1,0 @@ -# -# Copyright (c) 2010 Lenka Trochtova -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# - Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# - Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# - The name of the author may not be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# - -USPACE_PREFIX = ../../.. -LIBS = $(LIBDRV_PREFIX)/libdrv.a -EXTRA_CFLAGS += -I$(LIBDRV_PREFIX)/include -BINARY = rootpc - -SOURCES = \ - rootpc.c - -include $(USPACE_PREFIX)/Makefile.common Index: uspace/drv/infrastructure/rootpc/rootpc.c =================================================================== --- uspace/drv/infrastructure/rootpc/rootpc.c (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ (revision ) @@ -1,236 +1,0 @@ -/* - * Copyright (c) 2010 Lenka Trochtova - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** - * @defgroup root_pc PC platform driver. - * @brief HelenOS PC platform driver. - * @{ - */ - -/** @file - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#define NAME "rootpc" - -typedef struct rootpc_fun { - hw_resource_list_t hw_resources; - pio_window_t pio_window; -} rootpc_fun_t; - -static int rootpc_dev_add(ddf_dev_t *dev); -static void root_pc_init(void); - -/** The root device driver's standard operations. */ -static driver_ops_t rootpc_ops = { - .dev_add = &rootpc_dev_add -}; - -/** The root device driver structure. */ -static driver_t rootpc_driver = { - .name = NAME, - .driver_ops = &rootpc_ops -}; - -static hw_resource_t pci_conf_regs[] = { - { - .type = IO_RANGE, - .res.io_range = { - .address = 0xCF8, - .size = 4, - .relative = false, - .endianness = LITTLE_ENDIAN - } - }, - { - .type = IO_RANGE, - .res.io_range = { - .address = 0xCFC, - .size = 4, - .relative = false, - .endianness = LITTLE_ENDIAN - } - } -}; - -static rootpc_fun_t pci_data = { - .hw_resources = { - sizeof(pci_conf_regs) / sizeof(pci_conf_regs[0]), - pci_conf_regs - }, - .pio_window = { - .mem = { - .base = UINT32_C(0), - .size = UINT32_C(0xffffffff) /* practical maximum */ - }, - .io = { - .base = UINT32_C(0), - .size = UINT32_C(0x10000) - } - } -}; - -/** Obtain function soft-state from DDF function node */ -static rootpc_fun_t *rootpc_fun(ddf_fun_t *fnode) -{ - return ddf_fun_data_get(fnode); -} - -static hw_resource_list_t *rootpc_get_resources(ddf_fun_t *fnode) -{ - rootpc_fun_t *fun = rootpc_fun(fnode); - - assert(fun != NULL); - return &fun->hw_resources; -} - -static bool rootpc_enable_interrupt(ddf_fun_t *fun) -{ - /* TODO */ - - return false; -} - -static pio_window_t *rootpc_get_pio_window(ddf_fun_t *fnode) -{ - rootpc_fun_t *fun = rootpc_fun(fnode); - - assert(fun != NULL); - return &fun->pio_window; -} - -static hw_res_ops_t fun_hw_res_ops = { - .get_resource_list = &rootpc_get_resources, - .enable_interrupt = &rootpc_enable_interrupt, -}; - -static pio_window_ops_t fun_pio_window_ops = { - .get_pio_window = &rootpc_get_pio_window -}; - -/* Initialized in root_pc_init() function. */ -static ddf_dev_ops_t rootpc_fun_ops; - -static bool -rootpc_add_fun(ddf_dev_t *dev, const char *name, const char *str_match_id, - rootpc_fun_t *fun_proto) -{ - ddf_msg(LVL_DEBUG, "Adding new function '%s'.", name); - - ddf_fun_t *fnode = NULL; - int rc; - - /* Create new device. */ - fnode = ddf_fun_create(dev, fun_inner, name); - if (fnode == NULL) - goto failure; - - rootpc_fun_t *fun = ddf_fun_data_alloc(fnode, sizeof(rootpc_fun_t)); - *fun = *fun_proto; - - /* Add match ID */ - rc = ddf_fun_add_match_id(fnode, str_match_id, 100); - if (rc != EOK) - goto failure; - - /* Set provided operations to the device. */ - ddf_fun_set_ops(fnode, &rootpc_fun_ops); - - /* Register function. */ - if (ddf_fun_bind(fnode) != EOK) { - ddf_msg(LVL_ERROR, "Failed binding function %s.", name); - goto failure; - } - - return true; - -failure: - if (fnode != NULL) - ddf_fun_destroy(fnode); - - ddf_msg(LVL_ERROR, "Failed adding function '%s'.", name); - - return false; -} - -static bool rootpc_add_functions(ddf_dev_t *dev) -{ - return rootpc_add_fun(dev, "pci0", "intel_pci", &pci_data); -} - -/** Get the root device. - * - * @param dev The device which is root of the whole device tree (both - * of HW and pseudo devices). - * @return Zero on success, negative error number otherwise. - */ -static int rootpc_dev_add(ddf_dev_t *dev) -{ - ddf_msg(LVL_DEBUG, "rootpc_dev_add, device handle = %d", - (int)ddf_dev_get_handle(dev)); - - /* Register functions. */ - if (!rootpc_add_functions(dev)) { - ddf_msg(LVL_ERROR, "Failed to add functions for PC platform."); - } - - return EOK; -} - -static void root_pc_init(void) -{ - ddf_log_init(NAME); - rootpc_fun_ops.interfaces[HW_RES_DEV_IFACE] = &fun_hw_res_ops; - rootpc_fun_ops.interfaces[PIO_WINDOW_DEV_IFACE] = &fun_pio_window_ops; -} - -int main(int argc, char *argv[]) -{ - printf(NAME ": HelenOS PC platform driver\n"); - root_pc_init(); - return ddf_driver_main(&rootpc_driver); -} - -/** - * @} - */ Index: uspace/drv/infrastructure/rootpc/rootpc.ma =================================================================== --- uspace/drv/infrastructure/rootpc/rootpc.ma (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ (revision ) @@ -1,1 +1,0 @@ -10 platform/pc Index: uspace/drv/infrastructure/rootvirt/Makefile =================================================================== --- uspace/drv/infrastructure/rootvirt/Makefile (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ (revision ) @@ -1,37 +1,0 @@ -# -# Copyright (c) 2010 Vojtech Horky -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# - Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# - Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# - The name of the author may not be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# - -USPACE_PREFIX = ../../.. -LIBS = $(LIBDRV_PREFIX)/libdrv.a -EXTRA_CFLAGS += -I$(LIBDRV_PREFIX)/include -BINARY = rootvirt - -SOURCES = \ - rootvirt.c - -include $(USPACE_PREFIX)/Makefile.common Index: uspace/drv/infrastructure/rootvirt/devices.def =================================================================== --- uspace/drv/infrastructure/rootvirt/devices.def (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ (revision ) @@ -1,46 +1,0 @@ -/* - * Add list of virtual devices you want to launch driver for here. - * - * Unless the list is empty, the last item shall be followed by a comma. - */ - -/* Kernel framebuffer */ -{ - .name = "kfb", - .match_id = "virtual&kfb" -}, - -#ifdef CONFIG_TEST_DRIVERS - -{ - .name = "test1", - .match_id = "virtual&test1" -}, -{ - .name = "test2alpha", - .match_id = "virtual&test2" -}, -{ - .name = "test2bravo", - .match_id = "virtual&test2" -}, -{ - .name = "null", - .match_id = "virtual&test1" -}, -{ - .name = "test3", - .match_id = "virtual&test3" -}, - -#endif - -#ifdef CONFIG_RUN_VIRTUAL_USB_HC - -/* Virtual USB host controller. */ -{ - .name = "usbhc", - .match_id = "usb&hc=vhc" -}, - -#endif Index: uspace/drv/infrastructure/rootvirt/rootvirt.c =================================================================== --- uspace/drv/infrastructure/rootvirt/rootvirt.c (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ (revision ) @@ -1,249 +1,0 @@ -/* - * Copyright (c) 2010 Vojtech Horky - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** - * @defgroup rootvirt Root device driver for virtual devices. - * @{ - */ - -/** @file - */ - -#include -#include -#include -#include -#include -#include - -#define NAME "rootvirt" - -/** Virtual function entry */ -typedef struct { - /** Function name */ - const char *name; - /** Function match ID */ - const char *match_id; -} virtual_function_t; - -/** List of existing virtual functions */ -virtual_function_t virtual_functions[] = { -#include "devices.def" - /* Terminating item */ - { - .name = NULL, - .match_id = NULL - } -}; - -static int rootvirt_dev_add(ddf_dev_t *dev); -static int rootvirt_dev_remove(ddf_dev_t *dev); -static int rootvirt_fun_online(ddf_fun_t *fun); -static int rootvirt_fun_offline(ddf_fun_t *fun); - -static driver_ops_t rootvirt_ops = { - .dev_add = &rootvirt_dev_add, - .dev_remove = &rootvirt_dev_remove, - .fun_online = &rootvirt_fun_online, - .fun_offline = &rootvirt_fun_offline -}; - -static driver_t rootvirt_driver = { - .name = NAME, - .driver_ops = &rootvirt_ops -}; - -/* Device soft state */ -typedef struct { - ddf_dev_t *dev; - list_t functions; -} rootvirt_t; - -/* Function soft state */ -typedef struct { - ddf_fun_t *fun; - link_t dev_link; -} rootvirt_fun_t; - -static int instances = 0; - - -/** Add function to the virtual device. - * - * @param vdev The virtual device - * @param vfun Virtual function description - * @return EOK on success or negative error code. - */ -static int rootvirt_add_fun(rootvirt_t *rootvirt, virtual_function_t *vfun) -{ - ddf_dev_t *vdev = rootvirt->dev; - ddf_fun_t *fun; - rootvirt_fun_t *rvfun; - int rc; - - ddf_msg(LVL_DEBUG, "Registering function `%s' (match \"%s\")", - vfun->name, vfun->match_id); - - fun = ddf_fun_create(vdev, fun_inner, vfun->name); - if (fun == NULL) { - ddf_msg(LVL_ERROR, "Failed creating function %s", vfun->name); - return ENOMEM; - } - - rvfun = ddf_fun_data_alloc(fun, sizeof(rootvirt_fun_t)); - if (rvfun == NULL) { - ddf_msg(LVL_ERROR, "Failed allocating soft state for %s.", - vfun->name); - ddf_fun_destroy(fun); - return ENOMEM; - } - - rvfun->fun = fun; - - rc = ddf_fun_add_match_id(fun, vfun->match_id, 10); - if (rc != EOK) { - ddf_msg(LVL_ERROR, "Failed adding match IDs to function %s", - vfun->name); - ddf_fun_destroy(fun); - return rc; - } - - rc = ddf_fun_bind(fun); - if (rc != EOK) { - ddf_msg(LVL_ERROR, "Failed binding function %s: %s", - vfun->name, str_error(rc)); - ddf_fun_destroy(fun); - return rc; - } - - list_append(&rvfun->dev_link, &rootvirt->functions); - - ddf_msg(LVL_NOTE, "Registered child device `%s'", vfun->name); - return EOK; -} - -static int rootvirt_fun_remove(rootvirt_fun_t *rvfun) -{ - int rc; - const char *name = ddf_fun_get_name(rvfun->fun); - - ddf_msg(LVL_DEBUG, "rootvirt_fun_remove('%s')", name); - rc = ddf_fun_offline(rvfun->fun); - if (rc != EOK) { - ddf_msg(LVL_ERROR, "Error offlining function '%s'.", name); - return rc; - } - - rc = ddf_fun_unbind(rvfun->fun); - if (rc != EOK) { - ddf_msg(LVL_ERROR, "Failed unbinding function '%s'.", name); - return rc; - } - - list_remove(&rvfun->dev_link); - ddf_fun_destroy(rvfun->fun); - return EOK; -} - - -static int rootvirt_dev_add(ddf_dev_t *dev) -{ - rootvirt_t *rootvirt; - - /* - * Allow only single instance of root virtual device. - */ - if (++instances > 1) { - return ELIMIT; - } - - ddf_msg(LVL_DEBUG, "dev_add(handle=%d)", (int)ddf_dev_get_handle(dev)); - - rootvirt = ddf_dev_data_alloc(dev, sizeof(rootvirt_t)); - if (rootvirt == NULL) - return ENOMEM; - - rootvirt->dev = dev; - list_initialize(&rootvirt->functions); - - /* - * Go through all virtual functions and try to add them. - * We silently ignore failures. - */ - virtual_function_t *vfun = virtual_functions; - while (vfun->name != NULL) { - (void) rootvirt_add_fun(rootvirt, vfun); - vfun++; - } - - return EOK; -} - -static int rootvirt_dev_remove(ddf_dev_t *dev) -{ - rootvirt_t *rootvirt = (rootvirt_t *)ddf_dev_data_get(dev); - int rc; - - while (!list_empty(&rootvirt->functions)) { - rootvirt_fun_t *rvfun = list_get_instance( - list_first(&rootvirt->functions), rootvirt_fun_t, - dev_link); - - rc = rootvirt_fun_remove(rvfun); - if (rc != EOK) - return rc; - } - - --instances; - return EOK; -} - -static int rootvirt_fun_online(ddf_fun_t *fun) -{ - ddf_msg(LVL_DEBUG, "rootvirt_fun_online()"); - return ddf_fun_online(fun); -} - -static int rootvirt_fun_offline(ddf_fun_t *fun) -{ - ddf_msg(LVL_DEBUG, "rootvirt_fun_offline()"); - return ddf_fun_offline(fun); -} - -int main(int argc, char *argv[]) -{ - printf(NAME ": HelenOS virtual devices root driver\n"); - - ddf_log_init(NAME); - return ddf_driver_main(&rootvirt_driver); -} - -/** - * @} - */ - Index: uspace/drv/infrastructure/rootvirt/rootvirt.ma =================================================================== --- uspace/drv/infrastructure/rootvirt/rootvirt.ma (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ (revision ) @@ -1,1 +1,0 @@ -10 rootvirt Index: uspace/drv/nic/e1k/e1k.c =================================================================== --- uspace/drv/nic/e1k/e1k.c (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ uspace/drv/nic/e1k/e1k.c (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -1229,11 +1229,11 @@ /** Handle device interrupt * - * @param dev E1000 device * @param iid IPC call id * @param icall IPC call structure - * - */ -static void e1000_interrupt_handler(ddf_dev_t *dev, ipc_callid_t iid, - ipc_call_t *icall) + * @param dev E1000 device + * + */ +static void e1000_interrupt_handler(ipc_callid_t iid, ipc_call_t *icall, + ddf_dev_t *dev) { uint32_t icr = (uint32_t) IPC_GET_ARG2(*icall); Index: uspace/drv/nic/ne2k/ne2k.c =================================================================== --- uspace/drv/nic/ne2k/ne2k.c (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ uspace/drv/nic/ne2k/ne2k.c (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -122,6 +122,5 @@ }; -static void ne2k_interrupt_handler(ddf_dev_t *dev, ipc_callid_t iid, - ipc_call_t *call); +static void ne2k_interrupt_handler(ipc_callid_t, ipc_call_t *, ddf_dev_t *); static int ne2k_register_interrupt(nic_t *nic_data) @@ -240,9 +239,9 @@ } -void ne2k_interrupt_handler(ddf_dev_t *dev, ipc_callid_t iid, ipc_call_t *call) +void ne2k_interrupt_handler(ipc_callid_t iid, ipc_call_t *call, ddf_dev_t *dev) { nic_t *nic_data = DRIVER_DATA(dev); ne2k_interrupt(nic_data, IRQ_GET_ISR(*call), IRQ_GET_TSR(*call)); - + async_answer_0(iid, EOK); } Index: uspace/drv/nic/rtl8139/driver.c =================================================================== --- uspace/drv/nic/rtl8139/driver.c (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ uspace/drv/nic/rtl8139/driver.c (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -852,10 +852,11 @@ /** Handle device interrupt * - * @param dev The rtl8139 device - * @param iid The IPC call id - * @param icall The IPC call structure - */ -static void rtl8139_interrupt_handler(ddf_dev_t *dev, ipc_callid_t iid, - ipc_call_t *icall) + * @param iid The IPC call id + * @param icall The IPC call structure + * @param dev The rtl8139 device + * + */ +static void rtl8139_interrupt_handler(ipc_callid_t iid, ipc_call_t *icall, + ddf_dev_t *dev) { assert(dev); Index: uspace/drv/nic/rtl8169/driver.c =================================================================== --- uspace/drv/nic/rtl8169/driver.c (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ uspace/drv/nic/rtl8169/driver.c (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -27,6 +27,4 @@ */ -#define _DDF_DATA_IMPLANT - #include #include @@ -76,6 +74,6 @@ static int rtl8169_on_stopped(nic_t *nic_data); static void rtl8169_send_frame(nic_t *nic_data, void *data, size_t size); -static void rtl8169_irq_handler(ddf_dev_t *dev, ipc_callid_t iid, - ipc_call_t *icall); +static void rtl8169_irq_handler(ipc_callid_t iid, ipc_call_t *icall, + ddf_dev_t *dev); static inline int rtl8169_register_int_handler(nic_t *nic_data); static inline void rtl8169_get_hwaddr(rtl8169_t *rtl8169, nic_address_t *addr); @@ -330,4 +328,12 @@ } +static void rtl8169_dev_cleanup(ddf_dev_t *dev) +{ + assert(dev); + + if (ddf_dev_data_get(dev)) + nic_unbind_and_destroy(dev); +} + static int rtl8169_dev_initialize(ddf_dev_t *dev) { @@ -351,5 +357,5 @@ failed: ddf_msg(LVL_ERROR, "The device initialization failed"); -// rtl8139_dev_cleanup(dev); + rtl8169_dev_cleanup(dev); return ret; @@ -439,5 +445,4 @@ nic_set_ddf_fun(nic_data, fun); ddf_fun_set_ops(fun, &rtl8169_dev_ops); -// ddf_fun_data_implant(fun, nic_data); rc = ddf_fun_bind(fun); @@ -467,5 +472,5 @@ err_pio: err_destroy: - //rtl8169_dev_cleanup(dev); + rtl8169_dev_cleanup(dev); return rc; @@ -733,12 +738,8 @@ /* Configure Receive Control Register */ uint32_t rcr = pio_read_32(rtl8169->regs + RCR); - rcr |= RCR_ACCEPT_ALL_PHYS | RCR_ACCEPT_PHYS_MATCH \ - | RCR_ACCEPT_BROADCAST | RCR_ACCEPT_ERROR \ - | RCR_ACCEPT_RUNT; + rtl8169->rcr_ucast = RCR_ACCEPT_PHYS_MATCH; + rcr |= RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_ERROR | RCR_ACCEPT_RUNT; pio_write_32(rtl8169->regs + RCR, rcr); pio_write_16(rtl8169->regs + RMS, BUFFER_SIZE); - - ddf_msg(LVL_NOTE, "RCR: 0x%08x", pio_read_32(rtl8169->regs + RCR)); - pio_write_16(rtl8169->regs + IMR, 0xffff); @@ -793,7 +794,74 @@ } +/** Notify NIC framework about HW filtering state when promisc mode was disabled + * + * @param nic_data The NIC data + * @param mcast_mode Current multicast mode + * @param was_promisc Sign if the promiscuous mode was active before disabling + */ +inline static void rtl8169_rcx_promics_rem(nic_t *nic_data, + nic_multicast_mode_t mcast_mode, uint8_t was_promisc) +{ + assert(nic_data); + + if (was_promisc != 0) { + if (mcast_mode == NIC_MULTICAST_LIST) + nic_report_hw_filtering(nic_data, 1, 0, -1); + else + nic_report_hw_filtering(nic_data, 1, 1, -1); + } else { + nic_report_hw_filtering(nic_data, 1, -1, -1); + } +} + static int rtl8169_unicast_set(nic_t *nic_data, nic_unicast_mode_t mode, const nic_address_t *addr, size_t addr_count) { + rtl8169_t *rtl8169 = nic_get_specific(nic_data); + uint32_t rcr = pio_read_32(rtl8169->regs + RCR); + uint8_t was_promisc = rcr & RCR_ACCEPT_ALL_PHYS; + nic_multicast_mode_t mcast_mode; + + nic_query_multicast(nic_data, &mcast_mode, 0, NULL, NULL); + + ddf_msg(LVL_DEBUG, "Unicast RX filter mode: %d", mode); + + + switch (mode) { + case NIC_UNICAST_BLOCKED: + rtl8169->rcr_ucast = 0; + rtl8169_rcx_promics_rem(nic_data, mcast_mode, was_promisc); + break; + case NIC_UNICAST_DEFAULT: + rtl8169->rcr_ucast = RCR_ACCEPT_PHYS_MATCH; + rtl8169_rcx_promics_rem(nic_data, mcast_mode, was_promisc); + break; + case NIC_UNICAST_LIST: + rtl8169->rcr_ucast = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_ALL_PHYS; + + if (mcast_mode == NIC_MULTICAST_PROMISC) + nic_report_hw_filtering(nic_data, 0, 1, -1); + else + nic_report_hw_filtering(nic_data, 0, 0, -1); + break; + case NIC_UNICAST_PROMISC: + rtl8169->rcr_ucast = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_ALL_PHYS; + + if (mcast_mode == NIC_MULTICAST_PROMISC) + nic_report_hw_filtering(nic_data, 1, 1, -1); + else + nic_report_hw_filtering(nic_data, 1, 0, -1); + break; + default: + return ENOTSUP; + } + + fibril_mutex_lock(&rtl8169->rx_lock); + + rcr &= ~(RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_ALL_PHYS); + pio_write_32(rtl8169->regs + RCR, rcr | rtl8169->rcr_ucast | rtl8169->rcr_mcast); + ddf_msg(LVL_DEBUG, "new RCR value: 0x%08x", rcr | rtl8169->rcr_ucast | rtl8169->rcr_mcast); + + fibril_mutex_unlock(&rtl8169->rx_lock); return EOK; } @@ -802,4 +870,42 @@ const nic_address_t *addr, size_t addr_count) { + rtl8169_t *rtl8169 = nic_get_specific(nic_data); + uint32_t rcr = pio_read_32(rtl8169->regs + RCR); + uint64_t mask; + + ddf_msg(LVL_DEBUG, "Multicast RX filter mode: %d", mode); + + switch (mode) { + case NIC_MULTICAST_BLOCKED: + rtl8169->rcr_mcast = 0; + if ((rtl8169->rcr_ucast & RCR_ACCEPT_ALL_PHYS) != 0) + nic_report_hw_filtering(nic_data, -1, 0, -1); + else + nic_report_hw_filtering(nic_data, -1, 1, -1); + break; + case NIC_MULTICAST_LIST: + mask = nic_mcast_hash(addr, addr_count); + pio_write_32(rtl8169->regs + MAR0, (uint32_t)mask); + pio_write_32(rtl8169->regs + MAR0 + 4, (uint32_t)(mask >> 32)); + rtl8169->rcr_mcast = RCR_ACCEPT_MULTICAST; + nic_report_hw_filtering(nic_data, -1, 0, -1); + break; + case NIC_MULTICAST_PROMISC: + pio_write_32(rtl8169->regs + MAR0, 0xffffffffULL); + pio_write_32(rtl8169->regs + MAR0 + 4, (uint32_t)(0xffffffffULL >> 32)); + rtl8169->rcr_mcast = RCR_ACCEPT_MULTICAST; + nic_report_hw_filtering(nic_data, -1, 1, -1); + break; + default: + return ENOTSUP; + } + + fibril_mutex_lock(&rtl8169->rx_lock); + + rcr &= ~(RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_ALL_PHYS); + pio_write_32(rtl8169->regs + RCR, rcr | rtl8169->rcr_ucast | rtl8169->rcr_mcast); + ddf_msg(LVL_DEBUG, "new RCR value: 0x%08x", rcr | rtl8169->rcr_ucast | rtl8169->rcr_mcast); + + fibril_mutex_unlock(&rtl8169->rx_lock); return EOK; } @@ -807,4 +913,25 @@ static int rtl8169_broadcast_set(nic_t *nic_data, nic_broadcast_mode_t mode) { + rtl8169_t *rtl8169 = nic_get_specific(nic_data); + + /* Configure Receive Control Register */ + uint32_t rcr = pio_read_32(rtl8169->regs + RCR); + + ddf_msg(LVL_DEBUG, "Broadcast RX filter mode: %d", mode); + + switch (mode) { + case NIC_BROADCAST_BLOCKED: + rcr &= ~RCR_ACCEPT_BROADCAST; + break; + case NIC_BROADCAST_ACCEPTED: + rcr |= RCR_ACCEPT_BROADCAST; + break; + default: + return ENOTSUP; + } + + pio_write_32(rtl8169->regs + RCR, rcr); + ddf_msg(LVL_DEBUG," new RCR value: 0x%08x", rcr); + return EOK; } @@ -816,6 +943,7 @@ rtl8169_t *rtl8169 = nic_get_specific(nic_data); rtl8169_descr_t *descr; - - ddf_msg(LVL_NOTE, "rtl8169_transmit_done()"); + int sent = 0; + + ddf_msg(LVL_DEBUG, "rtl8169_transmit_done()"); fibril_mutex_lock(&rtl8169->tx_lock); @@ -828,8 +956,12 @@ descr->control &= (~CONTROL_OWN); write_barrier(); - ddf_msg(LVL_NOTE, "TX status for descr %d: 0x%08x", tail, descr->control); + ddf_msg(LVL_DEBUG, "TX status for descr %d: 0x%08x", tail, descr->control); tail = (tail + 1) % TX_BUFFERS_COUNT; - } + sent++; + } + + if (sent != 0) + nic_set_tx_busy(nic_data, 0); rtl8169->tx_tail = tail; @@ -849,5 +981,5 @@ int frame_size; - ddf_msg(LVL_NOTE, "rtl8169_receive_done()"); + ddf_msg(LVL_DEBUG, "rtl8169_receive_done()"); fibril_mutex_lock(&rtl8169->rx_lock); @@ -862,5 +994,5 @@ if (descr->control & RXSTATUS_RES) { - ddf_msg(LVL_NOTE, "error at slot %d: 0x%08x\n", tail, descr->control); + ddf_msg(LVL_WARN, "error at slot %d: 0x%08x\n", tail, descr->control); tail = (tail + 1) % RX_BUFFERS_COUNT; continue; @@ -871,6 +1003,5 @@ if (descr->control & CONTROL_LS) { - - ddf_msg(LVL_NOTE, "received message at slot %d, control 0x%08x", tail, descr->control); + ddf_msg(LVL_DEBUG, "received message at slot %d, control 0x%08x", tail, descr->control); if (fsidx != tail) @@ -897,6 +1028,6 @@ } -static void rtl8169_irq_handler(ddf_dev_t *dev, ipc_callid_t iid, - ipc_call_t *icall) +static void rtl8169_irq_handler(ipc_callid_t iid, ipc_call_t *icall, + ddf_dev_t *dev) { assert(dev); @@ -907,5 +1038,5 @@ rtl8169_t *rtl8169 = nic_get_specific(nic_data); - ddf_msg(LVL_NOTE, "rtl8169_irq_handler(): isr=0x%04x", isr); + ddf_msg(LVL_DEBUG, "rtl8169_irq_handler(): isr=0x%04x", isr); pio_write_16(rtl8169->regs + IMR, 0xffff); @@ -963,5 +1094,5 @@ fibril_mutex_lock(&rtl8169->tx_lock); - ddf_msg(LVL_NOTE, "send_frame: size: %zu, tx_head=%d tx_tail=%d", + ddf_msg(LVL_DEBUG, "send_frame: size: %zu, tx_head=%d tx_tail=%d", size, rtl8169->tx_head, rtl8169->tx_tail); @@ -986,5 +1117,5 @@ prev = &rtl8169->tx_ring[(head - 1) % TX_BUFFERS_COUNT]; - ddf_msg(LVL_NOTE, "current_descr=%p, prev_descr=%p", descr, prev); + ddf_msg(LVL_DEBUG, "current_descr=%p, prev_descr=%p", descr, prev); descr->control = CONTROL_OWN | CONTROL_FS | CONTROL_LS; Index: uspace/drv/nic/rtl8169/driver.h =================================================================== --- uspace/drv/nic/rtl8169/driver.h (revision de16f892e37393d27d9d32f487cc511dc31bbd38) +++ uspace/drv/nic/rtl8169/driver.h (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -86,4 +86,8 @@ size_t tx_used; + /** Receive Control Register masks */ + uint32_t rcr_ucast; + uint32_t rcr_mcast; + /** Lock for receiver */ fibril_mutex_t rx_lock; Index: uspace/drv/platform/amdm37x/Makefile =================================================================== --- uspace/drv/platform/amdm37x/Makefile (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) +++ uspace/drv/platform/amdm37x/Makefile (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -0,0 +1,38 @@ +# +# Copyright (c) 2012 Jan Vesely +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# - Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# - Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# - The name of the author may not be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +USPACE_PREFIX = ../../.. +LIBS = $(LIBDRV_PREFIX)/libdrv.a +EXTRA_CFLAGS += -I$(LIBDRV_PREFIX)/include +BINARY = amdm37x + +SOURCES = \ + amdm37x.c \ + main.c + +include $(USPACE_PREFIX)/Makefile.common Index: uspace/drv/platform/amdm37x/amdm37x.c =================================================================== --- uspace/drv/platform/amdm37x/amdm37x.c (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) +++ uspace/drv/platform/amdm37x/amdm37x.c (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -0,0 +1,404 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @defgroup amdm37x TI AM/DM37x platform driver. + * @brief HelenOS TI AM/DM37x platform driver. + * @{ + */ + +/** @file + */ + +#include "amdm37x.h" + +#include +#include +#include +#include +#include + +static void log(const volatile void *place, uint32_t val, volatile void* base, size_t size, void *data, bool write) +{ + printf("PIO %s: %p(%p) %#"PRIx32"\n", write ? "WRITE" : "READ", + (place - base) + data, place, val); +} + + +int amdm37x_init(amdm37x_t *device, bool trace) +{ + assert(device); + int ret = EOK; + + ret = pio_enable((void*)USBHOST_CM_BASE_ADDRESS, USBHOST_CM_SIZE, + (void**)&device->cm.usbhost); + if (ret != EOK) + return ret; + + ret = pio_enable((void*)CORE_CM_BASE_ADDRESS, CORE_CM_SIZE, + (void**)&device->cm.core); + if (ret != EOK) + return ret; + + ret = pio_enable((void*)CLOCK_CONTROL_CM_BASE_ADDRESS, + CLOCK_CONTROL_CM_SIZE, (void**)&device->cm.clocks); + if (ret != EOK) + return ret; + + ret = pio_enable((void*)MPU_CM_BASE_ADDRESS, + MPU_CM_SIZE, (void**)&device->cm.mpu); + if (ret != EOK) + return ret; + + ret = pio_enable((void*)IVA2_CM_BASE_ADDRESS, + IVA2_CM_SIZE, (void**)&device->cm.iva2); + if (ret != EOK) + return ret; + + ret = pio_enable((void*)CLOCK_CONTROL_PRM_BASE_ADDRESS, + CLOCK_CONTROL_PRM_SIZE, (void**)&device->prm.clocks); + if (ret != EOK) + return ret; + + ret = pio_enable((void*)GLOBAL_REG_PRM_BASE_ADDRESS, + GLOBAL_REG_PRM_SIZE, (void**)&device->prm.global); + if (ret != EOK) + return ret; + + ret = pio_enable((void*)AMDM37x_USBTLL_BASE_ADDRESS, + AMDM37x_USBTLL_SIZE, (void**)&device->tll); + if (ret != EOK) + return ret; + + ret = pio_enable((void*)AMDM37x_UHH_BASE_ADDRESS, + AMDM37x_UHH_SIZE, (void**)&device->uhh); + if (ret != EOK) + return ret; + + if (trace) { + pio_trace_enable(device->tll, AMDM37x_USBTLL_SIZE, log, (void*)AMDM37x_USBTLL_BASE_ADDRESS); + pio_trace_enable(device->cm.clocks, CLOCK_CONTROL_CM_SIZE, log, (void*)CLOCK_CONTROL_CM_BASE_ADDRESS); + pio_trace_enable(device->cm.core, CORE_CM_SIZE, log, (void*)CORE_CM_BASE_ADDRESS); + pio_trace_enable(device->cm.mpu, MPU_CM_SIZE, log, (void*)MPU_CM_BASE_ADDRESS); + pio_trace_enable(device->cm.iva2, IVA2_CM_SIZE, log, (void*)IVA2_CM_BASE_ADDRESS); + pio_trace_enable(device->cm.usbhost, USBHOST_CM_SIZE, log, (void*)USBHOST_CM_BASE_ADDRESS); + pio_trace_enable(device->uhh, AMDM37x_UHH_SIZE, log, (void*)AMDM37x_UHH_BASE_ADDRESS); + pio_trace_enable(device->prm.clocks, CLOCK_CONTROL_PRM_SIZE, log, (void*)CLOCK_CONTROL_PRM_BASE_ADDRESS); + pio_trace_enable(device->prm.global, GLOBAL_REG_PRM_SIZE, log, (void*)GLOBAL_REG_PRM_BASE_ADDRESS); + } + return EOK; +} + + +/** Set DPLLs 1,2,3,4,5 to ON (locked) and autoidle. + * @param device Register map. + * + * The idea is to get all DPLLs running and make hw control their power mode, + * based on the module requirements (module ICLKs and FCLKs). + */ +void amdm37x_setup_dpll_on_autoidle(amdm37x_t *device) +{ + assert(device); + /* Get SYS_CLK value, it is used as reference clock by all DPLLs, + * NFI who sets this or why it is set to specific value. */ + const unsigned osc_clk = pio_read_32(&device->prm.clocks->clksel) + & CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_MASK; + const unsigned clk_reg = pio_read_32(&device->prm.global->clksrc_ctrl); + const unsigned base_freq = sys_clk_freq_kHz(osc_clk) + / GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKDIV_GET(clk_reg); + ddf_msg(LVL_NOTE, "Base frequency: %d.%dMhz", + base_freq / 1000, base_freq % 1000); + + + /* DPLL1 provides MPU(CPU) clock. + * It uses SYS_CLK as reference clock and core clock (DPLL3) as + * high frequency bypass (MPU then runs on L3 interconnect freq). + * It should be setup by fw or u-boot.*/ + mpu_cm_regs_t *mpu = device->cm.mpu; + + /* Current MPU frequency. */ + if (pio_read_32(&mpu->clkstst) & MPU_CM_CLKSTST_CLKACTIVITY_MPU_ACTIVE_FLAG) { + if (pio_read_32(&mpu->idlest_pll) & MPU_CM_IDLEST_PLL_ST_MPU_CLK_LOCKED_FLAG) { + /* DPLL active and locked */ + const uint32_t reg = pio_read_32(&mpu->clksel1_pll); + const unsigned multiplier = + (reg & MPU_CM_CLKSEL1_PLL_MPU_DPLL_MULT_MASK) + >> MPU_CM_CLKSEL1_PLL_MPU_DPLL_MULT_SHIFT; + const unsigned divisor = + (reg & MPU_CM_CLKSEL1_PLL_MPU_DPLL_DIV_MASK) + >> MPU_CM_CLKSEL1_PLL_MPU_DPLL_DIV_SHIFT; + const unsigned divisor2 = + (pio_read_32(&mpu->clksel2_pll) + & MPU_CM_CLKSEL2_PLL_MPU_DPLL_CLKOUT_DIV_MASK); + if (multiplier && divisor && divisor2) { + /** See AMDM37x TRM p. 300 for the formula */ + const unsigned freq = + ((base_freq * multiplier) / (divisor + 1)) + / divisor2; + ddf_msg(LVL_NOTE, "MPU running at %d.%d MHz", + freq / 1000, freq % 1000); + } else { + ddf_msg(LVL_WARN, "Frequency divisor and/or " + "multiplier value invalid: %d %d %d", + multiplier, divisor, divisor2); + } + } else { + /* DPLL in LP bypass mode */ + const unsigned divisor = + MPU_CM_CLKSEL1_PLL_MPU_CLK_SRC_VAL( + pio_read_32(&mpu->clksel1_pll)); + ddf_msg(LVL_NOTE, "MPU DPLL in bypass mode, running at" + " CORE CLK / %d MHz", divisor); + } + } else { + ddf_msg(LVL_WARN, "MPU clock domain is not active, we should not be running..."); + } + // TODO: Enable this (automatic MPU downclocking): +#if 0 + /* Enable low power bypass mode, this will take effect the next lock or + * relock sequence. */ + //TODO: We might need to force re-lock after enabling this + pio_set_32(&mpu->clken_pll, MPU_CM_CLKEN_PLL_EN_MPU_DPLL_LP_MODE_FLAG, 5); + /* Enable automatic relocking */ + pio_change_32(&mpu->autoidle_pll, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_ENABLED, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_MASK, 5); +#endif + + /* DPLL2 provides IVA(video acceleration) clock. + * It uses SYS_CLK as reference clokc and core clock (DPLL3) as + * high frequency bypass (IVA runs on L3 freq). + */ + // TODO: We can probably turn this off entirely. IVA is left unused. + /* Enable low power bypass mode, this will take effect the next lock or + * relock sequence. */ + //TODO: We might need to force re-lock after enabling this + pio_set_32(&device->cm.iva2->clken_pll, MPU_CM_CLKEN_PLL_EN_MPU_DPLL_LP_MODE_FLAG, 5); + /* Enable automatic relocking */ + pio_change_32(&device->cm.iva2->autoidle_pll, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_ENABLED, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_MASK, 5); + + /* DPLL3 provides tons of clocks: + * CORE_CLK, COREX2_CLK, DSS_TV_CLK, 12M_CLK, 48M_CLK, 96M_CLK, L3_ICLK, + * and L4_ICLK. It uses SYS_CLK as reference clock and low frequency + * bypass. It should be setup by fw or u-boot as it controls critical + * interconnects. + */ + if (pio_read_32(&device->cm.clocks->idlest_ckgen) & CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_CORE_CLK_FLAG) { + /* DPLL active and locked */ + const uint32_t reg = + pio_read_32(&device->cm.clocks->clksel1_pll); + const unsigned multiplier = + CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_MULT_GET(reg); + const unsigned divisor = + CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_DIV_GET(reg); + const unsigned divisor2 = + CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_CLKOUT_DIV_GET(reg); + if (multiplier && divisor && divisor2) { + /** See AMDM37x TRM p. 300 for the formula */ + const unsigned freq = + ((base_freq * multiplier) / (divisor + 1)) / divisor2; + ddf_msg(LVL_NOTE, "CORE CLK running at %d.%d MHz", + freq / 1000, freq % 1000); + const unsigned l3_div = + pio_read_32(&device->cm.core->clksel) + & CORE_CM_CLKSEL_CLKSEL_L3_MASK; + if (l3_div == CORE_CM_CLKSEL_CLKSEL_L3_DIVIDED1 || + l3_div == CORE_CM_CLKSEL_CLKSEL_L3_DIVIDED2) { + ddf_msg(LVL_NOTE, "L3 interface at %d.%d MHz", + (freq / l3_div) / 1000, + (freq / l3_div) % 1000); + } else { + ddf_msg(LVL_WARN,"L3 interface clock divisor is" + " invalid: %d", l3_div); + } + } else { + ddf_msg(LVL_WARN, "DPLL3 frequency divisor and/or " + "multiplier value invalid: %d %d %d", + multiplier, divisor, divisor2); + } + } else { + ddf_msg(LVL_WARN, "CORE CLK in bypass mode, fruunig at SYS_CLK" + " frreq of %d.%d MHz", base_freq / 1000, base_freq % 1000); + } + + /* Set DPLL3 to automatic to save power */ + pio_change_32(&device->cm.clocks->autoidle_pll, + CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_AUTOMATIC, + CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_MASK, 5); + + /* DPLL4 provides peripheral domain clocks: + * CAM_MCLK, EMU_PER_ALWON_CLK, DSS1_ALWON_FCLK, and 96M_ALWON_FCLK. + * It uses SYS_CLK as reference clock and low frequency bypass. + * 96M clock is used by McBSP[1,5], MMC[1,2,3], I2C[1,2,3], so + * we can probably turn this off entirely (DSS is still non-functional). + */ + /* Set DPLL4 to automatic to save power */ + pio_change_32(&device->cm.clocks->autoidle_pll, + CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_AUTOMATIC, + CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_MASK, 5); + + /* DPLL5 provide peripheral domain clocks: 120M_FCLK. + * It uses SYS_CLK as reference clock and low frequency bypass. + * 120M clock is used by HS USB and USB TLL. + */ + // TODO setup DPLL5 + if ((pio_read_32(&device->cm.clocks->clken2_pll) + & CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_MASK) + != CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_LOCK) { + /* Compute divisors and multiplier + * See AMDM37x TRM p. 300 for the formula */ + // TODO: base_freq does not have to be rounded to Mhz + // (that's why I used KHz as unit). + const unsigned mult = 120; + const unsigned div = (base_freq / 1000) - 1; + const unsigned div2 = 1; + if ( ((base_freq % 1000) != 0) || (div > 127)) { + ddf_msg(LVL_ERROR, "Rounding error, or divisor to big " + "freq: %d, div: %d", base_freq, div); + return; + }; + assert(div <= 127); + + /* Set multiplier */ + pio_change_32(&device->cm.clocks->clksel4_pll, + CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT_CREATE(mult), + CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT_MASK, 10); + + /* Set DPLL divisor */ + pio_change_32(&device->cm.clocks->clksel4_pll, + CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV_CREATE(div), + CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV_MASK, 10); + + /* Set output clock divisor */ + pio_change_32(&device->cm.clocks->clksel5_pll, + CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M_CREATE(div2), + CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M_MASK, 10); + + /* Start DPLL5 */ + pio_change_32(&device->cm.clocks->clken2_pll, + CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_LOCK, + CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_MASK, 10); + + } + /* Set DPLL5 to automatic to save power */ + pio_change_32(&device->cm.clocks->autoidle2_pll, + CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_AUTOMATIC, + CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_MASK, 5); +} + +/** Enable/disable function and interface clocks for USBTLL and USBHOST. + * @param device Register map. + * @param on True to switch clocks on. + */ +void amdm37x_usb_clocks_set(amdm37x_t *device, bool enabled) +{ + if (enabled) { + /* Enable interface and function clock for USB TLL */ + pio_set_32(&device->cm.core->fclken3, + CORE_CM_FCLKEN3_EN_USBTLL_FLAG, 5); + pio_set_32(&device->cm.core->iclken3, + CORE_CM_ICLKEN3_EN_USBTLL_FLAG, 5); + + /* Enable interface and function clock for USB hosts */ + pio_set_32(&device->cm.usbhost->fclken, + USBHOST_CM_FCLKEN_EN_USBHOST1_FLAG | + USBHOST_CM_FCLKEN_EN_USBHOST2_FLAG, 5); + pio_set_32(&device->cm.usbhost->iclken, + USBHOST_CM_ICLKEN_EN_USBHOST, 5); +#if 0 + printf("DPLL5 (and everything else) should be on: %" + PRIx32" %"PRIx32".\n", + pio_read_32(&device->cm.clocks->idlest_ckgen), + pio_read_32(&device->cm.clocks->idlest2_ckgen)); +#endif + } else { + /* Disable interface and function clock for USB hosts */ + pio_clear_32(&device->cm.usbhost->iclken, + USBHOST_CM_ICLKEN_EN_USBHOST, 5); + pio_clear_32(&device->cm.usbhost->fclken, + USBHOST_CM_FCLKEN_EN_USBHOST1_FLAG | + USBHOST_CM_FCLKEN_EN_USBHOST2_FLAG, 5); + + /* Disable interface and function clock for USB TLL */ + pio_clear_32(&device->cm.core->iclken3, + CORE_CM_ICLKEN3_EN_USBTLL_FLAG, 5); + pio_clear_32(&device->cm.core->fclken3, + CORE_CM_FCLKEN3_EN_USBTLL_FLAG, 5); + } +} + +/** Initialize USB TLL port connections. + * + * Different modes are on page 3312 of the Manual Figure 22-34. + * Select mode than can operate in FS/LS. + */ +int amdm37x_usb_tll_init(amdm37x_t *device) +{ + /* Check access */ + if (pio_read_32(&device->cm.core->idlest3) & CORE_CM_IDLEST3_ST_USBTLL_FLAG) { + ddf_msg(LVL_ERROR, "USB TLL is not accessible"); + return EIO; + } + + /* Reset USB TLL */ + pio_set_32(&device->tll->sysconfig, TLL_SYSCONFIG_SOFTRESET_FLAG, 5); + ddf_msg(LVL_DEBUG2, "Waiting for USB TLL reset"); + while (!(pio_read_32(&device->tll->sysstatus) & TLL_SYSSTATUS_RESET_DONE_FLAG)); + ddf_msg(LVL_DEBUG, "USB TLL Reset done."); + + /* Setup idle mode (smart idle) */ + pio_change_32(&device->tll->sysconfig, + TLL_SYSCONFIG_CLOCKACTIVITY_FLAG | TLL_SYSCONFIG_AUTOIDLE_FLAG | + TLL_SYSCONFIG_SIDLE_MODE_SMART, TLL_SYSCONFIG_SIDLE_MODE_MASK, 5); + + /* Smart idle for UHH */ + pio_change_32(&device->uhh->sysconfig, + UHH_SYSCONFIG_CLOCKACTIVITY_FLAG | UHH_SYSCONFIG_AUTOIDLE_FLAG | + UHH_SYSCONFIG_SIDLE_MODE_SMART, UHH_SYSCONFIG_SIDLE_MODE_MASK, 5); + + /* Set all ports to go through TLL(UTMI) + * Direct connection can only work in HS mode */ + pio_set_32(&device->uhh->hostconfig, + UHH_HOSTCONFIG_P1_ULPI_BYPASS_FLAG | + UHH_HOSTCONFIG_P2_ULPI_BYPASS_FLAG | + UHH_HOSTCONFIG_P3_ULPI_BYPASS_FLAG, 5); + + /* What is this? */ + pio_set_32(&device->tll->shared_conf, TLL_SHARED_CONF_FCLK_IS_ON_FLAG, 5); + + for (unsigned i = 0; i < 3; ++i) { + /* Serial mode is the only one capable of FS/LS operation. + * Select FS/LS mode, no idea what the difference is + * one of bidirectional modes might be good choice + * 2 = 3pin bidi phy. */ + pio_change_32(&device->tll->channel_conf[i], + TLL_CHANNEL_CONF_CHANMODE_UTMI_SERIAL_MODE | + TLL_CHANNEL_CONF_FSLSMODE_3PIN_BIDI_PHY, + TLL_CHANNEL_CONF_CHANMODE_MASK | + TLL_CHANNEL_CONF_FSLSMODE_MASK, 5); + } + return EOK; +} Index: uspace/drv/platform/amdm37x/amdm37x.h =================================================================== --- uspace/drv/platform/amdm37x/amdm37x.h (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) +++ uspace/drv/platform/amdm37x/amdm37x.h (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup amdm37xdrv + * @{ + */ +/** @file + * @brief AM/DM 37x device. + */ +#ifndef AMDM37x_H +#define AMDM37x_H + +#include "uhh.h" +#include "usbtll.h" + +#include "cm/core.h" +#include "cm/clock_control.h" +#include "cm/usbhost.h" +#include "cm/mpu.h" +#include "cm/iva2.h" + +#include "prm/clock_control.h" +#include "prm/global_reg.h" + +#include + +typedef struct { + uhh_regs_t *uhh; + tll_regs_t *tll; + struct { + mpu_cm_regs_t *mpu; + iva2_cm_regs_t *iva2; + core_cm_regs_t *core; + clock_control_cm_regs_t *clocks; + usbhost_cm_regs_t *usbhost; + } cm; + struct { + clock_control_prm_regs_t *clocks; + global_reg_prm_regs_t *global; + } prm; +} amdm37x_t; + +int amdm37x_init(amdm37x_t *device, bool trace_io); +int amdm37x_usb_tll_init(amdm37x_t *device); +void amdm37x_setup_dpll_on_autoidle(amdm37x_t *device); +void amdm37x_usb_clocks_set(amdm37x_t *device, bool enabled); + +#endif +/** + * @} + */ Index: uspace/drv/platform/amdm37x/amdm37x.ma =================================================================== --- uspace/drv/platform/amdm37x/amdm37x.ma (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) +++ uspace/drv/platform/amdm37x/amdm37x.ma (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -0,0 +1,1 @@ +10 platform/beagleboardxm Index: uspace/drv/platform/amdm37x/cm/clock_control.h =================================================================== --- uspace/drv/platform/amdm37x/cm/clock_control.h (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) +++ uspace/drv/platform/amdm37x/cm/clock_control.h (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup amdm37xdrvclockcontrolcm + * @{ + */ +/** @file + * @brief Clock Control Clock Management IO register structure. + */ +#ifndef AMDM37x_CLOCK_CONTROL_CM_H +#define AMDM37x_CLOCK_CONTROL_CM_H +#include +#include + +/* AM/DM37x TRM p.485 */ +#define CLOCK_CONTROL_CM_BASE_ADDRESS 0x48004d00 +#define CLOCK_CONTROL_CM_SIZE 8192 + +/** Clock control register map + * + * Periph DPLL == DPLL4 + * Core DPLL == DPLL3 + */ +typedef struct { + ioport32_t clken_pll; +#define CLOCK_CONTROL_CM_CLKEN_PLL_PWRDN_EMU_PERIPH_FLAG (1 << 31) +#define CLOCK_CONTROL_CM_CLKEN_PLL_PWRDN_CAM_FLAG (1 << 30) +#define CLOCK_CONTROL_CM_CLKEN_PLL_PWRDN_DSS1_FLAG (1 << 29) +#define CLOCK_CONTROL_CM_CLKEN_PLL_PWRDN_TV_FLAG (1 << 28) +#define CLOCK_CONTROL_CM_CLKEN_PLL_PWRDN_96M_FLAG (1 << 27) +#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH_DPLL_DRIFTGUARD_FLAG (1 << 19) +#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH_DPLL_MASK (0x7 << 16) +#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH_DPLL_LP_STOP (0x1 << 16) +#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH_DPLL_LOCK (0x7 << 16) +#define CLOCK_CONTROL_CM_CLKEN_PLL_PWRDN_EMU_CORE_FLAG (1 << 12) +#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_CORE_DPLL_LPMODE_FLAG (1 << 10) +#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_CORE_DPLL_DRIFTGUARD_FLAG (1 << 3) +#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_CORE_DPLL_MASK (0x7) +#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_CORE_DPLL_LP_BYPASS (0x5) +#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_CORE_DPLL_FAST_RELOCK (0x6) +#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_CORE_DPLL_LOCK (0x7) + + ioport32_t clken2_pll; +#define CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_LPMODE_FLAG (1 << 10) +#define CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_DRIFTGUARD_FLAG (1 << 3) +#define CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_MASK (0x7) +#define CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_LP_STOP (0x1) +#define CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_LOCK (0x7) + + PADD32[6]; + + const ioport32_t idlest_ckgen; +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_EMU_PERIPH_CLK_FLAG (1 << 13) +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_CAM_CLK_FLAG (1 << 12) +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_DSS1_CLK_FLAG (1 << 11) +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_TV_CLK_FLAG (1 << 10) +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_FUNC96M_CLK_FLAG (1 << 9) +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_EMU_CORE_CLK_FLAG (1 << 8) +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_54M_CLK_FLAG (1 << 5) +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_12M_CLK_FLAG (1 << 4) +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_48M_CLK_FLAG (1 << 3) +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_96M_CLK_FLAG (1 << 2) +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_PERIPH_CLK_FLAG (1 << 1) +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_CORE_CLK_FLAG (1 << 0) + + const ioport32_t idlest2_ckgen; +#define CLOCK_CONTROL_CM_IDLEST2_CKGEN_ST_FUNC120M_CLK_FLAG (1 << 3) +#define CLOCK_CONTROL_CM_IDLEST2_CKGEN_ST_120M_CLK_FLAG (1 << 1) +#define CLOCK_CONTROL_CM_IDLEST2_CKGEN_ST_PERIPH2_CLK_FLAG (1 << 0) + + PADD32[2]; + + ioport32_t autoidle_pll; +#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_MASK (0x7 << 3) +#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_DISABLED (0x0 << 3) +#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_AUTOMATIC (0x1 << 3) +#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_MASK (0x7) +#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_DISABLED (0x0) +#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_AUTOMATIC (0x1) +#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_AUTOMATIC_BYPASS (0x5) + + ioport32_t autoidle2_pll; +#define CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_MASK (0x7) +#define CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_DISABLED (0x0) +#define CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_AUTOMATIC (0x1) + + PADD32[2]; + + ioport32_t clksel1_pll; +#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27) +#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_CLKOUT_DIV_CREATE(x) (((x) & 0x1f) << 27) +#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_CLKOUT_DIV_GET(x) (((x) >> 27) & 0x1f) +#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_MULT_MASK (0x7ff << 16) +#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_MULT_CREATE(x) (((x) & 0x7ff) << 16) +#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_MULT_GET(x) (((x) >> 16) & 0x7ff) +#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_DIV_MASK (0x7f << 8) +#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_DIV_CREATE(x) (((x) & 0x7f) << 8) +#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_DIV_GET(x) (((x) >> 8) & 0x7f) +#define CLOCK_CONTROL_CM_CLKSEL1_PLL_SOURCE_96M_FLAG (1 << 6) +#define CLOCK_CONTROL_CM_CLKSEL1_PLL_SOURCE_54M_FLAG (1 << 5) +#define CLOCK_CONTROL_CM_CLKSEL1_PLL_SOURCE_48M_FLAG (1 << 3) + + ioport32_t clksel2_pll; +#define CLOCK_CONTROL_CM_CLKSEL2_PLL_SD_DIV_MASK (0xff << 24) +#define CLOCK_CONTROL_CM_CLKSEL2_PLL_SD_DIV_(x) (((x) & 0xff) << 24) +#define CLOCK_CONTROL_CM_CLKSEL2_PLL_DCO_SEL_MASK (0x7 << 21) +#define CLOCK_CONTROL_CM_CLKSEL2_PLL_DCO_SEL_500 (0x2 << 21) +#define CLOCK_CONTROL_CM_CLKSEL2_PLL_DCO_SEL_1000 (0x4 << 21) +#define CLOCK_CONTROL_CM_CLKSEL2_PLL_PERIPH_DPLL_MULT_MASK (0xfff << 8) +#define CLOCK_CONTROL_CM_CLKSEL2_PLL_PERIPH_DPLL_MULT(x) (((x) & 0xfff) << 8) +#define CLOCK_CONTROL_CM_CLKSEL2_PLL_PERIPH_DPLL_DIV_MASK (0x7f) +#define CLOCK_CONTROL_CM_CLKSEL2_PLL_PERIPH_DPLL_DIV(x) ((x) & 0x7f) + + ioport32_t clksel3_pll; +#define CLOCK_CONTROL_CM_CLKSEL3_PLL_DIV_96M_MASK (0xf) +#define CLOCK_CONTROL_CM_CLKSEL3_PLL_DIV_96M(x) ((x) & 0xf) + + ioport32_t clksel4_pll; +#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT_MASK (0x7ff << 8) +#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT_CREATE(x) (((x) & 0x7ff) << 8) +#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT_GET(x) (((x) >> 8) & 0x7ff) +#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV_MASK (0x7f) +#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV_CREATE(x) ((x) & 0x7f) +#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV_GET(x) ((x) & 0x7f) + + ioport32_t clksel5_pll; +#define CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M_MASK (0x1f) +#define CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M_CREATE(x) ((x) & 0x1f) +#define CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M_GET(x) ((x) & 0x1f) +} clock_control_cm_regs_t; + +#endif +/** + * @} + */ + Index: uspace/drv/platform/amdm37x/cm/core.h =================================================================== --- uspace/drv/platform/amdm37x/cm/core.h (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) +++ uspace/drv/platform/amdm37x/cm/core.h (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -0,0 +1,188 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup amdm37xdrvcorecm + * @{ + */ +/** @file + * @brief CORE Clock Management IO register structure. + */ +#ifndef AMDM37x_CORE_CM_H +#define AMDM37x_CORE_CM_H +#include +#include + +/* AM/DM37x TRM p.447 */ +#define CORE_CM_BASE_ADDRESS 0x48004a00 +#define CORE_CM_SIZE 8192 + +typedef struct { + ioport32_t fclken1; +#define CORE_CM_FCLKEN1_EN_MCBSP1_FLAG (1 << 9) +#define CORE_CM_FCLKEN1_EN_MCBSP5_FLAG (1 << 10) +#define CORE_CM_FCLKEN1_EN_GPT10_FLAG (1 << 11) +#define CORE_CM_FCLKEN1_EN_GPT11_FLAG (1 << 12) +#define CORE_CM_FCLKEN1_EN_UART1_FLAG (1 << 13) +#define CORE_CM_FCLKEN1_EN_UART2_FLAG (1 << 14) +#define CORE_CM_FCLKEN1_EN_I2C1_FLAG (1 << 15) +#define CORE_CM_FCLKEN1_EN_I2C2_FLAG (1 << 16) +#define CORE_CM_FCLKEN1_EN_I2C3_FLAG (1 << 17) +#define CORE_CM_FCLKEN1_EN_MCSPI1_FLAG (1 << 18) +#define CORE_CM_FCLKEN1_EN_MCSPI2_FLAG (1 << 19) +#define CORE_CM_FCLKEN1_EN_MCSPI3_FLAG (1 << 20) +#define CORE_CM_FCLKEN1_EN_MCSPI4_FLAG (1 << 21) +#define CORE_CM_FCLKEN1_EN_HDQ_FLAG (1 << 22) +#define CORE_CM_FCLKEN1_EN_MMC1_FLAG (1 << 24) +#define CORE_CM_FCLKEN1_EN_MMC2_FLAG (1 << 25) +#define CORE_CM_FCLKEN1_EN_MMC3_FLAG (1 << 30) + + PADD32; + ioport32_t fclken3; +#define CORE_CM_FCLKEN3_EN_TS_FLAG (1 << 1) +#define CORE_CM_FCLKEN3_EN_USBTLL_FLAG (1 << 2) + + PADD32; + ioport32_t iclken1; +#define CORE_CM_ICLKEN1_EN_SDRC_FLAG (1 << 1) +#define CORE_CM_ICLKEN1_EN_HSOTGUSB_FLAG (1 << 4) +#define CORE_CM_ICLKEN1_EN_SCMCTRL_FLAG (1 << 6) +#define CORE_CM_ICLKEN1_EN_MAILBOXES_FLAG (1 << 7) +#define CORE_CM_ICLKEN1_EN_MCBSP1_FLAG (1 << 9) +#define CORE_CM_ICLKEN1_EN_MCBSP5_FLAG (1 << 10) +#define CORE_CM_ICLKEN1_EN_GPT10_FLAG (1 << 11) +#define CORE_CM_ICLKEN1_EN_GPT11_FLAG (1 << 12) +#define CORE_CM_ICLKEN1_EN_UART1_FLAG (1 << 13) +#define CORE_CM_ICLKEN1_EN_UART2_FLAG (1 << 14) +#define CORE_CM_ICLKEN1_EN_I2C1_FLAG (1 << 15) +#define CORE_CM_ICLKEN1_EN_I2C2_FLAG (1 << 16) +#define CORE_CM_ICLKEN1_EN_I2C3_FLAG (1 << 17) +#define CORE_CM_ICLKEN1_EN_MCSPI1_FLAG (1 << 18) +#define CORE_CM_ICLKEN1_EN_MCSPI2_FLAG (1 << 19) +#define CORE_CM_ICLKEN1_EN_MCSPI3_FLAG (1 << 20) +#define CORE_CM_ICLKEN1_EN_MCSPI4_FLAG (1 << 21) +#define CORE_CM_ICLKEN1_EN_HDQ_FLAG (1 << 22) +#define CORE_CM_ICLKEN1_EN_MMC1_FLAG (1 << 24) +#define CORE_CM_ICLKEN1_EN_MMC2_FLAG (1 << 25) +#define CORE_CM_ICLKEN1_EN_ICR_FLAG (1 << 29) +#define CORE_CM_ICLKEN1_EN_MMC3_FLAG (1 << 30) + + ioport32_t reserved1; + ioport32_t iclken3; +#define CORE_CM_ICLKEN3_EN_USBTLL_FLAG (1 << 2) + + PADD32; + const ioport32_t idlest1; +#define CORE_CM_IDLEST1_ST_SDRC_FLAG (1 << 1) +#define CORE_CM_IDLEST1_ST_SDMA_FLAG (1 << 2) +#define CORE_CM_IDLEST1_ST_HSOTGUSB_STBY_FLAG (1 << 4) +#define CORE_CM_IDLEST1_ST_HSOTGUSB_IDLE_FLAG (1 << 5) +#define CORE_CM_IDLEST1_ST_SCMCTRL_FLAG (1 << 6) +#define CORE_CM_IDLEST1_ST_MAILBOXES_FLAG (1 << 7) +#define CORE_CM_IDLEST1_ST_MCBSP1_FLAG (1 << 9) +#define CORE_CM_IDLEST1_ST_MCBSP5_FLAG (1 << 10) +#define CORE_CM_IDLEST1_ST_GPT10_FLAG (1 << 11) +#define CORE_CM_IDLEST1_ST_GPT11_FLAG (1 << 12) +#define CORE_CM_IDLEST1_ST_UART1_FLAG (1 << 13) +#define CORE_CM_IDLEST1_ST_UART2_FLAG (1 << 14) +#define CORE_CM_IDLEST1_ST_I2C1_FLAG (1 << 15) +#define CORE_CM_IDLEST1_ST_I2C2_FLAG (1 << 16) +#define CORE_CM_IDLEST1_ST_I2C3_FLAG (1 << 17) +#define CORE_CM_IDLEST1_ST_MCSPI1_FLAG (1 << 18) +#define CORE_CM_IDLEST1_ST_MCSPI2_FLAG (1 << 19) +#define CORE_CM_IDLEST1_ST_MCSPI3_FLAG (1 << 20) +#define CORE_CM_IDLEST1_ST_MCSPI4_FLAG (1 << 21) +#define CORE_CM_IDLEST1_ST_HDQ_FLAG (1 << 22) +#define CORE_CM_IDLEST1_ST_MMC1_FLAG (1 << 24) +#define CORE_CM_IDLEST1_ST_MMC2_FLAG (1 << 25) +#define CORE_CM_IDLEST1_ST_ICR_FLAG (1 << 29) +#define CORE_CM_IDLEST1_ST_MMC3_FLAG (1 << 30) + + const ioport32_t reserved2; + const ioport32_t idlest3; +#define CORE_CM_IDLEST3_ST_USBTLL_FLAG (1 << 2) + + PADD32; + ioport32_t autoidle1; +#define CORE_CM_AUTOIDLE1_AUTO_HSOTGUSB_FLAG (1 << 4) +#define CORE_CM_AUTOIDLE1_AUTO_SCMCTRL_FLAG (1 << 6) +#define CORE_CM_AUTOIDLE1_AUTO_MAILBOXES_FLAG (1 << 7) +#define CORE_CM_AUTOIDLE1_AUTO_MCBSP1_FLAG (1 << 9) +#define CORE_CM_AUTOIDLE1_AUTO_MCBSP5_FLAG (1 << 10) +#define CORE_CM_AUTOIDLE1_AUTO_GPT10_FLAG (1 << 11) +#define CORE_CM_AUTOIDLE1_AUTO_GPT11_FLAG (1 << 12) +#define CORE_CM_AUTOIDLE1_AUTO_UART1_FLAG (1 << 13) +#define CORE_CM_AUTOIDLE1_AUTO_UART2_FLAG (1 << 14) +#define CORE_CM_AUTOIDLE1_AUTO_I2C1_FLAG (1 << 15) +#define CORE_CM_AUTOIDLE1_AUTO_I2C2_FLAG (1 << 16) +#define CORE_CM_AUTOIDLE1_AUTO_I2C3_FLAG (1 << 17) +#define CORE_CM_AUTOIDLE1_AUTO_MCSPI1_FLAG (1 << 18) +#define CORE_CM_AUTOIDLE1_AUTO_MCSPI2_FLAG (1 << 19) +#define CORE_CM_AUTOIDLE1_AUTO_MCSPI3_FLAG (1 << 20) +#define CORE_CM_AUTOIDLE1_AUTO_MCSPI4_FLAG (1 << 21) +#define CORE_CM_AUTOIDLE1_AUTO_HDQ_FLAG (1 << 22) +#define CORE_CM_AUTOIDLE1_AUTO_MMC1_FLAG (1 << 24) +#define CORE_CM_AUTOIDLE1_AUTO_MMC2_FLAG (1 << 25) +#define CORE_CM_AUTOIDLE1_AUTO_ICR_FLAG (1 << 29) +#define CORE_CM_AUTOIDLE1_AUTO_MMC3_FLAG (1 << 30) + + ioport32_t reserved3; + ioport32_t autoidle3; +#define CORE_CM_AUTOIDLE3_AUTO_USBTLL_FLAG (1 << 2) + + PADD32; + ioport32_t clksel; +#define CORE_CM_CLKSEL_CLKSEL_L3_MASK (0x3 << 0) +#define CORE_CM_CLKSEL_CLKSEL_L3_DIVIDED1 (0x1 << 0) +#define CORE_CM_CLKSEL_CLKSEL_L3_DIVIDED2 (0x2 << 0) +#define CORE_CM_CLKSEL_CLKSEL_L4_MASK (0x3 << 2) +#define CORE_CM_CLKSEL_CLKSEL_L4_DIVIDED1 (0x1 << 2) +#define CORE_CM_CLKSEL_CLKSEL_L4_DIVIDED2 (0x2 << 2) +#define CORE_CM_CLKSEL_CLKSEL_96M_MASK (0x3 << 12) +#define CORE_CM_CLKSEL_CLKSEL_96M_DIVIDED1 (0x1 << 12) +#define CORE_CM_CLKSEL_CLKSEL_96M_DIVIDED2 (0x2 << 12) +#define CORE_CM_CLKSEL_CLKSEL_GPT10_FLAG (1 << 6) +#define CORE_CM_CLKSEL_CLKSEL_GPT11_FLAG (1 << 7) + + PADD32; + ioport32_t clkstctrl; +#define CORE_CM_CLKCTRL_CLKCTRL_L3_MASK (0x3 << 0) +#define CORE_CM_CLKCTRL_CLKCTRL_L3_AUTO_EN (0x0 << 0) +#define CORE_CM_CLKCTRL_CLKCTRL_L3_AUTO_DIS (0x3 << 0) +#define CORE_CM_CLKCTRL_CLKCTRL_L4_MASK (0x3 << 2) +#define CORE_CM_CLKCTRL_CLKCTRL_L4_AUTO_EN (0x0 << 2) +#define CORE_CM_CLKCTRL_CLKCTRL_L4_AUTO_DIS (0x3 << 2) + + const ioport32_t clkstst; +#define CORE_CM_CLKSTST_CLKACTIVITY_L3_FLAG (1 << 0) +#define CORE_CM_CLKSTST_CLKACTIVITY_L4_FLAG (1 << 1) +} core_cm_regs_t; + +#endif +/** + * @} + */ Index: uspace/drv/platform/amdm37x/cm/iva2.h =================================================================== --- uspace/drv/platform/amdm37x/cm/iva2.h (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) +++ uspace/drv/platform/amdm37x/cm/iva2.h (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup amdm37xdrvcm + * @{ + */ +/** @file + * @brief MPU Clock Management IO register structure. + */ +#ifndef AMDM37x_IVA2_CM_H +#define AMDM37x_IVA2_CM_H +#include +#include + +/* AM/DM37x TRM p.446 */ +#define IVA2_CM_BASE_ADDRESS 0x48004000 +#define IVA2_CM_SIZE 8192 + +typedef struct { + ioport32_t fclken; +#define IVA2_CM_FCLKEN_EN_IVA2_FLAG (1 << 0) + + ioport32_t clken_pll; +#define IVA2_CM_CLKEN_PLL_EN_IVA2_DPLL_LP_MODE_FLAG (1 << 10) +#define IVA2_CM_CLKEN_PLL_EN_IVA2_DPLL_DRIFTGUARD (1 << 3) +#define IVA2_CM_CLKEN_PLL_EN_IVA2_DPLL_EN_IVA2_DPLL_MASK (0x7) +#define IVA2_CM_CLKEN_PLL_EN_IVA2_DPLL_EN_IVA2_DPLL_LP_STOP (0x1) +#define IVA2_CM_CLKEN_PLL_EN_IVA2_DPLL_EN_IVA2_DPLL_LP_BYPASS (0x5) +#define IVA2_CM_CLKEN_PLL_EN_IVA2_DPLL_EN_IVA2_DPLL_LOCKED (0x7) + + PADD32[6]; + const ioport32_t idlest; +#define IVA2_CM_IDLEST_ST_IVA2_STANDBY_FLAG (1 << 0) + + const ioport32_t idlest_pll; +#define IVA2_CM_IDLEST_PLL_ST_IVA2_CLK_LOCKED_FLAG (1 << 0) + + PADD32[3]; + ioport32_t autoidle_pll; +#define IVA2_CM_AUTOIDLE_PLL_AUTO_IVA2_DPLL_MASK (0x7) +#define IVA2_CM_AUTOIDLE_PLL_AUTO_IVA2_DPLL_DISABLED (0x0) +#define IVA2_CM_AUTOIDLE_PLL_AUTO_IVA2_DPLL_ENABLED (0x1) + + PADD32[2]; + ioport32_t clksel1_pll; +#define IVA2_CM_CLKSEL1_PLL_IVA2_CLK_SRC_MASK (0x7 << 19) +#define IVA2_CM_CLKSEL1_PLL_IVA2_CLK_SRC_SHIFT (19) +#define IVA2_CM_CLKSEL1_PLL_IVA2_CLK_SRC_VAL(x) ((x >> 19) & 0x7) +#define IVA2_CM_CLKSEL1_PLL_IVA2_CLK_SRC_CORE_DIV_1 (0x1 << 19) +#define IVA2_CM_CLKSEL1_PLL_IVA2_CLK_SRC_CORE_DIV_2 (0x2 << 19) +#define IVA2_CM_CLKSEL1_PLL_IVA2_CLK_SRC_CORE_DIV_4 (0x4 << 19) +#define IVA2_CM_CLKSEL1_PLL_IVA2_DPLL_MULT_MASK (0x7ff << 8) +#define IVA2_CM_CLKSEL1_PLL_IVA2_DPLL_MULT_SHIFT (8) +#define IVA2_CM_CLKSEL1_PLL_IVA2_DPLL_DIV_MASK (0x7f << 0) +#define IVA2_CM_CLKSEL1_PLL_IVA2_DPLL_DIV_SHIFT (0) + + ioport32_t clksel2_pll; +#define IVA2_CM_CLKSEL2_PLL_IVA2_DPLL_CLKOUT_DIV_MASK (0x1f) + + ioport32_t clkstctrl; +#define IVA2_CM_CLKSCTRL_CLKTRCTRL_IVA2_MASK (0x3) +#define IVA2_CM_CLKSCTRL_CLKTRCTRL_IVA2_DISABLED (0x0) +#define IVA2_CM_CLKSCTRL_CLKTRCTRL_IVA2_START_SLEEP (0x2) +#define IVA2_CM_CLKSCTRL_CLKTRCTRL_IVA2_START_WAKEUP (0x2) +#define IVA2_CM_CLKSCTRL_CLKTRCTRL_IVA2_AUTOMATIC (0x3) + + const ioport32_t clkstst; +#define IVA2_CM_CLKSTST_CLKACTIVITY_IVA2_ACTIVE_FLAG (1 << 0) + +} iva2_cm_regs_t; + +#endif +/** + * @} + */ + Index: uspace/drv/platform/amdm37x/cm/mpu.h =================================================================== --- uspace/drv/platform/amdm37x/cm/mpu.h (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) +++ uspace/drv/platform/amdm37x/cm/mpu.h (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup amdm37xdrvcm + * @{ + */ +/** @file + * @brief MPU Clock Management IO register structure. + */ +#ifndef AMDM37x_MPU_CM_H +#define AMDM37x_MPU_CM_H +#include +#include + +/* AM/DM37x TRM p.455 */ +#define MPU_CM_BASE_ADDRESS 0x48004900 +#define MPU_CM_SIZE 8192 + +typedef struct { + PADD32; + ioport32_t clken_pll; +#define MPU_CM_CLKEN_PLL_EN_MPU_DPLL_LP_MODE_FLAG (1 << 10) +#define MPU_CM_CLKEN_PLL_EN_MPU_DPLL_DRIFTGUARD (1 << 3) +#define MPU_CM_CLKEN_PLL_EN_MPU_DPLL_EN_MPU_DPLL_MASK (0x7) +#define MPU_CM_CLKEN_PLL_EN_MPU_DPLL_EN_MPU_DPLL_LP_BYPASS (0x5) +#define MPU_CM_CLKEN_PLL_EN_MPU_DPLL_EN_MPU_DPLL_LOCKED (0x7) + + PADD32[6]; + const ioport32_t idlest; +#define MPU_CM_IDLEST_ST_MPU_STANDBY_FLAG (1 << 0) + + const ioport32_t idlest_pll; +#define MPU_CM_IDLEST_PLL_ST_MPU_CLK_LOCKED_FLAG (1 << 0) + + PADD32[3]; + ioport32_t autoidle_pll; +#define MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_MASK (0x7) +#define MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_DISABLED (0x0) +#define MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_ENABLED (0x1) + + PADD32[2]; + ioport32_t clksel1_pll; +#define MPU_CM_CLKSEL1_PLL_MPU_CLK_SRC_MASK (0x7 << 19) +#define MPU_CM_CLKSEL1_PLL_MPU_CLK_SRC_SHIFT (19) +#define MPU_CM_CLKSEL1_PLL_MPU_CLK_SRC_VAL(x) ((x >> 19) & 0x7) +#define MPU_CM_CLKSEL1_PLL_MPU_CLK_SRC_CORE_DIV_1 (0x1 << 19) +#define MPU_CM_CLKSEL1_PLL_MPU_CLK_SRC_CORE_DIV_2 (0x2 << 19) +#define MPU_CM_CLKSEL1_PLL_MPU_CLK_SRC_CORE_DIV_4 (0x4 << 19) +#define MPU_CM_CLKSEL1_PLL_MPU_DPLL_MULT_MASK (0x7ff << 8) +#define MPU_CM_CLKSEL1_PLL_MPU_DPLL_MULT_SHIFT (8) +#define MPU_CM_CLKSEL1_PLL_MPU_DPLL_DIV_MASK (0x7f << 0) +#define MPU_CM_CLKSEL1_PLL_MPU_DPLL_DIV_SHIFT (0) + + ioport32_t clksel2_pll; +#define MPU_CM_CLKSEL2_PLL_MPU_DPLL_CLKOUT_DIV_MASK (0x1f) + + ioport32_t clkstctrl; +#define MPU_CM_CLKSCTRL_CLKTRCTRL_MPU_MASK (0x3) +#define MPU_CM_CLKSCTRL_CLKTRCTRL_MPU_DISABLED (0x0) +#define MPU_CM_CLKSCTRL_CLKTRCTRL_MPU_START_WAKEUP (0x2) +#define MPU_CM_CLKSCTRL_CLKTRCTRL_MPU_AUTOMATIC (0x3) + + const ioport32_t clkstst; +#define MPU_CM_CLKSTST_CLKACTIVITY_MPU_ACTIVE_FLAG (1 << 0) + +} mpu_cm_regs_t; + +#endif +/** + * @} + */ + Index: uspace/drv/platform/amdm37x/cm/usbhost.h =================================================================== --- uspace/drv/platform/amdm37x/cm/usbhost.h (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) +++ uspace/drv/platform/amdm37x/cm/usbhost.h (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup amdm37xdrvusbhostcm + * @{ + */ +/** @file + * @brief USBHOST Clock Management IO register structure. + */ +#ifndef AMDM37x_USBHOST_CM_H +#define AMDM37x_USBHOST_CM_H +#include +#include + +/* AM/DM37x TRM p.447 */ +#define USBHOST_CM_BASE_ADDRESS 0x48005400 +#define USBHOST_CM_SIZE 8192 + +typedef struct { + ioport32_t fclken; +#define USBHOST_CM_FCLKEN_EN_USBHOST1_FLAG (1 << 0) +#define USBHOST_CM_FCLKEN_EN_USBHOST2_FLAG (1 << 1) + + PADD32[3]; + ioport32_t iclken; +#define USBHOST_CM_ICLKEN_EN_USBHOST (1 << 0) + + PADD32[3]; + const ioport32_t idlest; +#define USBHOST_CM_IDLEST_ST_USBHOST_STDBY_FLAG (1 << 0) +#define USBHOST_CM_IDLEST_ST_USBHOST_IDLE_FLAG (1 << 1) + + PADD32[3]; + ioport32_t autoidle; +#define USBHOST_CM_AUTOIDLE_AUTO_USBHOST_FLAG (1 << 0) + + PADD32[4]; + ioport32_t sleepdep; +#define USBHOST_CM_SLEEPDEP_EN_MPU_FLAG (1 << 1) +#define USBHOST_CM_SLEEPDEP_EN_IVA2_FLAG (1 << 2) + + ioport32_t clkstctrl; +#define USBHOST_CM_CLKSTCTRL_CLKSTCTRL_USBHOST_MASK (0x3 << 0) +#define USBHOST_CM_CLKSTCTRL_CLKSTCTRL_USBHOST_AUTO_DIS (0x0 << 0) +#define USBHOST_CM_CLKSTCTRL_CLKSTCTRL_USBHOST_SUPERVISED_SLEEP (0x1 << 0) +#define USBHOST_CM_CLKSTCTRL_CLKSTCTRL_USBHOST_SUPERVISED_WAKEUP (0x2 << 0) +#define USBHOST_CM_CLKSTCTRL_CLKSTCTRL_USBHOST_AUTO_EN (0x3 << 0) + + ioport32_t clkstst; +#define USBHOST_CM_CLKSTCTRL_CLKSTST_CLKACTIVITY_USBHOST (1 << 0) +} usbhost_cm_regs_t; + +#endif +/** + * @} + */ + Index: uspace/drv/platform/amdm37x/main.c =================================================================== --- uspace/drv/platform/amdm37x/main.c (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) +++ uspace/drv/platform/amdm37x/main.c (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -0,0 +1,282 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @defgroup amdm37x TI AM/DM37x platform driver. + * @brief HelenOS TI AM/DM37x platform driver. + * @{ + */ + +/** @file + */ + +#define DEBUG_CM 0 + +#include +#include +#include +#include + +#include "amdm37x.h" + +#define NAME "amdm37x" + +typedef struct { + const char *name; + match_id_t match_id; + hw_resource_list_t hw_resources; +} amdm37x_fun_t; + +/* See amdm37x TRM page 3316 for these values */ +#define OHCI_BASE_ADDRESS 0x48064400 +#define OHCI_SIZE 1024 +#define EHCI_BASE_ADDRESS 0x48064800 +#define EHCI_SIZE 1024 + +/* See amdm37x TRM page 1813 for these values */ +#define DSS_BASE_ADDRESS 0x48050000 +#define DSS_SIZE 512 +#define DISPC_BASE_ADDRESS 0x48050400 +#define DISPC_SIZE 1024 +#define VIDEO_ENC_BASE_ADDRESS 0x48050C00 +#define VIDEO_ENC_SIZE 256 + + +static hw_resource_t ohci_res[] = { + { + .type = MEM_RANGE, + .res.io_range = { + .address = OHCI_BASE_ADDRESS, + .size = OHCI_SIZE, + .endianness = LITTLE_ENDIAN + }, + }, + { + .type = INTERRUPT, + .res.interrupt = { .irq = 76 }, + }, +}; + +static hw_resource_t ehci_res[] = { + { + .type = MEM_RANGE, + /* See amdm37x TRM page. 3316 for these values */ + .res.io_range = { + .address = EHCI_BASE_ADDRESS, + .size = EHCI_SIZE, + .endianness = LITTLE_ENDIAN + }, + }, + { + .type = INTERRUPT, + .res.interrupt = { .irq = 77 }, + }, +}; + +static hw_resource_t disp_res[] = { + { + .type = MEM_RANGE, + .res.io_range = { + .address = DSS_BASE_ADDRESS, + .size = DSS_SIZE, + .endianness = LITTLE_ENDIAN + }, + }, + { + .type = MEM_RANGE, + .res.io_range = { + .address = DISPC_BASE_ADDRESS, + .size = DISPC_SIZE, + .endianness = LITTLE_ENDIAN + }, + }, + { + .type = MEM_RANGE, + .res.io_range = { + .address = VIDEO_ENC_BASE_ADDRESS, + .size = VIDEO_ENC_SIZE, + .endianness = LITTLE_ENDIAN + }, + }, + { + .type = INTERRUPT, + .res.interrupt = { .irq = 25 }, + }, +}; + +static const amdm37x_fun_t amdm37x_funcs[] = { +{ + .name = "ohci", + .match_id = { .id = "usb/host=ohci", .score = 90 }, + .hw_resources = { .resources = ohci_res, .count = ARRAY_SIZE(ohci_res) } +}, +{ + .name = "ehci", + .match_id = { .id = "usb/host=ehci", .score = 90 }, + .hw_resources = { .resources = ehci_res, .count = ARRAY_SIZE(ehci_res) } +}, +{ + .name = "fb", + .match_id = { .id = "amdm37x&dispc", .score = 90 }, + .hw_resources = { .resources = disp_res, .count = ARRAY_SIZE(disp_res) } +}, +}; + + +static hw_resource_list_t *amdm37x_get_resources(ddf_fun_t *fnode); +static bool amdm37x_enable_interrupt(ddf_fun_t *fun); + +static hw_res_ops_t fun_hw_res_ops = { + .get_resource_list = &amdm37x_get_resources, + .enable_interrupt = &amdm37x_enable_interrupt, +}; + +static ddf_dev_ops_t amdm37x_fun_ops = { + .interfaces[HW_RES_DEV_IFACE] = &fun_hw_res_ops +}; + +static int amdm37x_add_fun(ddf_dev_t *dev, const amdm37x_fun_t *fun) +{ + assert(dev); + assert(fun); + + ddf_msg(LVL_DEBUG, "Adding new function '%s'.", fun->name); + + /* Create new device function. */ + ddf_fun_t *fnode = ddf_fun_create(dev, fun_inner, fun->name); + if (fnode == NULL) + return ENOMEM; + + /* Add match id */ + int ret = ddf_fun_add_match_id(fnode, + fun->match_id.id, fun->match_id.score); + if (ret != EOK) { + ddf_fun_destroy(fnode); + return ret; + } + + /* Alloc needed data */ + amdm37x_fun_t *rf = + ddf_fun_data_alloc(fnode, sizeof(amdm37x_fun_t)); + if (!rf) { + ddf_fun_destroy(fnode); + return ENOMEM; + } + *rf = *fun; + + /* Set provided operations to the device. */ + ddf_fun_set_ops(fnode, &amdm37x_fun_ops); + + /* Register function. */ + ret = ddf_fun_bind(fnode); + if (ret != EOK) { + ddf_msg(LVL_ERROR, "Failed binding function %s.", fun->name); + ddf_fun_destroy(fnode); + return ret; + } + + return EOK; +} + +/** Add the root device. + * + * @param dev Device which is root of the whole device tree + * (both of HW and pseudo devices). + * + * @return Zero on success, negative error number otherwise. + * + */ +static int amdm37x_dev_add(ddf_dev_t *dev) +{ + assert(dev); + amdm37x_t *device = ddf_dev_data_alloc(dev, sizeof(amdm37x_t)); + if (!device) + return ENOMEM; + int ret = amdm37x_init(device, DEBUG_CM); + if (ret != EOK) { + ddf_msg(LVL_FATAL, "Failed to setup hw access!.\n"); + return ret; + } + + /* Set dplls to ON and automatic */ + amdm37x_setup_dpll_on_autoidle(device); + + /* Enable function and interface clocks */ + amdm37x_usb_clocks_set(device, true); + + /* Init TLL */ + ret = amdm37x_usb_tll_init(device); + if (ret != EOK) { + ddf_msg(LVL_FATAL, "Failed to init USB TLL!.\n"); + amdm37x_usb_clocks_set(device, false); + return ret; + } + + /* Register functions */ + for (unsigned i = 0; i < ARRAY_SIZE(amdm37x_funcs); ++i) { + if (amdm37x_add_fun(dev, &amdm37x_funcs[i]) != EOK) + ddf_msg(LVL_ERROR, "Failed to add %s function for " + "BeagleBoard-xM platform.", amdm37x_funcs[i].name); + } + return EOK; +} + +/** The root device driver's standard operations. */ +static driver_ops_t amdm37x_ops = { + .dev_add = &amdm37x_dev_add +}; + +/** The root device driver structure. */ +static driver_t amdm37x_driver = { + .name = NAME, + .driver_ops = &amdm37x_ops +}; + +static hw_resource_list_t * amdm37x_get_resources(ddf_fun_t *fnode) +{ + amdm37x_fun_t *fun = ddf_fun_data_get(fnode); + assert(fun != NULL); + return &fun->hw_resources; +} + +static bool amdm37x_enable_interrupt(ddf_fun_t *fun) +{ + //TODO: Implement + return false; +} + +int main(int argc, char *argv[]) +{ + printf("%s: HelenOS AM/DM37x(OMAP37x) platform driver\n", NAME); + ddf_log_init(NAME); + return ddf_driver_main(&amdm37x_driver); +} + +/** + * @} + */ Index: uspace/drv/platform/amdm37x/prm/clock_control.h =================================================================== --- uspace/drv/platform/amdm37x/prm/clock_control.h (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) +++ uspace/drv/platform/amdm37x/prm/clock_control.h (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup amdm37xdrvprm + * @{ + */ +/** @file + * @brief Clock Control Clock Management IO register structure. + */ +#ifndef AMDM37X_PRM_CLOCK_CONTROL_H +#define AMDM37X_PRM_CLOCK_CONTROL_H +#include +#include + +/* AM/DM37x TRM p.536 and p.589 */ +#define CLOCK_CONTROL_PRM_BASE_ADDRESS 0x48306d00 +#define CLOCK_CONTROL_PRM_SIZE 8192 + +/** Clock control PRM register map + */ +typedef struct { + PADD32[16]; + ioport32_t clksel; +#define CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_MASK (0x7) +#define CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_12M (0x0) +#define CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_13M (0x1) +#define CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_19_2M (0x2) +#define CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_26M (0x3) +#define CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_38_4M (0x4) +#define CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_16_8M (0x5) + + PADD32[12]; + ioport32_t clkout_ctrl; +#define CLOCK_CONTROL_PRM_CLKOUT_CTRL_CLKOUOUT_EN_FLAG (1 << 7) + +} clock_control_prm_regs_t; + +static inline unsigned sys_clk_freq_kHz(unsigned reg_val) +{ + switch(reg_val) + { + case CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_12M: return 12000; + case CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_13M: return 13000; + case CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_19_2M: return 19200; + case CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_26M: return 26000; + case CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_38_4M: return 38400; + case CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_16_8M: return 16800; + } + return 0; +} + + +#endif +/** + * @} + */ Index: uspace/drv/platform/amdm37x/prm/global_reg.h =================================================================== --- uspace/drv/platform/amdm37x/prm/global_reg.h (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) +++ uspace/drv/platform/amdm37x/prm/global_reg.h (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -0,0 +1,300 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup amdm37xdrvprm + * @{ + */ +/** @file + * @brief Clock Control Clock Management IO register structure. + */ +#ifndef AMDM37X_PRM_GLOBAL_REG_H +#define AMDM37X_PRM_GLOBAL_REG_H +#include +#include + +/* AM/DM37x TRM p.536 and p.615 */ +#define GLOBAL_REG_PRM_BASE_ADDRESS 0x48307200 +#define GLOBAL_REG_PRM_SIZE 65536 + +/** Global Reg PRM register map + */ +typedef struct { + PADD32[8]; + struct { + ioport32_t smps_sa; +#define GLOBAL_REG_PRM_VC_SMPS_SA_SA0_MASK (0x7f << 0) +#define GLOBAL_REG_PRM_VC_SMPS_SA_SA0_CREATE(x) (((x) & 0x7f) << 0) +#define GLOBAL_REG_PRM_VC_SMPS_SA_SA0_GET(r) (r & 0x7f) +#define GLOBAL_REG_PRM_VC_SMPS_SA_SA1_MASK (0x7f << 16) +#define GLOBAL_REG_PRM_VC_SMPS_SA_SA1_CREATE(x) (((x) & 0x7f) << 16) +#define GLOBAL_REG_PRM_VC_SMPS_SA_SA1_GET(r) (((r) >> 16 ) & 0x7f) + + ioport32_t smps_vol_ra; +#define GLOBAL_REG_PRM_VC_SMPS_VOL_RA_VOLRA0_MASK (0xff << 0) +#define GLOBAL_REG_PRM_VC_SMPS_VOL_RA_VOLRA0_CREATE(x) (((x) & 0xff) << 0) +#define GLOBAL_REG_PRM_VC_SMPS_VOL_RA_VOLRA0_GET(r) (r & 0xff) +#define GLOBAL_REG_PRM_VC_SMPS_VOL_RA_VOLRA1_MASK (0xff << 16) +#define GLOBAL_REG_PRM_VC_SMPS_VOL_RA_VOLRA1_CREATE(x) (((x) & 0xff) << 16) +#define GLOBAL_REG_PRM_VC_SMPS_VOL_RA_VOLRA1_GET(r) (((r) >> 16 ) & 0xff) + + ioport32_t smps_cmd_ra; +#define GLOBAL_REG_PRM_VC_SMPS_CMD_RA_CMDRA0_MASK (0xff << 0) +#define GLOBAL_REG_PRM_VC_SMPS_CMD_RA_CMDRA0_CREATE(x) (((x) & 0xff) << 0) +#define GLOBAL_REG_PRM_VC_SMPS_CMD_RA_CMDRA0_GET(r) (r & 0xff) +#define GLOBAL_REG_PRM_VC_SMPS_CMD_RA_CMDRA1_MASK (0xff << 16) +#define GLOBAL_REG_PRM_VC_SMPS_CMD_RA_CMDRA1_CREATE(x) (((x) & 0xff) << 16) +#define GLOBAL_REG_PRM_VC_SMPS_CMD_RA_CMDRA1_GET(r) (((r) >> 16 ) & 0xff) + + ioport32_t cmd_val_0; +#define GLOBAL_REG_PRM_VC_CMD_VAL_0_ON_MASK (0xff << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_0_ON_CREATE(x) (((x) & 0xff) << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_0_ON_GET(r) (((x) >> 24) & 0xff) +#define GLOBAL_REG_PRM_VC_CMD_VAL_0_ONLP_MASK (0xff << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_0_ONLP_CREATE(x) (((x) & 0xff) << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_0_ONLP_GET(r) (((x) >> 24) & 0xff) +#define GLOBAL_REG_PRM_VC_CMD_VAL_0_RET_MASK (0xff << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_0_RET_CREATE(x) (((x) & 0xff) << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_0_RET_GET(r) (((x) >> 24) & 0xff) +#define GLOBAL_REG_PRM_VC_CMD_VAL_0_OFF_MASK (0xff << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_0_OFF_CREATE(x) (((x) & 0xff) << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_0_OFF_GET(r) (((x) >> 24) & 0xff) + + ioport32_t cmd_val_1; +#define GLOBAL_REG_PRM_VC_CMD_VAL_1_ON_MASK (0xff << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_1_ON_CREATE(x) (((x) & 0xff) << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_1_ON_GET(r) (((x) >> 24) & 0xff) +#define GLOBAL_REG_PRM_VC_CMD_VAL_1_ONLP_MASK (0xff << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_1_ONLP_CREATE(x) (((x) & 0xff) << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_1_ONLP_GET(r) (((x) >> 24) & 0xff) +#define GLOBAL_REG_PRM_VC_CMD_VAL_1_RET_MASK (0xff << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_1_RET_CREATE(x) (((x) & 0xff) << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_1_RET_GET(r) (((x) >> 24) & 0xff) +#define GLOBAL_REG_PRM_VC_CMD_VAL_1_OFF_MASK (0xff << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_1_OFF_CREATE(x) (((x) & 0xff) << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_1_OFF_GET(r) (((x) >> 24) & 0xff) + + ioport32_t ch_conf; +#define GLOBAL_REG_PRM_VC_CH_CONF_CMD1_FLAG (1 << 20) +#define GLOBAL_REG_PRM_VC_CH_CONF_RACEN1_FLAG (1 << 19) +#define GLOBAL_REG_PRM_VC_CH_CONF_RAC1_FLAG (1 << 18) +#define GLOBAL_REG_PRM_VC_CH_CONF_RAV1_FLAG (1 << 17) +#define GLOBAL_REG_PRM_VC_CH_CONF_SA1_FLAG (1 << 16) +#define GLOBAL_REG_PRM_VC_CH_CONF_CMD0_FLAG (1 << 4) +#define GLOBAL_REG_PRM_VC_CH_CONF_RACEN0_FLAG (1 << 3) +#define GLOBAL_REG_PRM_VC_CH_CONF_RAC0_FLAG (1 << 2) +#define GLOBAL_REG_PRM_VC_CH_CONF_RAV0_FLAG (1 << 1) +#define GLOBAL_REG_PRM_VC_CH_CONF_SA0_FLAG (1 << 0) + + ioport32_t i2c_cfg; +#define GLOBAL_REG_PRM_VC_I2C_CFG_HSMASTER_FLAG (1 << 5) +#define GLOBAL_REG_PRM_VC_I2C_CFG_SREN_FLAG (1 << 4) +#define GLOBAL_REG_PRM_VC_I2C_CFG_HSEN_FLAG (1 << 3) +#define GLOBAL_REG_PRM_VC_I2C_CFG_MCODE_MASK (0x3 << 0) +#define GLOBAL_REG_PRM_VC_I2C_CFG_MCODE_CREATE(x) ((x) & 0x3) +#define GLOBAL_REG_PRM_VC_I2C_CFG_MCODE_GET(r) ((r) & 0x3) + + ioport32_t bypass_val; +#define GLOBAL_REG_PRM_VC_BYPASS_VAL_VALID_FLAG (1 << 24) +#define GLOBAL_REG_PRM_VC_BYPASS_VAL_DATA_MASK (0xff << 16) +#define GLOBAL_REG_PRM_VC_BYPASS_VAL_DATA_CREATE(x) (((x) & 0xff) << 16) +#define GLOBAL_REG_PRM_VC_BYPASS_VAL_DATA_GET(r) (((r) >> 16) & 0xff) +#define GLOBAL_REG_PRM_VC_BYPASS_VAL_REGADDR_MASK (0xff << 8) +#define GLOBAL_REG_PRM_VC_BYPASS_VAL_REGADDR_CREATE(x) (((x) & 0xff) << 8) +#define GLOBAL_REG_PRM_VC_BYPASS_VAL_REGADDR_GET(r) (((r) >> 8) & 0xff) +#define GLOBAL_REG_PRM_VC_BYPASS_VAL_SLAVEADDR_MASK (0x7f << 0) +#define GLOBAL_REG_PRM_VC_BYPASS_VAL_SLAVEADDR_CREATE(x) (((x) & 0x7f) << 0) +#define GLOBAL_REG_PRM_VC_BYPASS_VAL_SLAVEADDR_GET(r) (((r) >> 0) & 0x7f) + } vc; + + PADD32[4]; + ioport32_t rstctrl; +#define GLOBAL_REG_PRM_RSTCTRL_RST_DPLL3_FLAG (1 << 2) +#define GLOBAL_REG_PRM_RSTCTRL_RST_GS_FLAG (1 << 1) + + ioport32_t rsttime; +#define GLOBAL_REG_PRM_RSTTIME_RSTTIME2_MASK (0x1f << 8) +#define GLOBAL_REG_PRM_RSTTIME_RSTTIME2_CREATE(x) (((x) & 0x1f) << 8) +#define GLOBAL_REG_PRM_RSTTIME_RSTTIME2_GET(r) (((r) >> 8) & 0x1f) +#define GLOBAL_REG_PRM_RSTTIME_RSTTIME1_MASK (0xff << 0) +#define GLOBAL_REG_PRM_RSTTIME_RSTTIME1_CREATE(x) (((x) & 0xff) << 0) +#define GLOBAL_REG_PRM_RSTTIME_RSTTIME1_GET(r) (((r) >> 0) & 0xff) + + ioport32_t rstst; +#define GLOBAL_REG_PRM_RSTST_ICECRUSHER_RST_FLAG (1 << 10) +#define GLOBAL_REG_PRM_RSTST_ICEPICK_RST_FLAG (1 << 9) +#define GLOBAL_REG_PRM_RSTST_VDD2_VOLTAGE_MGR_RST_FLAG (1 << 8) +#define GLOBAL_REG_PRM_RSTST_VDD1_VOLTAGE_MGR_RST_FLAG (1 << 7) +#define GLOBAL_REG_PRM_RSTST_EXTERNAL_WARM_REST_FLAG (1 << 6) +#define GLOBAL_REG_PRM_RSTST_MPU_WD_RST_FLAG (1 << 4) +#define GLOBAL_REG_PRM_RSTST_GLOBAL_SW_RST_FLAG (1 << 1) +#define GLOBAL_REG_PRM_RSTST_GLOABL_COLD_RST_FLAG (1 << 0) + + PADD32; + ioport32_t volctrl; +#define GLOBAL_REG_PRM_VOLCTRL_SEL_VMODE_FLAG (1 << 4) +#define GLOBAL_REG_PRM_VOLCTRL_SEL_OFF_FLAG (1 << 3) +#define GLOBAL_REG_PRM_VOLCTRL_AUTO_OFF_FLAG (1 << 2) +#define GLOBAL_REG_PRM_VOLCTRL_AUTO_RET_FLAG (1 << 1) +#define GLOBAL_REG_PRM_VOLCTRL_AUTO_SLEEP_FLAG (1 << 0) + + ioport32_t sram_pcharge; +#define GLOBAL_REG_PRM_SRAM_PCHARGE_PCHARGE_TIME_MASK (0xff) +#define GLOBAL_REG_PRM_SRAM_PCHARGE_PCHARGE_TIME_CREATE(x) ((x) & 0xff) +#define GLOBAL_REG_PRM_SRAM_PCHARGE_PCHARGE_TIME_GET(r) ((r) & 0xff) + + PADD32[2]; + ioport32_t clksrc_ctrl; +#define GLOBAL_REG_PRM_CLKSRC_CTRL_DPLL4_CLKINP_DIV_65_FLAG (1 << 8) +#define GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKDIV_MASK (0x3 << 6) +#define GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKDIV_1 (0x1 << 6) +#define GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKDIV_2 (0x2 << 6) +#define GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKDIV_GET(r) (((r) >> 6) & 0x3) +#define GLOBAL_REG_PRM_CLKSRC_CTRL_AUTOEXTCLKMODE_MASK (0x3 << 3) +#define GLOBAL_REG_PRM_CLKSRC_CTRL_AUTOEXTCLKMODE_ON (0x0 << 3) +#define GLOBAL_REG_PRM_CLKSRC_CTRL_AUTOEXTCLKMODE_SLEEP (0x1 << 3) +#define GLOBAL_REG_PRM_CLKSRC_CTRL_AUTOEXTCLKMODE_RET (0x2 << 3) +#define GLOBAL_REG_PRM_CLKSRC_CTRL_AUTOEXTCLKMODE_OFF (0x3 << 3) +#define GLOBAL_REG_PRM_CLKSRC_CTRL_AUTOEXTCLKMODE_GET(r) (((r) >> 3) & 0x3) +#define GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKSEL_MASK (0x3 << 0) +#define GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKSEL_BYPASS (0x0 << 0) +#define GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKSEL_OSCILLATOR (0x1 << 0) +#define GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKSEL_UNKNOWN (0x3 << 0) +#define GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKSEL_GET(r) (((r) >> 0) & 0x3) + + PADD32[3]; + const ioport32_t obs; +#define GLOBAL_REG_PRM_OBS_OBS_BUS_MASK (0x3ff) + + PADD32[3]; + ioport32_t voltsetup1; +#define GLOBAL_REG_PRM_VOLTSETUP1_SETUPTIME2_MASK (0xff << 16) +#define GLOBAL_REG_PRM_VOLTSETUP1_SETUPTIME2_CREATE(x) (((x) & 0xff) << 16) +#define GLOBAL_REG_PRM_VOLTSETUP1_SETUPTIME2_GET(r) (((r) >> 16) & 0xff) +#define GLOBAL_REG_PRM_VOLTSETUP1_SETUPTIME1_MASK (0xff << 0) +#define GLOBAL_REG_PRM_VOLTSETUP1_SETUPTIME1_CREATE(x) (((x) & 0xff) << 0) +#define GLOBAL_REG_PRM_VOLTSETUP1_SETUPTIME1_GET(r) (((r) >> 0) & 0xff) + + ioport32_t voltoffset; +#define GLOBAL_REG_PRM_VOLTOFFSET_OFFSET_TIME_MASK (0xffff << 0) +#define GLOBAL_REG_PRM_VOLTOFFSET_OFFSET_TIME_CREATE(x) (((x) & 0xffff) << 0) +#define GLOBAL_REG_PRM_VOLTOFFSET_OFFSET_TIME_GET(r) (((r) >> 0) & 0xffff) + + ioport32_t clksetup; +#define GLOBAL_REG_PRM_CLKSETUP_SETUP_TIME_MASK (0xffff << 0) +#define GLOBAL_REG_PRM_CLKSETUP_SETUP_TIME_CREATE(x) (((x) & 0xffff) << 0) +#define GLOBAL_REG_PRM_CLKSETUP_SETUP_TIME_GET(r) (((r) >> 0) & 0xffff) + + ioport32_t polctrl; +#define GLOBAL_REG_PRM_POLCTRL_OFFMODE_POL_FLAG (1 << 3) +#define GLOBAL_REG_PRM_POLCTRL_CLKOUT_POL_FLAG (1 << 2) +#define GLOBAL_REG_PRM_POLCTRL_CLKREG_POL_FLAG (1 << 1) +#define GLOBAL_REG_PRM_POLCTRL_EXTVOL_POL_FLAG (1 << 0) + + ioport32_t voltsetup2; +#define GLOBAL_REG_PRM_VOLTSETUP2_OFFMODESETUPTIME_MASK (0xffff << 0) +#define GLOBAL_REG_PRM_VOLTSETUP2_OFFMODESETUPTIME_CREATE(x) (((x) & 0xffff) << 0) +#define GLOBAL_REG_PRM_VOLTSETUP2_OFFMODESETUPTIME_GET(r) (((r) >> 0) & 0xffff) + + PADD32[3]; + struct { + ioport32_t config; +#define GLOBAL_REG_PRM_VP_CONFIG_ERROROFFSET_MASK (0xff << 24) +#define GLOBAL_REG_PRM_VP_CONFIG_ERROROFFSET_CREATE(x) (((x) & 0xff) << 24) +#define GLOBAL_REG_PRM_VP_CONFIG_ERROROFFSET_GET(r) (((r) >> 0xff << 24) +#define GLOBAL_REG_PRM_VP_CONFIG_ERRORGAIN_MASK (0xff << 16) +#define GLOBAL_REG_PRM_VP_CONFIG_ERRORGAIN_CREATE(x) (((x) & 0xff) << 16) +#define GLOBAL_REG_PRM_VP_CONFIG_ERRORGAIN_GET(r) (((r) >> 0xff << 16) +#define GLOBAL_REG_PRM_VP_CONFIG_INITVOLTAGE_MASK (0xff << 8) +#define GLOBAL_REG_PRM_VP_CONFIG_INITVOLTAGE_CREATE(x) (((x) & 0xff) << 8) +#define GLOBAL_REG_PRM_VP_CONFIG_INITVOLTAGE_GET(r) (((r) >> 0xff << 8) +#define GLOBAL_REG_PRM_VP_CONFIG_TIMEOUTEN_FLAG (1 << 3) +#define GLOBAL_REG_PRM_VP_CONFIG_INITVDD_FLAG (1 << 2) +#define GLOBAL_REG_PRM_VP_CONFIG_FORCEUPDATE_FLAG (1 << 1) +#define GLOBAL_REG_PRM_VP_CONFIG_VPENABLE_FLAG (1 << 0) + + ioport32_t vstepmin; +#define GLOBAL_REG_PRM_VP_VSTEPMIN_SMPSWAITTIMEMIN_MASK (0xffff << 8) +#define GLOBAL_REG_PRM_VP_VSTEPMIN_SMPSWAITTIMEMIN_CREATE(x) (((x)0xffff << 8) +#define GLOBAL_REG_PRM_VP_VSTEPMIN_SMPSWAITTIMEMIN_GET(r) (((r) >> 8) & 0xffff) +#define GLOBAL_REG_PRM_VP_VSTEPMIN_VSTEPMIN_MASK (0xff << 0) +#define GLOBAL_REG_PRM_VP_VSTEPMIN_VSTEPMIN_CREATE(x) (((x)0xff << 0) +#define GLOBAL_REG_PRM_VP_VSTEPMIN_VSTEPMIN_GET(r) (((r) >> 0) & 0xff) + + ioport32_t vstepmax; +#define GLOBAL_REG_PRM_VP_VSTEPMAX_SMPSWAITTIMEMIN_MASK (0xffff << 8) +#define GLOBAL_REG_PRM_VP_VSTEPMAX_SMPSWAITTIMEMIN_CREATE(x) (((x)0xffff << 8) +#define GLOBAL_REG_PRM_VP_VSTEPMAX_SMPSWAITTIMEMIN_GET(r) (((r) >> 8) & 0xffff) +#define GLOBAL_REG_PRM_VP_VSTEPMAX_VSTEPMIN_MASK (0xff << 0) +#define GLOBAL_REG_PRM_VP_VSTEPMAX_VSTEPMIN_CREATE(x) (((x)0xff << 0) +#define GLOBAL_REG_PRM_VP_VSTEPMAX_VSTEPMIN_GET(r) (((r) >> 0) & 0xff) + + ioport32_t vlimitto; +#define GLOBAL_REG_PRM_VP_VLIMITTO_VDDMAX_MASK (0xff << 24) +#define GLOBAL_REG_PRM_VP_VLIMITTO_VDDMAX_CREATE(x) (((x)0xff << 24) +#define GLOBAL_REG_PRM_VP_VLIMITTO_VDDMAX_GET(r) (((r) >> 24) & 0xff) +#define GLOBAL_REG_PRM_VP_VLIMITTO_VDDMIN_MASK (0xff << 16) +#define GLOBAL_REG_PRM_VP_VLIMITTO_VDDMIN_CREATE(x) (((x)0xff << 16) +#define GLOBAL_REG_PRM_VP_VLIMITTO_VDDMIN_GET(r) (((r) >> 16) & 0xff) +#define GLOBAL_REG_PRM_VP_VLIMITTO_TIMEOUT_MASK (0xffff << 0) +#define GLOBAL_REG_PRM_VP_VLIMITTO_TIMEOUT_CREATE(x) (((x)0xffff << 0) +#define GLOBAL_REG_PRM_VP_VLIMITTO_TIMEOUT_GET(r) (((r) >> 0) & 0xffff) + + const ioport32_t voltage; +#define GLOBAL_REG_PRM_VP_VOLTAGE_VPVOLTAGE_MASK (0xff) +#define GLOBAL_REG_PRM_VP_VOLTAGE_VPVOLTAGE_GET(r) ((r) & 0xff) + + const ioport32_t status; +#define GLOBAL_REG_PRM_VP_STATUS_VPINIDLE_FLAG (1 << 0) + + PADD32[2]; + } vp[2]; + + ioport32_t ldo_abb_setup; +#define GLOBAL_REG_PRM_LDO_ABB_SETUP_SR2_IN_TRANSITION (1 << 6) +#define GLOBAL_REG_PRM_LDO_ABB_SETUP_SR2_STATUS_MASK (0x3 << 3) +#define GLOBAL_REG_PRM_LDO_ABB_SETUP_SR2_STATUS_BYPASS (0x0 << 3) +#define GLOBAL_REG_PRM_LDO_ABB_SETUP_SR2_STATUS_FBB (0x2 << 3) +#define GLOBAL_REG_PRM_LDO_ABB_SETUP_SR2_OPP_CHANGE_FLAG (1 << 2) +#define GLOBAL_REG_PRM_LDO_ABB_SETUP_OPP_SEL_MASK (0x3 << 0) +#define GLOBAL_REG_PRM_LDO_ABB_SETUP_OPP_SEL_DEFAULT (0x0 << 0) +#define GLOBAL_REG_PRM_LDO_ABB_SETUP_OPP_SEL_FAST (0x1 << 0) +#define GLOBAL_REG_PRM_LDO_ABB_SETUP_OPP_SEL_NOMINAL (0x2 << 0) +#define GLOBAL_REG_PRM_LDO_ABB_SETUP_OPP_SEL_SLOW (0x3 << 0) + + ioport32_t ldo_abb_ctrl; +#define GLOBAL_REG_PRM_LDO_ABB_CTRL_SR2_WTCNT_VALUE_MASK (0xff << 8) +#define GLOBAL_REG_PRM_LDO_ABB_CTRL_SR2_WTCNT_VALUE_CREATE(x) (((x) & 0xff) << 8) +#define GLOBAL_REG_PRM_LDO_ABB_CTRL_SR2_WTCNT_VALUE_GET(r) (((r) >> 8) & 0xff) +#define GLOBAL_REG_PRM_LDO_ABB_CTRL_ACTIVE_FBB_SEL_FLAG (1 << 2) +#define GLOBAL_REG_PRM_LDO_ABB_CTRL_SR2EN (1 << 0) +} global_reg_prm_regs_t; + +#endif +/** + * @} + */ Index: uspace/drv/platform/amdm37x/prm/usbhost.h =================================================================== --- uspace/drv/platform/amdm37x/prm/usbhost.h (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) +++ uspace/drv/platform/amdm37x/prm/usbhost.h (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup amdm37xdrvprm + * @{ + */ +/** @file + * @brief Clock Control Clock Management IO register structure. + */ +#ifndef AMDM37X_PRM_CLOCK_CONTROL_H +#define AMDM37X_PRM_CLOCK_CONTROL_H +#include +#include + +/* AM/DM37x TRM p.536 and p.589 */ +#define CLOCK_CONTROL_CM_BASE_ADDRESS 0x48307400 +#define CLOCK_CONTROL_CM_SIZE 8192 + +/** Clock control PRM register map + * + * Periph DPLL == DPLL4 + * Core DPLL == DPLL3 + */ +typedef struct { + PADD32[22]; + ioport32_t rm_rstst; +#define USBHOST_PRM_RM_RSTST_COREDOMAINWKUP_RST_FLAG (1 << 3) +#define USBHOST_PRM_RM_RSTST_DOMAINWKUP_RST_FLAG (1 << 2) +#define USBHOST_PRM_RM_RSTST_GLOBALWARM_RST_FLAG (1 << 1) +#define USBHOST_PRM_RM_RSTST_GLOBALCOLD_RST_FLAG (1 << 0) + + PADD32[18]; + ioport32_t pm_wken; +#define USBHOST_PRM_PM_WKEN_EN_USBHOST_FLAG (1 << 0) + + ioport32_t pm_mpugrpsel; +#define USBHOST_PRM_PM_MPUGRPSEL_GRPSEL_USBHOST_FLAG (1 << 0) + + ioport32_t pm_iva2grpsel; +#define USBHOST_PRM_PM_IVA2GRPSEL_GRPSEL_USBHOST_FLAG (1 << 0) + + PADD32; + ioport32_t pm_wkst; +#define USBHOST_PRM_PM_WKST_ST_USBHOST_FLAG (1 << 0) + + PADD32[5]; + ioport32_t pm_wkdep; +#define USBHOST_PRM_PM_WKDEP_EN_WKUP_FLAG (1 << 4) +#define USBHOST_PRM_PM_WKDEP_EN_IVA2_FLAG (1 << 2) +#define USBHOST_PRM_PM_WKDEP_EN_MPU_FLAG (1 << 1) +#define USBHOST_PRM_PM_WKDEP_EN_CORE_FLAG (1 << 0) + + PADD32[5]; + ioport32_t pm_pwstctrl; +#define USBHOST_PRM_PM_PWSTCTRL_MEMONSTATE_MASK (0x3 << 16) +#define USBHOST_PRM_PM_PWSTCTRL_MEMONSTATE_ALWAYS_ON (0x3 << 16) +#define USBHOST_PRM_PM_PWSTCTRL_MEMRETSTATE_FLAG (1 << 8) +#define USBHOST_PRM_PM_PWSTCTRL_SAVEANDRESTORE_FLAG (1 << 4) +#define USBHOST_PRM_PM_PWSTCTRL_LOGICRESTATE_FLAG (1 << 2) +#define USBHOST_PRM_PM_PWSTCTRL_POWERSTATE_MASK (0x3 << 0) +#define USBHOST_PRM_PM_PWSTCTRL_POWERSTATE_OFF (0x0 << 0) +#define USBHOST_PRM_PM_PWSTCTRL_POWERSTATE_RETENTION (0x1 << 0) +#define USBHOST_PRM_PM_PWSTCTRL_POWERSTATE_ON (0x3 << 0) + + const ioport32_t pm_pwstst; +#define USBHOST_PRM_PM_PWSTST_INTRANSITION_FLAG (1 << 20) +#define USBHOST_PRM_PM_PWSTST_POWERSTATEST_MASK (0x3 << 0) +#define USBHOST_PRM_PM_PWSTST_POWERSTATEST_OFF (0x0 << 0) +#define USBHOST_PRM_PM_PWSTST_POWERSTATEST_RETENTION (0x1 << 0) +#define USBHOST_PRM_PM_PWSTST_POWERSTATEST_INACTIVE (0x2 << 0) +#define USBHOST_PRM_PM_PWSTST_POWERSTATEST_ON (0x3 << 0) + + ioport32_t pm_prepwstst; +#define USBHOST_PRM_PM_PREPWSTST_LASTPOWERSTATEENTERED_MASK (0x3 << 0) +#define USBHOST_PRM_PM_PREPWSTST_LASTPOWERSTATEENTERED_OFF (0x0 << 0) +#define USBHOST_PRM_PM_PREPWSTST_LASTPOWERSTATEENTERED_RETENTION (0x1 << 0) +#define USBHOST_PRM_PM_PREPWSTST_LASTPOWERSTATEENTERED_INACTIVE (0x2 << 0) +#define USBHOST_PRM_PM_PREPWSTST_LASTPOWERSTATEENTERED_ON (0x3 << 0) + +} usbhost_prm_regs_t; + +#endif +/** + * @} + */ + Index: uspace/drv/platform/amdm37x/uhh.h =================================================================== --- uspace/drv/platform/amdm37x/uhh.h (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) +++ uspace/drv/platform/amdm37x/uhh.h (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup amdm37xdrvuhh + * @{ + */ +/** @file + * @brief UHH IO register structure. + */ +#ifndef AMDM37x_UHH_H +#define AMDM37x_UHH_H +#include +#include + +#define AMDM37x_UHH_BASE_ADDRESS 0x48064000 +#define AMDM37x_UHH_SIZE 1024 + +typedef struct { + const ioport32_t revision; +#define UHH_REVISION_MINOR_MASK 0x0f +#define UHH_REVISION_MAJOR_MASK 0xf0 + + PADD32[3]; + ioport32_t sysconfig; +#define UHH_SYSCONFIG_AUTOIDLE_FLAG (1 << 0) +#define UHH_SYSCONFIG_SOFTRESET_FLAG (1 << 1) +#define UHH_SYSCONFIG_ENWAKEUP_FLAG (1 << 2) +#define UHH_SYSCONFIG_SIDLE_MODE_MASK (0x3 << 3) +#define UHH_SYSCONFIG_SIDLE_MODE_FORCE (0x0 << 3) +#define UHH_SYSCONFIG_SIDLE_MODE_NO (0x1 << 3) +#define UHH_SYSCONFIG_SIDLE_MODE_SMART (0x2 << 3) +#define UHH_SYSCONFIG_CLOCKACTIVITY_FLAG (1 << 8) +#define UHH_SYSCONFIG_MIDLE_MODE_MASK (0x3 << 12) +#define UHH_SYSCONFIG_MIDLE_MODE_FORCE (0x0 << 12) +#define UHH_SYSCONFIG_MIDLE_MODE_NO (0x1 << 12) +#define UHH_SYSCONFIG_MIDLE_MODE_SMART (0x2 << 12) + + const ioport32_t sysstatus; +#define UHH_SYSSTATUS_RESETDONE_FLAG (1 << 0) +#define UHH_SYSSTATUS_OHCI_RESETDONE_FLAG (1 << 1) +#define UHH_SYSSTATUS_EHCI_RESETDONE_FLAG (1 << 2) + + PADD32[10]; + ioport32_t hostconfig; +#define UHH_HOSTCONFIG_P1_ULPI_BYPASS_FLAG (1 << 0) +#define UHH_HOSTCONFIG_AUTOPPD_ON_OVERCUR_EN_FLAG (1 << 1) +#define UHH_HOSTCONFIG_ENA_INCR4_FLAG (1 << 2) +#define UHH_HOSTCONFIG_ENA_INCR8_FLAG (1 << 3) +#define UHH_HOSTCONFIG_ENA_INCR16_FLA (1 << 4) +#define UHH_HOSTCONFIG_ENA_INCR_ALIGN_FLAG (1 << 5) +#define UHH_HOSTCONFIG_P1_CONNECT_STATUS_FLAG (1 << 8) +#define UHH_HOSTCONFIG_P2_CONNECT_STATUS_FLAG (1 << 9) +#define UHH_HOSTCONFIG_P3_CONNECT_STATUS_FLAG (1 << 10) +#define UHH_HOSTCONFIG_P2_ULPI_BYPASS_FLAG (1 << 11) +#define UHH_HOSTCONFIG_P3_ULPI_BYPASS_FLAG (1 << 12) + + ioport32_t debug_csr; +#define UHH_DEBUG_CSR_EHCI_FLADJ_MASK (0x3f << 0) +#define UHH_DEBUG_CSR_EHCI_FLADJ(x) ((x) & 0x3f) +#define UHH_DEBUG_CSR_EHCI_SIMULATION_MODE_FLAG (1 << 6) +#define UHH_DEBUG_CSR_OHCI_CNTSEL_FLAG (1 << 7) +#define UHH_DEBUG_CSR_OHCI_GLOBAL_SUSPEND_FLAG (1 << 16) +#define UHH_DEBUG_CSR_OHCI_CCS1_FLAG (1 << 17) +#define UHH_DEBUG_CSR_OHCI_CCS2_FLAG (1 << 18) +#define UHH_DEBUG_CSR_OHCI_CCS3_FLAG (1 << 19) + +} uhh_regs_t; + +#endif +/** + * @} + */ Index: uspace/drv/platform/amdm37x/usbtll.h =================================================================== --- uspace/drv/platform/amdm37x/usbtll.h (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) +++ uspace/drv/platform/amdm37x/usbtll.h (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup amdm37xdrvusbtll + * @{ + */ +/** @file + * @brief USBTLL IO register structure. + */ +#ifndef AMDM37x_USBTLL_H +#define AMDM37x_USBTLL_H +#include +#include + +#define AMDM37x_USBTLL_BASE_ADDRESS 0x48062000 +#define AMDM37x_USBTLL_SIZE 4096 + +typedef struct { + const ioport32_t revision; +#define TLL_REVISION_MINOR_MASK 0x0f +#define TLL_REVISION_MAJOR_MASK 0xf0 + + PADD32[3]; + ioport32_t sysconfig; +#define TLL_SYSCONFIG_AUTOIDLE_FLAG (1 << 0) +#define TLL_SYSCONFIG_SOFTRESET_FLAG (1 << 1) +#define TLL_SYSCONFIG_ENWAKEUP_FLAG (1 << 2) +#define TLL_SYSCONFIG_SIDLE_MODE_MASK (0x3 << 3) +#define TLL_SYSCONFIG_SIDLE_MODE_FORCE (0x0 << 3) +#define TLL_SYSCONFIG_SIDLE_MODE_NO (0x1 << 3) +#define TLL_SYSCONFIG_SIDLE_MODE_SMART (0x2 << 3) +#define TLL_SYSCONFIG_CLOCKACTIVITY_FLAG (1 << 8) + + const ioport32_t sysstatus; +#define TLL_SYSSTATUS_RESET_DONE_FLAG (1 << 0) + + const ioport32_t irqstatus; +#define TLL_IRQSTATUS_FCLK_START_FLAG (1 << 0) +#define TLL_IRQSTATUS_FCLK_END_FLAG (1 << 1) +#define TLL_IRQSTATUS_ACCESS_ERROR_FLAG (1 << 2) + + ioport32_t irqenable; +#define TLL_IRQSTATUS_FCLK_START_EN_FLAG (1 << 0) +#define TLL_IRQSTATUS_FCLK_END_EN_FLAG (1 << 1) +#define TLL_IRQSTATUS_ACCESS_ERROR_EN_FLAG (1 << 2) + + PADD32[4]; + ioport32_t shared_conf; +#define TLL_SHARED_CONF_FCLK_IS_ON_FLAG (1 << 0) +#define TLL_SHARED_CONF_FCLK_REQ_FLAG (1 << 1) +#define TLL_SHARED_CONF_USB_DIVRATIO_MASK (0x7 << 2) +#define TLL_SHARED_CONF_USB_DIVRATIO(x) (((x) & 0x7) << 2) +#define TLL_SHARED_CONF_USB_180D_SDR_EN_FLAG (1 << 5) +#define TLL_SHARED_CONF_USB_90D_DDR_EN_FLAG (1 << 6) + + PADD32[3]; + ioport32_t channel_conf[3]; +#define TLL_CHANNEL_CONF_CHANEN_FLAG (1 << 0) +#define TLL_CHANNEL_CONF_CHANMODE_MASK (0x3 << 1) +#define TLL_CHANNEL_CONF_CHANMODE_UTMI_ULPI_MODE (0x0 << 1) +#define TLL_CHANNEL_CONF_CHANMODE_UTMI_SERIAL_MODE (0x1 << 1) +#define TLL_CHANNEL_CONF_CHANMODE_UTMI_TRANS_MODE (0x2 << 1) +#define TLL_CHANNEL_CONF_CHANMODE_NO_MODE (0x3 << 1) +#define TLL_CHANNEL_CONF_UTMIISADEV_FLAG (1 << 3) +#define TLL_CHANNEL_CONF_TLLATTACH_FLAG (1 << 4) +#define TLL_CHANNEL_CONF_TLLCONNECT_FLAG (1 << 5) +#define TLL_CHANNEL_CONF_TLLFULLSPEED_FLAG (1 << 6) +#define TLL_CHANNEL_CONF_ULPIOUTCLKMODE_FLAG (1 << 7) +#define TLL_CHANNEL_CONF_ULPIDDRMODE_FLAG (1 << 8) +#define TLL_CHANNEL_CONF_UTMIAUTOIDLE_FLAG (1 << 9) +#define TLL_CHANNEL_CONF_ULPIAUTOIDLE_FLAG (1 << 10) +#define TLL_CHANNEL_CONF_ULPINOBITSTUFF_FLAG (1 << 11) +#define TLL_CHANNEL_CONF_CHRGVBUS_FLAG (1 << 15) +#define TLL_CHANNEL_CONF_DRVVBUS_FLAG (1 << 16) +#define TLL_CHANNEL_CONF_TESTEN_FLAG (1 << 17) +#define TLL_CHANNEL_CONF_TESTTXEN_FLAG (1 << 18) +#define TLL_CHANNEL_CONF_TESTTXDAT_FLAG (1 << 19) +#define TLL_CHANNEL_CONF_TESTTXSE0_FLAG (1 << 20) +#define TLL_CHANNEL_CONF_FSLSMODE_MASK (0xf << 24) +#define TLL_CHANNEL_CONF_FSLSMODE_6PIN_UNI_PHY_TX_DATSE0 (0x0 << 24) +#define TLL_CHANNEL_CONF_FSLSMODE_6PIN_UNI_PHY_TX_DPDM (0x1 << 24) +#define TLL_CHANNEL_CONF_FSLSMODE_3PIN_BIDI_PHY (0x2 << 24) +#define TLL_CHANNEL_CONF_FSLSMODE_4PIN_BIDI_PHY (0x3 << 24) +#define TLL_CHANNEL_CONF_FSLSMODE_6PIN_UNI_TLL_TX_DATSE0 (0x4 << 24) +#define TLL_CHANNEL_CONF_FSLSMODE_6PIN_UNI_TLL_TX_DPDM (0x5 << 24) +#define TLL_CHANNEL_CONF_FSLSMODE_3PIN_BIDI_TLL (0x6 << 24) +#define TLL_CHANNEL_CONF_FSLSMODE_4PIN_BIDI_TLL (0x7 << 24) +#define TLL_CHANNEL_CONF_FSLSMODE_2PIN_BIDI_TLL_DATSE0 (0xa << 24) +#define TLL_CHANNEL_CONF_FSLSMODE_2PIN_BIDI_TLL_DPDM (0xb << 24) + +#define TLL_CHANNEL_CONF_FSLSLINESTATE_MASK (0x3 << 28) +#define TLL_CHANNEL_CONF_FSLSLINESTATE_SE0 (0x0 << 28) +#define TLL_CHANNEL_CONF_FSLSLINESTATE_FS_J (0x1 << 28) +#define TLL_CHANNEL_CONF_FSLSLINESTATE_FS_K (0x2 << 28) +#define TLL_CHANNEL_CONF_FSLSLINESTATE_SE1 (0x3 << 28) + + /* The rest are 8bit ULPI registers */ +} tll_regs_t; + +#endif +/** + * @} + */ + Index: uspace/drv/platform/icp/Makefile =================================================================== --- uspace/drv/platform/icp/Makefile (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) +++ uspace/drv/platform/icp/Makefile (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -0,0 +1,37 @@ +# +# Copyright (c) 2014 Jiri Svoboda +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# - Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# - Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# - The name of the author may not be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +USPACE_PREFIX = ../../.. +LIBS = $(LIBDRV_PREFIX)/libdrv.a +EXTRA_CFLAGS += -I$(LIBDRV_PREFIX)/include +BINARY = icp + +SOURCES = \ + icp.c + +include $(USPACE_PREFIX)/Makefile.common Index: uspace/drv/platform/icp/icp.c =================================================================== --- uspace/drv/platform/icp/icp.c (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) +++ uspace/drv/platform/icp/icp.c (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -0,0 +1,261 @@ +/* + * Copyright (c) 2014 Jiri Svoboda + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @defgroup icp IntegratorCP platform driver. + * @brief HelenOS IntegratorCP platform driver. + * @{ + */ + +/** @file + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#define NAME "icp" + +enum { + icp_kbd_base = 0x18000000, + icp_kbd_irq = 3, + icp_mouse_base = 0x19000000, + icp_mouse_irq = 4 +}; + +typedef struct icp_fun { + hw_resource_list_t hw_resources; +} icp_fun_t; + +static int icp_dev_add(ddf_dev_t *dev); + +static driver_ops_t icp_ops = { + .dev_add = &icp_dev_add +}; + +static driver_t icp_driver = { + .name = NAME, + .driver_ops = &icp_ops +}; + +static hw_resource_t icp_kbd_res[] = { + { + .type = MEM_RANGE, + .res.mem_range = { + .address = icp_kbd_base, + .size = 9, + .relative = false, + .endianness = LITTLE_ENDIAN + } + }, + { + .type = INTERRUPT, + .res.interrupt = { + .irq = icp_kbd_irq + } + } +}; + +static hw_resource_t icp_mouse_res[] = { + { + .type = MEM_RANGE, + .res.mem_range = { + .address = icp_mouse_base, + .size = 9, + .relative = false, + .endianness = LITTLE_ENDIAN + } + }, + { + .type = INTERRUPT, + .res.interrupt = { + .irq = icp_mouse_irq + } + } +}; + +static pio_window_t icp_pio_window = { + .mem = { + .base = 0, + .size = -1 + } +}; + +static icp_fun_t icp_kbd_fun_proto = { + .hw_resources = { + sizeof(icp_kbd_res) / sizeof(icp_kbd_res[0]), + icp_kbd_res + }, +}; + +static icp_fun_t icp_mouse_fun_proto = { + .hw_resources = { + sizeof(icp_mouse_res) / sizeof(icp_mouse_res[0]), + icp_mouse_res + }, +}; + +/** Obtain function soft-state from DDF function node */ +static icp_fun_t *icp_fun(ddf_fun_t *fnode) +{ + return ddf_fun_data_get(fnode); +} + +static hw_resource_list_t *icp_get_resources(ddf_fun_t *fnode) +{ + icp_fun_t *fun = icp_fun(fnode); + + assert(fun != NULL); + return &fun->hw_resources; +} + +static bool icp_enable_interrupt(ddf_fun_t *fun) +{ + /* TODO */ + return false; +} + +static pio_window_t *icp_get_pio_window(ddf_fun_t *fnode) +{ + return &icp_pio_window; +} + +static hw_res_ops_t icp_hw_res_ops = { + .get_resource_list = &icp_get_resources, + .enable_interrupt = &icp_enable_interrupt, +}; + +static pio_window_ops_t icp_pio_window_ops = { + .get_pio_window = &icp_get_pio_window +}; + +static ddf_dev_ops_t icp_fun_ops = { + .interfaces = { + [HW_RES_DEV_IFACE] = &icp_hw_res_ops, + [PIO_WINDOW_DEV_IFACE] = &icp_pio_window_ops + } +}; + +static int icp_add_fun(ddf_dev_t *dev, const char *name, const char *str_match_id, + icp_fun_t *fun_proto) +{ + ddf_msg(LVL_NOTE, "Adding function '%s'.", name); + + ddf_fun_t *fnode = NULL; + int rc; + + /* Create new device. */ + fnode = ddf_fun_create(dev, fun_inner, name); + if (fnode == NULL) { + ddf_msg(LVL_ERROR, "Error creating function '%s'", name); + rc = ENOMEM; + goto error; + } + + icp_fun_t *fun = ddf_fun_data_alloc(fnode, sizeof(icp_fun_t)); + *fun = *fun_proto; + + /* Add match ID */ + rc = ddf_fun_add_match_id(fnode, str_match_id, 100); + if (rc != EOK) { + ddf_msg(LVL_ERROR, "Error adding match ID"); + goto error; + } + + /* Set provided operations to the device. */ + ddf_fun_set_ops(fnode, &icp_fun_ops); + + /* Register function. */ + if (ddf_fun_bind(fnode) != EOK) { + ddf_msg(LVL_ERROR, "Failed binding function %s.", name); + goto error; + } + + return EOK; + +error: + if (fnode != NULL) + ddf_fun_destroy(fnode); + + return rc; +} + +static int icp_add_functions(ddf_dev_t *dev) +{ + int rc; + + rc = icp_add_fun(dev, "kbd", "arm/pl050", &icp_kbd_fun_proto); + if (rc != EOK) + return rc; + + rc = icp_add_fun(dev, "mouse", "arm/pl050", &icp_mouse_fun_proto); + if (rc != EOK) + return rc; + + return EOK; +} + +/** Add device. */ +static int icp_dev_add(ddf_dev_t *dev) +{ + ddf_msg(LVL_NOTE, "icp_dev_add, device handle = %d", + (int)ddf_dev_get_handle(dev)); + + /* Register functions. */ + if (icp_add_functions(dev)) { + ddf_msg(LVL_ERROR, "Failed to add functions for ICP platform."); + } + + return EOK; +} + +int main(int argc, char *argv[]) +{ + int rc; + + printf(NAME ": HelenOS IntegratorCP platform driver\n"); + + rc = ddf_log_init(NAME); + if (rc != EOK) { + printf(NAME ": Failed initializing logging service"); + return 1; + } + + return ddf_driver_main(&icp_driver); +} + +/** + * @} + */ Index: uspace/drv/platform/icp/icp.ma =================================================================== --- uspace/drv/platform/icp/icp.ma (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) +++ uspace/drv/platform/icp/icp.ma (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -0,0 +1,1 @@ +10 platform/integratorcp Index: uspace/drv/platform/leon3/Makefile =================================================================== --- uspace/drv/platform/leon3/Makefile (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) +++ uspace/drv/platform/leon3/Makefile (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -0,0 +1,37 @@ +# +# Copyright (c) 2012 Jan Vesely +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# - Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# - Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# - The name of the author may not be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +USPACE_PREFIX = ../../.. +LIBS = $(LIBDRV_PREFIX)/libdrv.a +EXTRA_CFLAGS += -I$(LIBDRV_PREFIX)/include +BINARY = leon3 + +SOURCES = \ + leon3.c + +include $(USPACE_PREFIX)/Makefile.common Index: uspace/drv/platform/leon3/leon3.c =================================================================== --- uspace/drv/platform/leon3/leon3.c (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) +++ uspace/drv/platform/leon3/leon3.c (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -0,0 +1,195 @@ +/* + * Copyright (c) 2012 Jan Vesely + * Copyright (c) 2013 Jakub Klama + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @defgroup leon3 SPARC LEON3 platform driver. + * @brief HelenOS SPARC LEON3 platform driver. + * @{ + */ +/** @file + */ + +#include +#include +#include +#include +#include "leon3.h" + +#define NAME "leon3" + +typedef struct { + const char *name; + match_id_t match_id; + hw_resource_list_t hw_resources; +} leon3_fun_t; + +static hw_resource_t amba_res[] = { + { + .type = MEM_RANGE, + .res.mem_range = { + .address = AMBAPP_MASTER_AREA, + .size = AMBAPP_MASTER_SIZE, + .endianness = BIG_ENDIAN + } + }, + { + .type = MEM_RANGE, + .res.mem_range = { + .address = AMBAPP_SLAVE_AREA, + .size = AMBAPP_SLAVE_SIZE, + .endianness = BIG_ENDIAN, + } + } +}; + +static const leon3_fun_t leon3_func = { + .name = "leon_amba", + .match_id = { + .id = "leon_amba", + .score = 90 + }, + .hw_resources = { + .count = 2, + .resources = amba_res + } +}; + +static hw_resource_list_t *leon3_get_resources(ddf_fun_t *); +static bool leon3_enable_interrupt(ddf_fun_t *); + +static hw_res_ops_t fun_hw_res_ops = { + .get_resource_list = &leon3_get_resources, + .enable_interrupt = &leon3_enable_interrupt +}; + +static ddf_dev_ops_t leon3_fun_ops = { + .interfaces[HW_RES_DEV_IFACE] = &fun_hw_res_ops +}; + +static int leon3_add_fun(ddf_dev_t *dev, const leon3_fun_t *fun) +{ + assert(dev); + assert(fun); + + ddf_msg(LVL_DEBUG, "Adding new function '%s'.", fun->name); + + /* Create new device function. */ + ddf_fun_t *fnode = ddf_fun_create(dev, fun_inner, fun->name); + if (fnode == NULL) + return ENOMEM; + + /* Add match id */ + int ret = ddf_fun_add_match_id(fnode, fun->match_id.id, + fun->match_id.score); + if (ret != EOK) { + ddf_fun_destroy(fnode); + return ret; + } + + /* Allocate needed data */ + leon3_fun_t *rf = + ddf_fun_data_alloc(fnode, sizeof(leon3_fun_t)); + if (!rf) { + ddf_fun_destroy(fnode); + return ENOMEM; + } + *rf = *fun; + + /* Set provided operations to the device. */ + ddf_fun_set_ops(fnode, &leon3_fun_ops); + + /* Register function. */ + ret = ddf_fun_bind(fnode); + if (ret != EOK) { + ddf_msg(LVL_ERROR, "Failed binding function %s.", fun->name); + ddf_fun_destroy(fnode); + return ret; + } + + return EOK; +} + +/** Add the root device. + * + * @param dev Device which is root of the whole device tree + * (both of HW and pseudo devices). + * + * @return Zero on success, negative error number otherwise. + * + */ +static int leon3_dev_add(ddf_dev_t *dev) +{ + assert(dev); + + /* Register functions */ + if (leon3_add_fun(dev, &leon3_func) != EOK) { + ddf_msg(LVL_ERROR, "Failed to add %s function for " + "LEON3 platform.", leon3_func.name); + } + + return EOK; +} + +/** The root device driver's standard operations. */ +static driver_ops_t leon3_ops = { + .dev_add = &leon3_dev_add +}; + +/** The root device driver structure. */ +static driver_t leon3_driver = { + .name = NAME, + .driver_ops = &leon3_ops +}; + +static hw_resource_list_t *leon3_get_resources(ddf_fun_t *fnode) +{ + leon3_fun_t *fun = ddf_fun_data_get(fnode); + assert(fun != NULL); + + printf("leon3_get_resources() called\n"); + + return &fun->hw_resources; +} + +static bool leon3_enable_interrupt(ddf_fun_t *fun) +{ + // FIXME TODO + return false; +} + +int main(int argc, char *argv[]) +{ + printf("%s: HelenOS SPARC LEON3 platform driver\n", NAME); + ddf_log_init(NAME); + return ddf_driver_main(&leon3_driver); +} + +/** + * @} + */ Index: uspace/drv/platform/leon3/leon3.h =================================================================== --- uspace/drv/platform/leon3/leon3.h (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) +++ uspace/drv/platform/leon3/leon3.h (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2013 Jakub Klama + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup leon3drv + * @{ + */ +/** @file + * @brief LEON3 root device. + */ + +#ifndef LEON3_H +#define LEON3_H + +#define AMBAPP_MASTER_AREA 0xfffff000 +#define AMBAPP_SLAVE_AREA 0xfffff800 +#define AMBAPP_MASTER_SIZE 0x800 +#define AMBAPP_SLAVE_SIZE 0x800 + +#endif + +/** + * @} + */ Index: uspace/drv/platform/leon3/leon3.ma =================================================================== --- uspace/drv/platform/leon3/leon3.ma (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) +++ uspace/drv/platform/leon3/leon3.ma (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -0,0 +1,1 @@ +100 platform/leon3 Index: uspace/drv/platform/mac/Makefile =================================================================== --- uspace/drv/platform/mac/Makefile (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) +++ uspace/drv/platform/mac/Makefile (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -0,0 +1,37 @@ +# +# Copyright (c) 2010 Lenka Trochtova +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# - Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# - Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# - The name of the author may not be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +USPACE_PREFIX = ../../.. +LIBS = $(LIBDRV_PREFIX)/libdrv.a +EXTRA_CFLAGS += -I$(LIBDRV_PREFIX)/include +BINARY = mac + +SOURCES = \ + mac.c + +include $(USPACE_PREFIX)/Makefile.common Index: uspace/drv/platform/mac/mac.c =================================================================== --- uspace/drv/platform/mac/mac.c (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) +++ uspace/drv/platform/mac/mac.c (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -0,0 +1,190 @@ +/* + * Copyright (c) 2011 Martin Decky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @defgroup mac Mac platform driver. + * @brief HelenOS Mac platform driver. + * @{ + */ + +/** @file + */ + +#include +#include +#include +#include +#include + +#define NAME "mac" + +typedef struct { + hw_resource_list_t hw_resources; +} mac_fun_t; + +static hw_resource_t pci_conf_regs[] = { + { + .type = IO_RANGE, + .res.io_range = { + .address = 0xfec00000, + .size = 4, + .relative = false, + .endianness = LITTLE_ENDIAN + } + }, + { + .type = IO_RANGE, + .res.io_range = { + .address = 0xfee00000, + .size = 4, + .relative = false, + .endianness = LITTLE_ENDIAN + } + } +}; + +static mac_fun_t pci_data = { + .hw_resources = { + 2, + pci_conf_regs + } +}; + +static ddf_dev_ops_t mac_fun_ops; + +/** Obtain function soft-state from DDF function node */ +static mac_fun_t *mac_fun(ddf_fun_t *fnode) +{ + return ddf_fun_data_get(fnode); +} + +static bool mac_add_fun(ddf_dev_t *dev, const char *name, + const char *str_match_id, mac_fun_t *fun_proto) +{ + ddf_msg(LVL_DEBUG, "Adding new function '%s'.", name); + + ddf_fun_t *fnode = NULL; + int rc; + + /* Create new device. */ + fnode = ddf_fun_create(dev, fun_inner, name); + if (fnode == NULL) + goto failure; + + mac_fun_t *fun = ddf_fun_data_alloc(fnode, sizeof(mac_fun_t)); + *fun = *fun_proto; + + /* Add match ID */ + rc = ddf_fun_add_match_id(fnode, str_match_id, 100); + if (rc != EOK) + goto failure; + + /* Set provided operations to the device. */ + ddf_fun_set_ops(fnode, &mac_fun_ops); + + /* Register function. */ + if (ddf_fun_bind(fnode) != EOK) { + ddf_msg(LVL_ERROR, "Failed binding function %s.", name); + goto failure; + } + + return true; + +failure: + if (fnode != NULL) + ddf_fun_destroy(fnode); + + ddf_msg(LVL_ERROR, "Failed adding function '%s'.", name); + + return false; +} + +/** Get the root device. + * + * @param dev Device which is root of the whole device tree + * (both of HW and pseudo devices). + * + * @return Zero on success, negative error number otherwise. + * + */ +static int mac_dev_add(ddf_dev_t *dev) +{ +#if 0 + /* Register functions */ + if (!mac_add_fun(dev, "pci0", "intel_pci", &pci_data)) + ddf_msg(LVL_ERROR, "Failed to add functions for Mac platform."); +#else + (void)pci_data; + (void)mac_add_fun; +#endif + + return EOK; +} + +/** The root device driver's standard operations. */ +static driver_ops_t mac_ops = { + .dev_add = &mac_dev_add +}; + +/** The root device driver structure. */ +static driver_t mac_driver = { + .name = NAME, + .driver_ops = &mac_ops +}; + +static hw_resource_list_t *mac_get_resources(ddf_fun_t *fnode) +{ + mac_fun_t *fun = mac_fun(fnode); + assert(fun != NULL); + + return &fun->hw_resources; +} + +static bool mac_enable_interrupt(ddf_fun_t *fun) +{ + /* TODO */ + + return false; +} + +static hw_res_ops_t fun_hw_res_ops = { + .get_resource_list = &mac_get_resources, + .enable_interrupt = &mac_enable_interrupt +}; + +int main(int argc, char *argv[]) +{ + printf("%s: HelenOS Mac platform driver\n", NAME); + ddf_log_init(NAME); + mac_fun_ops.interfaces[HW_RES_DEV_IFACE] = &fun_hw_res_ops; + return ddf_driver_main(&mac_driver); +} + +/** + * @} + */ Index: uspace/drv/platform/mac/mac.ma =================================================================== --- uspace/drv/platform/mac/mac.ma (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) +++ uspace/drv/platform/mac/mac.ma (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -0,0 +1,1 @@ +10 platform/mac Index: uspace/drv/platform/malta/Makefile =================================================================== --- uspace/drv/platform/malta/Makefile (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) +++ uspace/drv/platform/malta/Makefile (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -0,0 +1,37 @@ +# +# Copyright (c) 2010 Lenka Trochtova +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# - Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# - Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# - The name of the author may not be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +USPACE_PREFIX = ../../.. +LIBS = $(LIBDRV_PREFIX)/libdrv.a +EXTRA_CFLAGS += -I$(LIBDRV_PREFIX)/include +BINARY = malta + +SOURCES = \ + malta.c + +include $(USPACE_PREFIX)/Makefile.common Index: uspace/drv/platform/malta/malta.c =================================================================== --- uspace/drv/platform/malta/malta.c (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) +++ uspace/drv/platform/malta/malta.c (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -0,0 +1,273 @@ +/* + * Copyright (c) 2010 Lenka Trochtova + * Copyright (c) 2013 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @defgroup malta Malta board platform driver. + * @brief HelenOS Malta board platform driver. + * @{ + */ + +/** @file + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#define NAME "malta" + +#define GT_BASE UINT32_C(0x1be00000) +#define GT_SIZE (2 * 1024 * 1024) + +#define GT_PCI_CMD 0xc00 +#define GT_PCI_CONFADDR 0xcf8 +#define GT_PCI_CONFDATA 0xcfc + +#define GT_PCI_CMD_MBYTESWAP 0x1 + +#define GT_PCI_MEMBASE UINT32_C(0x10000000) +#define GT_PCI_MEMSIZE UINT32_C(0x08000000) + +#define GT_PCI_IOBASE UINT32_C(0x18000000) +#define GT_PCI_IOSIZE UINT32_C(0x00200000) + +typedef struct malta_fun { + hw_resource_list_t hw_resources; + pio_window_t pio_window; +} malta_fun_t; + +static int malta_dev_add(ddf_dev_t *dev); +static void malta_init(void); + +/** The root device driver's standard operations. */ +static driver_ops_t malta_ops = { + .dev_add = &malta_dev_add +}; + +/** The root device driver structure. */ +static driver_t malta_driver = { + .name = NAME, + .driver_ops = &malta_ops +}; + +static hw_resource_t pci_conf_regs[] = { + { + .type = IO_RANGE, + .res.io_range = { + .address = GT_BASE + GT_PCI_CONFADDR, + .size = 4, + .relative = false, + .endianness = LITTLE_ENDIAN + } + }, + { + .type = IO_RANGE, + .res.io_range = { + .address = GT_BASE + GT_PCI_CONFDATA, + .size = 4, + .relative = false, + .endianness = LITTLE_ENDIAN + } + } +}; + +static malta_fun_t pci_data = { + .hw_resources = { + sizeof(pci_conf_regs) / sizeof(pci_conf_regs[0]), + pci_conf_regs + }, + .pio_window = { + .mem = { + .base = GT_PCI_MEMBASE, + .size = GT_PCI_MEMSIZE + }, + .io = { + .base = GT_PCI_IOBASE, + .size = GT_PCI_IOSIZE + } + } +}; + +/** Obtain function soft-state from DDF function node */ +static malta_fun_t *malta_fun(ddf_fun_t *fnode) +{ + return ddf_fun_data_get(fnode); +} + +static hw_resource_list_t *malta_get_resources(ddf_fun_t *fnode) +{ + malta_fun_t *fun = malta_fun(fnode); + + assert(fun != NULL); + return &fun->hw_resources; +} + +static bool malta_enable_interrupt(ddf_fun_t *fun) +{ + /* TODO */ + + return false; +} + +static pio_window_t *malta_get_pio_window(ddf_fun_t *fnode) +{ + malta_fun_t *fun = malta_fun(fnode); + + assert(fun != NULL); + return &fun->pio_window; +} + +static hw_res_ops_t fun_hw_res_ops = { + .get_resource_list = &malta_get_resources, + .enable_interrupt = &malta_enable_interrupt, +}; + +static pio_window_ops_t fun_pio_window_ops = { + .get_pio_window = &malta_get_pio_window +}; + +/* Initialized in malta_init() function. */ +static ddf_dev_ops_t malta_fun_ops; + +static bool +malta_add_fun(ddf_dev_t *dev, const char *name, const char *str_match_id, + malta_fun_t *fun_proto) +{ + ddf_msg(LVL_DEBUG, "Adding new function '%s'.", name); + + ddf_fun_t *fnode = NULL; + int rc; + + /* Create new device. */ + fnode = ddf_fun_create(dev, fun_inner, name); + if (fnode == NULL) + goto failure; + + malta_fun_t *fun = ddf_fun_data_alloc(fnode, sizeof(malta_fun_t)); + *fun = *fun_proto; + + /* Add match ID */ + rc = ddf_fun_add_match_id(fnode, str_match_id, 100); + if (rc != EOK) + goto failure; + + /* Set provided operations to the device. */ + ddf_fun_set_ops(fnode, &malta_fun_ops); + + /* Register function. */ + if (ddf_fun_bind(fnode) != EOK) { + ddf_msg(LVL_ERROR, "Failed binding function %s.", name); + goto failure; + } + + return true; + +failure: + if (fnode != NULL) + ddf_fun_destroy(fnode); + + ddf_msg(LVL_ERROR, "Failed adding function '%s'.", name); + + return false; +} + +static bool malta_add_functions(ddf_dev_t *dev) +{ + return malta_add_fun(dev, "pci0", "intel_pci", &pci_data); +} + +/** Get the root device. + * + * @param dev The device which is root of the whole device tree (both + * of HW and pseudo devices). + * @return Zero on success, negative error number otherwise. + */ +static int malta_dev_add(ddf_dev_t *dev) +{ + ioport32_t *gt; + uint32_t val; + int ret; + + ddf_msg(LVL_DEBUG, "malta_dev_add, device handle = %d", + (int)ddf_dev_get_handle(dev)); + + /* + * We need to disable byte swapping of the outgoing and incoming + * PCI data, because the PCI driver assumes no byte swapping behind + * the scenes and takes care of it itself. + */ + ret = pio_enable((void *) GT_BASE, GT_SIZE, (void **) >); + if (ret != EOK) + return ret; + val = uint32_t_le2host(pio_read_32( + >[GT_PCI_CMD / sizeof(ioport32_t)])); + val |= GT_PCI_CMD_MBYTESWAP; + pio_write_32( + >[GT_PCI_CMD / sizeof(ioport32_t)], host2uint32_t_le(val)); + + + /* Register functions. */ + if (!malta_add_functions(dev)) { + ddf_msg(LVL_ERROR, "Failed to add functions for the Malta platform."); + } + + return EOK; +} + +static void malta_init(void) +{ + ddf_log_init(NAME); + malta_fun_ops.interfaces[HW_RES_DEV_IFACE] = &fun_hw_res_ops; + malta_fun_ops.interfaces[PIO_WINDOW_DEV_IFACE] = &fun_pio_window_ops; +} + +int main(int argc, char *argv[]) +{ + printf(NAME ": HelenOS Malta platform driver\n"); + malta_init(); + return ddf_driver_main(&malta_driver); +} + +/** + * @} + */ Index: uspace/drv/platform/malta/malta.ma =================================================================== --- uspace/drv/platform/malta/malta.ma (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) +++ uspace/drv/platform/malta/malta.ma (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -0,0 +1,1 @@ +10 platform/malta Index: uspace/drv/platform/pc/Makefile =================================================================== --- uspace/drv/platform/pc/Makefile (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) +++ uspace/drv/platform/pc/Makefile (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -0,0 +1,37 @@ +# +# Copyright (c) 2010 Lenka Trochtova +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# - Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# - Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# - The name of the author may not be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +USPACE_PREFIX = ../../.. +LIBS = $(LIBDRV_PREFIX)/libdrv.a +EXTRA_CFLAGS += -I$(LIBDRV_PREFIX)/include +BINARY = pc + +SOURCES = \ + pc.c + +include $(USPACE_PREFIX)/Makefile.common Index: uspace/drv/platform/pc/pc.c =================================================================== --- uspace/drv/platform/pc/pc.c (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) +++ uspace/drv/platform/pc/pc.c (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -0,0 +1,236 @@ +/* + * Copyright (c) 2010 Lenka Trochtova + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @defgroup pc PC platform driver. + * @brief HelenOS PC platform driver. + * @{ + */ + +/** @file + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#define NAME "pc" + +typedef struct pc_fun { + hw_resource_list_t hw_resources; + pio_window_t pio_window; +} pc_fun_t; + +static int pc_dev_add(ddf_dev_t *dev); +static void pc_init(void); + +/** The root device driver's standard operations. */ +static driver_ops_t pc_ops = { + .dev_add = &pc_dev_add +}; + +/** The root device driver structure. */ +static driver_t pc_driver = { + .name = NAME, + .driver_ops = &pc_ops +}; + +static hw_resource_t pci_conf_regs[] = { + { + .type = IO_RANGE, + .res.io_range = { + .address = 0xCF8, + .size = 4, + .relative = false, + .endianness = LITTLE_ENDIAN + } + }, + { + .type = IO_RANGE, + .res.io_range = { + .address = 0xCFC, + .size = 4, + .relative = false, + .endianness = LITTLE_ENDIAN + } + } +}; + +static pc_fun_t pci_data = { + .hw_resources = { + sizeof(pci_conf_regs) / sizeof(pci_conf_regs[0]), + pci_conf_regs + }, + .pio_window = { + .mem = { + .base = UINT32_C(0), + .size = UINT32_C(0xffffffff) /* practical maximum */ + }, + .io = { + .base = UINT32_C(0), + .size = UINT32_C(0x10000) + } + } +}; + +/** Obtain function soft-state from DDF function node */ +static pc_fun_t *pc_fun(ddf_fun_t *fnode) +{ + return ddf_fun_data_get(fnode); +} + +static hw_resource_list_t *pc_get_resources(ddf_fun_t *fnode) +{ + pc_fun_t *fun = pc_fun(fnode); + + assert(fun != NULL); + return &fun->hw_resources; +} + +static bool pc_enable_interrupt(ddf_fun_t *fun) +{ + /* TODO */ + + return false; +} + +static pio_window_t *pc_get_pio_window(ddf_fun_t *fnode) +{ + pc_fun_t *fun = pc_fun(fnode); + + assert(fun != NULL); + return &fun->pio_window; +} + +static hw_res_ops_t fun_hw_res_ops = { + .get_resource_list = &pc_get_resources, + .enable_interrupt = &pc_enable_interrupt, +}; + +static pio_window_ops_t fun_pio_window_ops = { + .get_pio_window = &pc_get_pio_window +}; + +/* Initialized in pc_init() function. */ +static ddf_dev_ops_t pc_fun_ops; + +static bool +pc_add_fun(ddf_dev_t *dev, const char *name, const char *str_match_id, + pc_fun_t *fun_proto) +{ + ddf_msg(LVL_DEBUG, "Adding new function '%s'.", name); + + ddf_fun_t *fnode = NULL; + int rc; + + /* Create new device. */ + fnode = ddf_fun_create(dev, fun_inner, name); + if (fnode == NULL) + goto failure; + + pc_fun_t *fun = ddf_fun_data_alloc(fnode, sizeof(pc_fun_t)); + *fun = *fun_proto; + + /* Add match ID */ + rc = ddf_fun_add_match_id(fnode, str_match_id, 100); + if (rc != EOK) + goto failure; + + /* Set provided operations to the device. */ + ddf_fun_set_ops(fnode, &pc_fun_ops); + + /* Register function. */ + if (ddf_fun_bind(fnode) != EOK) { + ddf_msg(LVL_ERROR, "Failed binding function %s.", name); + goto failure; + } + + return true; + +failure: + if (fnode != NULL) + ddf_fun_destroy(fnode); + + ddf_msg(LVL_ERROR, "Failed adding function '%s'.", name); + + return false; +} + +static bool pc_add_functions(ddf_dev_t *dev) +{ + return pc_add_fun(dev, "pci0", "intel_pci", &pci_data); +} + +/** Get the root device. + * + * @param dev The device which is root of the whole device tree (both + * of HW and pseudo devices). + * @return Zero on success, negative error number otherwise. + */ +static int pc_dev_add(ddf_dev_t *dev) +{ + ddf_msg(LVL_DEBUG, "pc_dev_add, device handle = %d", + (int)ddf_dev_get_handle(dev)); + + /* Register functions. */ + if (!pc_add_functions(dev)) { + ddf_msg(LVL_ERROR, "Failed to add functions for PC platform."); + } + + return EOK; +} + +static void pc_init(void) +{ + ddf_log_init(NAME); + pc_fun_ops.interfaces[HW_RES_DEV_IFACE] = &fun_hw_res_ops; + pc_fun_ops.interfaces[PIO_WINDOW_DEV_IFACE] = &fun_pio_window_ops; +} + +int main(int argc, char *argv[]) +{ + printf(NAME ": HelenOS PC platform driver\n"); + pc_init(); + return ddf_driver_main(&pc_driver); +} + +/** + * @} + */ Index: uspace/drv/platform/pc/pc.ma =================================================================== --- uspace/drv/platform/pc/pc.ma (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) +++ uspace/drv/platform/pc/pc.ma (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -0,0 +1,1 @@ +10 platform/pc Index: uspace/drv/root/root/Makefile =================================================================== --- uspace/drv/root/root/Makefile (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) +++ uspace/drv/root/root/Makefile (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -0,0 +1,37 @@ +# +# Copyright (c) 2010 Lenka Trochtova +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# - Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# - Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# - The name of the author may not be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +USPACE_PREFIX = ../../.. +LIBS = $(LIBDRV_PREFIX)/libdrv.a +EXTRA_CFLAGS += -I$(LIBDRV_PREFIX)/include +BINARY = root + +SOURCES = \ + root.c + +include $(USPACE_PREFIX)/Makefile.common Index: uspace/drv/root/root/root.c =================================================================== --- uspace/drv/root/root/root.c (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) +++ uspace/drv/root/root/root.c (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -0,0 +1,248 @@ +/* + * Copyright (c) 2010 Lenka Trochtova + * Copyright (c) 2010 Vojtech Horky + * Copyright (c) 2011 Jiri Svoboda + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @defgroup root Root device driver. + * @brief HelenOS root device driver. + * @{ + */ + +/** @file + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define NAME "root" + +#define PLATFORM_FUN_NAME "hw" +#define PLATFORM_FUN_MATCH_ID_FMT "platform/%s" +#define PLATFORM_FUN_MATCH_SCORE 100 + +#define VIRTUAL_FUN_NAME "virt" +#define VIRTUAL_FUN_MATCH_ID "virt" +#define VIRTUAL_FUN_MATCH_SCORE 100 + +static int root_dev_add(ddf_dev_t *dev); +static int root_fun_online(ddf_fun_t *fun); +static int root_fun_offline(ddf_fun_t *fun); + +/** The root device driver's standard operations. */ +static driver_ops_t root_ops = { + .dev_add = &root_dev_add, + .fun_online = &root_fun_online, + .fun_offline = &root_fun_offline +}; + +/** The root device driver structure. */ +static driver_t root_driver = { + .name = NAME, + .driver_ops = &root_ops +}; + +/** Create the function which represents the root of virtual device tree. + * + * @param dev Device + * @return EOK on success or negative error code + */ +static int add_virtual_root_fun(ddf_dev_t *dev) +{ + const char *name = VIRTUAL_FUN_NAME; + ddf_fun_t *fun; + int rc; + + ddf_msg(LVL_DEBUG, "Adding new function for virtual devices. " + "Function node is `%s' (%d %s)", name, + VIRTUAL_FUN_MATCH_SCORE, VIRTUAL_FUN_MATCH_ID); + + fun = ddf_fun_create(dev, fun_inner, name); + if (fun == NULL) { + ddf_msg(LVL_ERROR, "Failed creating function %s", name); + return ENOMEM; + } + + rc = ddf_fun_add_match_id(fun, VIRTUAL_FUN_MATCH_ID, + VIRTUAL_FUN_MATCH_SCORE); + if (rc != EOK) { + ddf_msg(LVL_ERROR, "Failed adding match IDs to function %s", + name); + ddf_fun_destroy(fun); + return rc; + } + + rc = ddf_fun_bind(fun); + if (rc != EOK) { + ddf_msg(LVL_ERROR, "Failed binding function %s: %s", name, + str_error(rc)); + ddf_fun_destroy(fun); + return rc; + } + + return EOK; +} + +/** Create the function which represents the root of HW device tree. + * + * @param dev Device + * @return EOK on success or negative error code + */ +static int add_platform_fun(ddf_dev_t *dev) +{ + char *match_id; + char *platform; + size_t platform_size; + + const char *name = PLATFORM_FUN_NAME; + ddf_fun_t *fun; + int rc; + + /* Get platform name from sysinfo. */ + platform = sysinfo_get_data("platform", &platform_size); + if (platform == NULL) { + ddf_msg(LVL_ERROR, "Failed to obtain platform name."); + return ENOENT; + } + + /* Null-terminate string. */ + platform = realloc(platform, platform_size + 1); + if (platform == NULL) { + ddf_msg(LVL_ERROR, "Memory allocation failed."); + return ENOMEM; + } + + platform[platform_size] = '\0'; + + /* Construct match ID. */ + if (asprintf(&match_id, PLATFORM_FUN_MATCH_ID_FMT, platform) == -1) { + ddf_msg(LVL_ERROR, "Memory allocation failed."); + free(platform); + return ENOMEM; + } + + free(platform); + + /* Add function. */ + ddf_msg(LVL_DEBUG, "Adding platform function. Function node is `%s' " + " (%d %s)", PLATFORM_FUN_NAME, PLATFORM_FUN_MATCH_SCORE, + match_id); + + fun = ddf_fun_create(dev, fun_inner, name); + if (fun == NULL) { + ddf_msg(LVL_ERROR, "Error creating function %s", name); + free(match_id); + return ENOMEM; + } + + rc = ddf_fun_add_match_id(fun, match_id, PLATFORM_FUN_MATCH_SCORE); + if (rc != EOK) { + ddf_msg(LVL_ERROR, "Failed adding match IDs to function %s", + name); + free(match_id); + ddf_fun_destroy(fun); + return rc; + } + + free(match_id); + + rc = ddf_fun_bind(fun); + if (rc != EOK) { + ddf_msg(LVL_ERROR, "Failed binding function %s: %s", name, + str_error(rc)); + ddf_fun_destroy(fun); + return rc; + } + + return EOK; +} + +/** Get the root device. + * + * @param dev The device which is root of the whole device tree (both + * of HW and pseudo devices). + */ +static int root_dev_add(ddf_dev_t *dev) +{ + ddf_msg(LVL_DEBUG, "root_dev_add, device handle=%" PRIun, + ddf_dev_get_handle(dev)); + + /* + * Register virtual devices root. + * We warn on error occurrence because virtual devices shall not be + * vital for the system. + */ + int res = add_virtual_root_fun(dev); + if (res != EOK) + ddf_msg(LVL_WARN, "Failed to add virtual child."); + + /* Register root device's children. */ + res = add_platform_fun(dev); + if (EOK != res) + ddf_msg(LVL_ERROR, "Failed adding child device for platform."); + + return res; +} + +static int root_fun_online(ddf_fun_t *fun) +{ + ddf_msg(LVL_DEBUG, "root_fun_online()"); + return ddf_fun_online(fun); +} + +static int root_fun_offline(ddf_fun_t *fun) +{ + ddf_msg(LVL_DEBUG, "root_fun_offline()"); + return ddf_fun_offline(fun); +} + +int main(int argc, char *argv[]) +{ + printf(NAME ": HelenOS root device driver\n"); + + ddf_log_init(NAME); + return ddf_driver_main(&root_driver); +} + +/** + * @} + */ + Index: uspace/drv/root/root/root.ma =================================================================== --- uspace/drv/root/root/root.ma (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) +++ uspace/drv/root/root/root.ma (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -0,0 +1,1 @@ +10 root Index: uspace/drv/root/virt/Makefile =================================================================== --- uspace/drv/root/virt/Makefile (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) +++ uspace/drv/root/virt/Makefile (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -0,0 +1,37 @@ +# +# Copyright (c) 2010 Vojtech Horky +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# - Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# - Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# - The name of the author may not be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +USPACE_PREFIX = ../../.. +LIBS = $(LIBDRV_PREFIX)/libdrv.a +EXTRA_CFLAGS += -I$(LIBDRV_PREFIX)/include +BINARY = virt + +SOURCES = \ + virt.c + +include $(USPACE_PREFIX)/Makefile.common Index: uspace/drv/root/virt/devices.def =================================================================== --- uspace/drv/root/virt/devices.def (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) +++ uspace/drv/root/virt/devices.def (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -0,0 +1,46 @@ +/* + * Add list of virtual devices you want to launch driver for here. + * + * Unless the list is empty, the last item shall be followed by a comma. + */ + +/* Kernel framebuffer */ +{ + .name = "kfb", + .match_id = "virtual&kfb" +}, + +#ifdef CONFIG_TEST_DRIVERS + +{ + .name = "test1", + .match_id = "virtual&test1" +}, +{ + .name = "test2alpha", + .match_id = "virtual&test2" +}, +{ + .name = "test2bravo", + .match_id = "virtual&test2" +}, +{ + .name = "null", + .match_id = "virtual&test1" +}, +{ + .name = "test3", + .match_id = "virtual&test3" +}, + +#endif + +#ifdef CONFIG_RUN_VIRTUAL_USB_HC + +/* Virtual USB host controller. */ +{ + .name = "usbhc", + .match_id = "usb&hc=vhc" +}, + +#endif Index: uspace/drv/root/virt/virt.c =================================================================== --- uspace/drv/root/virt/virt.c (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) +++ uspace/drv/root/virt/virt.c (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -0,0 +1,249 @@ +/* + * Copyright (c) 2010 Vojtech Horky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @defgroup virt Root device driver for virtual devices. + * @{ + */ + +/** @file + */ + +#include +#include +#include +#include +#include +#include + +#define NAME "virt" + +/** Virtual function entry */ +typedef struct { + /** Function name */ + const char *name; + /** Function match ID */ + const char *match_id; +} virtual_function_t; + +/** List of existing virtual functions */ +virtual_function_t virtual_functions[] = { +#include "devices.def" + /* Terminating item */ + { + .name = NULL, + .match_id = NULL + } +}; + +static int virt_dev_add(ddf_dev_t *dev); +static int virt_dev_remove(ddf_dev_t *dev); +static int virt_fun_online(ddf_fun_t *fun); +static int virt_fun_offline(ddf_fun_t *fun); + +static driver_ops_t virt_ops = { + .dev_add = &virt_dev_add, + .dev_remove = &virt_dev_remove, + .fun_online = &virt_fun_online, + .fun_offline = &virt_fun_offline +}; + +static driver_t virt_driver = { + .name = NAME, + .driver_ops = &virt_ops +}; + +/* Device soft state */ +typedef struct { + ddf_dev_t *dev; + list_t functions; +} virt_t; + +/* Function soft state */ +typedef struct { + ddf_fun_t *fun; + link_t dev_link; +} virt_fun_t; + +static int instances = 0; + + +/** Add function to the virtual device. + * + * @param vdev The virtual device + * @param vfun Virtual function description + * @return EOK on success or negative error code. + */ +static int virt_add_fun(virt_t *virt, virtual_function_t *vfun) +{ + ddf_dev_t *vdev = virt->dev; + ddf_fun_t *fun; + virt_fun_t *rvfun; + int rc; + + ddf_msg(LVL_DEBUG, "Registering function `%s' (match \"%s\")", + vfun->name, vfun->match_id); + + fun = ddf_fun_create(vdev, fun_inner, vfun->name); + if (fun == NULL) { + ddf_msg(LVL_ERROR, "Failed creating function %s", vfun->name); + return ENOMEM; + } + + rvfun = ddf_fun_data_alloc(fun, sizeof(virt_fun_t)); + if (rvfun == NULL) { + ddf_msg(LVL_ERROR, "Failed allocating soft state for %s.", + vfun->name); + ddf_fun_destroy(fun); + return ENOMEM; + } + + rvfun->fun = fun; + + rc = ddf_fun_add_match_id(fun, vfun->match_id, 10); + if (rc != EOK) { + ddf_msg(LVL_ERROR, "Failed adding match IDs to function %s", + vfun->name); + ddf_fun_destroy(fun); + return rc; + } + + rc = ddf_fun_bind(fun); + if (rc != EOK) { + ddf_msg(LVL_ERROR, "Failed binding function %s: %s", + vfun->name, str_error(rc)); + ddf_fun_destroy(fun); + return rc; + } + + list_append(&rvfun->dev_link, &virt->functions); + + ddf_msg(LVL_NOTE, "Registered child device `%s'", vfun->name); + return EOK; +} + +static int virt_fun_remove(virt_fun_t *rvfun) +{ + int rc; + const char *name = ddf_fun_get_name(rvfun->fun); + + ddf_msg(LVL_DEBUG, "virt_fun_remove('%s')", name); + rc = ddf_fun_offline(rvfun->fun); + if (rc != EOK) { + ddf_msg(LVL_ERROR, "Error offlining function '%s'.", name); + return rc; + } + + rc = ddf_fun_unbind(rvfun->fun); + if (rc != EOK) { + ddf_msg(LVL_ERROR, "Failed unbinding function '%s'.", name); + return rc; + } + + list_remove(&rvfun->dev_link); + ddf_fun_destroy(rvfun->fun); + return EOK; +} + + +static int virt_dev_add(ddf_dev_t *dev) +{ + virt_t *virt; + + /* + * Allow only single instance of root virtual device. + */ + if (++instances > 1) { + return ELIMIT; + } + + ddf_msg(LVL_DEBUG, "dev_add(handle=%d)", (int)ddf_dev_get_handle(dev)); + + virt = ddf_dev_data_alloc(dev, sizeof(virt_t)); + if (virt == NULL) + return ENOMEM; + + virt->dev = dev; + list_initialize(&virt->functions); + + /* + * Go through all virtual functions and try to add them. + * We silently ignore failures. + */ + virtual_function_t *vfun = virtual_functions; + while (vfun->name != NULL) { + (void) virt_add_fun(virt, vfun); + vfun++; + } + + return EOK; +} + +static int virt_dev_remove(ddf_dev_t *dev) +{ + virt_t *virt = (virt_t *)ddf_dev_data_get(dev); + int rc; + + while (!list_empty(&virt->functions)) { + virt_fun_t *rvfun = list_get_instance( + list_first(&virt->functions), virt_fun_t, + dev_link); + + rc = virt_fun_remove(rvfun); + if (rc != EOK) + return rc; + } + + --instances; + return EOK; +} + +static int virt_fun_online(ddf_fun_t *fun) +{ + ddf_msg(LVL_DEBUG, "virt_fun_online()"); + return ddf_fun_online(fun); +} + +static int virt_fun_offline(ddf_fun_t *fun) +{ + ddf_msg(LVL_DEBUG, "virt_fun_offline()"); + return ddf_fun_offline(fun); +} + +int main(int argc, char *argv[]) +{ + printf(NAME ": HelenOS virtual devices root driver\n"); + + ddf_log_init(NAME); + return ddf_driver_main(&virt_driver); +} + +/** + * @} + */ + Index: uspace/drv/root/virt/virt.ma =================================================================== --- uspace/drv/root/virt/virt.ma (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) +++ uspace/drv/root/virt/virt.ma (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) @@ -0,0 +1,1 @@ +10 virt