Index: uspace/lib/libc/arch/mips32/Makefile.inc
===================================================================
--- uspace/lib/libc/arch/mips32/Makefile.inc	(revision 00acd66d3981789b3f8b04cdd854d29343dd9aa0)
+++ uspace/lib/libc/arch/mips32/Makefile.inc	(revision f2f03920b9cbe70ec1fa65df9ff172eba44647a4)
@@ -40,5 +40,5 @@
 
 ARCH_SOURCES += arch/$(ARCH)/src/syscall.c \
-	arch/$(ARCH)/src/psthread.S \
+	arch/$(ARCH)/src/fibril.S \
 	arch/$(ARCH)/src/thread.c
 
Index: uspace/lib/libc/arch/mips32/include/fibril.h
===================================================================
--- uspace/lib/libc/arch/mips32/include/fibril.h	(revision f2f03920b9cbe70ec1fa65df9ff172eba44647a4)
+++ uspace/lib/libc/arch/mips32/include/fibril.h	(revision f2f03920b9cbe70ec1fa65df9ff172eba44647a4)
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2006 Ondrej Palkovsky
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/** @addtogroup libcmips32	
+ * @{
+ */
+/** @file
+ * @ingroup libcmips32eb	
+ */
+
+#ifndef LIBC_mips32_FIBRIL_H_
+#define LIBC_mips32_FIBRIL_H_
+
+#include <types.h>
+
+/* We define our own context_set, because we need to set
+ * the TLS pointer to the tcb+0x7000
+ *
+ * See tls_set in thread.h
+ */
+#define context_set(c, _pc, stack, size, ptls) 			\
+	(c)->pc = (sysarg_t) (_pc);				\
+	(c)->sp = ((sysarg_t) (stack)) + (size) - SP_DELTA; 	\
+        (c)->tls = ((sysarg_t)(ptls)) + 0x7000 + sizeof(tcb_t);
+
+
+/* +16 is just for sure that the called function
+ * have space to store it's arguments
+ */
+#define SP_DELTA	(8+16)
+
+typedef struct  {
+	uint32_t sp;
+	uint32_t pc;
+	
+	uint32_t s0;
+	uint32_t s1;
+	uint32_t s2;
+	uint32_t s3;
+	uint32_t s4;
+	uint32_t s5;
+	uint32_t s6;
+	uint32_t s7;
+	uint32_t s8;
+	uint32_t gp;
+	uint32_t tls; /* Thread local storage(=k1) */
+
+	uint32_t f20;
+	uint32_t f21;
+	uint32_t f22;
+	uint32_t f23;
+	uint32_t f24;
+	uint32_t f25;
+	uint32_t f26;
+	uint32_t f27;
+	uint32_t f28;
+	uint32_t f29;
+	uint32_t f30;
+	
+} context_t;
+
+#endif
+
+/** @}
+ */
Index: uspace/lib/libc/arch/mips32/include/psthread.h
===================================================================
--- uspace/lib/libc/arch/mips32/include/psthread.h	(revision 00acd66d3981789b3f8b04cdd854d29343dd9aa0)
+++ 	(revision )
@@ -1,90 +1,0 @@
-/*
- * Copyright (c) 2006 Ondrej Palkovsky
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * - Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in the
- *   documentation and/or other materials provided with the distribution.
- * - The name of the author may not be used to endorse or promote products
- *   derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/** @addtogroup libcmips32	
- * @{
- */
-/** @file
- * @ingroup libcmips32eb	
- */
-
-#ifndef LIBC_mips32_PSTHREAD_H_
-#define LIBC_mips32_PSTHREAD_H_
-
-#include <types.h>
-
-/* We define our own context_set, because we need to set
- * the TLS pointer to the tcb+0x7000
- *
- * See tls_set in thread.h
- */
-#define context_set(c, _pc, stack, size, ptls) 			\
-	(c)->pc = (sysarg_t) (_pc);				\
-	(c)->sp = ((sysarg_t) (stack)) + (size) - SP_DELTA; 	\
-        (c)->tls = ((sysarg_t)(ptls)) + 0x7000 + sizeof(tcb_t);
-
-
-/* +16 is just for sure that the called function
- * have space to store it's arguments
- */
-#define SP_DELTA	(8+16)
-
-typedef struct  {
-	uint32_t sp;
-	uint32_t pc;
-	
-	uint32_t s0;
-	uint32_t s1;
-	uint32_t s2;
-	uint32_t s3;
-	uint32_t s4;
-	uint32_t s5;
-	uint32_t s6;
-	uint32_t s7;
-	uint32_t s8;
-	uint32_t gp;
-	uint32_t tls; /* Thread local storage(=k1) */
-
-	uint32_t f20;
-	uint32_t f21;
-	uint32_t f22;
-	uint32_t f23;
-	uint32_t f24;
-	uint32_t f25;
-	uint32_t f26;
-	uint32_t f27;
-	uint32_t f28;
-	uint32_t f29;
-	uint32_t f30;
-	
-} context_t;
-
-#endif
-
-/** @}
- */
Index: uspace/lib/libc/arch/mips32/include/thread.h
===================================================================
--- uspace/lib/libc/arch/mips32/include/thread.h	(revision 00acd66d3981789b3f8b04cdd854d29343dd9aa0)
+++ uspace/lib/libc/arch/mips32/include/thread.h	(revision f2f03920b9cbe70ec1fa65df9ff172eba44647a4)
@@ -36,6 +36,6 @@
 /* TLS for MIPS is described in http://www.linux-mips.org/wiki/NPTL */
 
-#ifndef LIBC_mips32THREAD_H_
-#define LIBC_mips32THREAD_H_
+#ifndef LIBC_mips32_THREAD_H_
+#define LIBC_mips32_THREAD_H_
 
 /* I did not find any specification (neither MIPS nor PowerPC), but
@@ -54,5 +54,5 @@
 
 typedef struct {
-	void *pst_data;
+	void *fibril_data;
 } tcb_t;
 
Index: uspace/lib/libc/arch/mips32/src/fibril.S
===================================================================
--- uspace/lib/libc/arch/mips32/src/fibril.S	(revision f2f03920b9cbe70ec1fa65df9ff172eba44647a4)
+++ uspace/lib/libc/arch/mips32/src/fibril.S	(revision f2f03920b9cbe70ec1fa65df9ff172eba44647a4)
@@ -0,0 +1,161 @@
+#
+# Copyright (c) 2003-2004 Jakub Jermar
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# - Redistributions of source code must retain the above copyright
+#   notice, this list of conditions and the following disclaimer.
+# - Redistributions in binary form must reproduce the above copyright
+#   notice, this list of conditions and the following disclaimer in the
+#   documentation and/or other materials provided with the distribution.
+# - The name of the author may not be used to endorse or promote products
+#   derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+.text
+
+.set noat
+.set noreorder
+
+
+#include <arch/asm/regname.h>
+#include <libarch/context_offset.h>
+	
+.global context_save
+.global context_restore
+	
+.macro CONTEXT_STORE r
+	sw $s0,OFFSET_S0(\r)
+	sw $s1,OFFSET_S1(\r)
+	sw $s2,OFFSET_S2(\r)
+	sw $s3,OFFSET_S3(\r)
+	sw $s4,OFFSET_S4(\r)
+	sw $s5,OFFSET_S5(\r)
+	sw $s6,OFFSET_S6(\r)
+	sw $s7,OFFSET_S7(\r)
+	sw $s8,OFFSET_S8(\r)
+	sw $gp,OFFSET_GP(\r)
+	sw $k1,OFFSET_TLS(\r)
+
+#ifdef CONFIG_MIPS_FPU	
+	mfc1 $t0,$20
+	sw $t0, OFFSET_F20(\r)
+
+	mfc1 $t0,$21
+	sw $t0, OFFSET_F21(\r)
+
+	mfc1 $t0,$22
+	sw $t0, OFFSET_F22(\r)
+
+	mfc1 $t0,$23
+	sw $t0, OFFSET_F23(\r)
+
+	mfc1 $t0,$24
+	sw $t0, OFFSET_F24(\r)
+
+	mfc1 $t0,$25
+	sw $t0, OFFSET_F25(\r)
+
+	mfc1 $t0,$26
+	sw $t0, OFFSET_F26(\r)
+
+	mfc1 $t0,$27
+	sw $t0, OFFSET_F27(\r)
+
+	mfc1 $t0,$28
+	sw $t0, OFFSET_F28(\r)
+
+	mfc1 $t0,$29
+	sw $t0, OFFSET_F29(\r)
+	
+	mfc1 $t0,$30
+	sw $t0, OFFSET_F30(\r)
+#endif	
+		
+	sw $ra,OFFSET_PC(\r)
+	sw $sp,OFFSET_SP(\r)
+.endm
+
+.macro CONTEXT_LOAD r
+	lw $s0,OFFSET_S0(\r)
+	lw $s1,OFFSET_S1(\r)
+	lw $s2,OFFSET_S2(\r)
+	lw $s3,OFFSET_S3(\r)
+	lw $s4,OFFSET_S4(\r)
+	lw $s5,OFFSET_S5(\r)
+	lw $s6,OFFSET_S6(\r)
+	lw $s7,OFFSET_S7(\r)
+	lw $s8,OFFSET_S8(\r)
+	lw $gp,OFFSET_GP(\r)
+	lw $k1,OFFSET_TLS(\r)
+
+#ifdef CONFIG_MIPS_FPU	
+	lw $t0, OFFSET_F20(\r)
+	mtc1 $t0,$20
+
+	lw $t0, OFFSET_F21(\r)
+	mtc1 $t0,$21
+
+	lw $t0, OFFSET_F22(\r)
+	mtc1 $t0,$22
+
+	lw $t0, OFFSET_F23(\r)
+	mtc1 $t0,$23
+
+	lw $t0, OFFSET_F24(\r)
+	mtc1 $t0,$24
+
+	lw $t0, OFFSET_F25(\r)
+	mtc1 $t0,$25
+
+	lw $t0, OFFSET_F26(\r)
+	mtc1 $t0,$26
+
+	lw $t0, OFFSET_F27(\r)
+	mtc1 $t0,$27
+
+	lw $t0, OFFSET_F28(\r)
+	mtc1 $t0,$28
+
+	lw $t0, OFFSET_F29(\r)
+	mtc1 $t0,$29
+
+	lw $t0, OFFSET_F30(\r)
+	mtc1 $t0,$30
+#endif	
+		
+	lw $ra,OFFSET_PC(\r)
+	lw $sp,OFFSET_SP(\r)
+.endm
+	
+context_save:
+	CONTEXT_STORE $a0
+
+	# context_save returns 1
+	j $ra
+	li $v0, 1	
+	
+context_restore:
+	CONTEXT_LOAD $a0
+
+	# Just for the jump into first function, but one instruction
+	# should not bother us
+	move $t9, $ra	
+	# context_restore returns 0
+	j $ra
+	xor $v0, $v0	
+
Index: uspace/lib/libc/arch/mips32/src/psthread.S
===================================================================
--- uspace/lib/libc/arch/mips32/src/psthread.S	(revision 00acd66d3981789b3f8b04cdd854d29343dd9aa0)
+++ 	(revision )
@@ -1,161 +1,0 @@
-#
-# Copyright (c) 2003-2004 Jakub Jermar
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions
-# are met:
-#
-# - Redistributions of source code must retain the above copyright
-#   notice, this list of conditions and the following disclaimer.
-# - Redistributions in binary form must reproduce the above copyright
-#   notice, this list of conditions and the following disclaimer in the
-#   documentation and/or other materials provided with the distribution.
-# - The name of the author may not be used to endorse or promote products
-#   derived from this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
-# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
-# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-
-.text
-
-.set noat
-.set noreorder
-
-
-#include <arch/asm/regname.h>
-#include <libarch/context_offset.h>
-	
-.global context_save
-.global context_restore
-	
-.macro CONTEXT_STORE r
-	sw $s0,OFFSET_S0(\r)
-	sw $s1,OFFSET_S1(\r)
-	sw $s2,OFFSET_S2(\r)
-	sw $s3,OFFSET_S3(\r)
-	sw $s4,OFFSET_S4(\r)
-	sw $s5,OFFSET_S5(\r)
-	sw $s6,OFFSET_S6(\r)
-	sw $s7,OFFSET_S7(\r)
-	sw $s8,OFFSET_S8(\r)
-	sw $gp,OFFSET_GP(\r)
-	sw $k1,OFFSET_TLS(\r)
-
-#ifdef CONFIG_MIPS_FPU	
-	mfc1 $t0,$20
-	sw $t0, OFFSET_F20(\r)
-
-	mfc1 $t0,$21
-	sw $t0, OFFSET_F21(\r)
-
-	mfc1 $t0,$22
-	sw $t0, OFFSET_F22(\r)
-
-	mfc1 $t0,$23
-	sw $t0, OFFSET_F23(\r)
-
-	mfc1 $t0,$24
-	sw $t0, OFFSET_F24(\r)
-
-	mfc1 $t0,$25
-	sw $t0, OFFSET_F25(\r)
-
-	mfc1 $t0,$26
-	sw $t0, OFFSET_F26(\r)
-
-	mfc1 $t0,$27
-	sw $t0, OFFSET_F27(\r)
-
-	mfc1 $t0,$28
-	sw $t0, OFFSET_F28(\r)
-
-	mfc1 $t0,$29
-	sw $t0, OFFSET_F29(\r)
-	
-	mfc1 $t0,$30
-	sw $t0, OFFSET_F30(\r)
-#endif	
-		
-	sw $ra,OFFSET_PC(\r)
-	sw $sp,OFFSET_SP(\r)
-.endm
-
-.macro CONTEXT_LOAD r
-	lw $s0,OFFSET_S0(\r)
-	lw $s1,OFFSET_S1(\r)
-	lw $s2,OFFSET_S2(\r)
-	lw $s3,OFFSET_S3(\r)
-	lw $s4,OFFSET_S4(\r)
-	lw $s5,OFFSET_S5(\r)
-	lw $s6,OFFSET_S6(\r)
-	lw $s7,OFFSET_S7(\r)
-	lw $s8,OFFSET_S8(\r)
-	lw $gp,OFFSET_GP(\r)
-	lw $k1,OFFSET_TLS(\r)
-
-#ifdef CONFIG_MIPS_FPU	
-	lw $t0, OFFSET_F20(\r)
-	mtc1 $t0,$20
-
-	lw $t0, OFFSET_F21(\r)
-	mtc1 $t0,$21
-
-	lw $t0, OFFSET_F22(\r)
-	mtc1 $t0,$22
-
-	lw $t0, OFFSET_F23(\r)
-	mtc1 $t0,$23
-
-	lw $t0, OFFSET_F24(\r)
-	mtc1 $t0,$24
-
-	lw $t0, OFFSET_F25(\r)
-	mtc1 $t0,$25
-
-	lw $t0, OFFSET_F26(\r)
-	mtc1 $t0,$26
-
-	lw $t0, OFFSET_F27(\r)
-	mtc1 $t0,$27
-
-	lw $t0, OFFSET_F28(\r)
-	mtc1 $t0,$28
-
-	lw $t0, OFFSET_F29(\r)
-	mtc1 $t0,$29
-
-	lw $t0, OFFSET_F30(\r)
-	mtc1 $t0,$30
-#endif	
-		
-	lw $ra,OFFSET_PC(\r)
-	lw $sp,OFFSET_SP(\r)
-.endm
-	
-context_save:
-	CONTEXT_STORE $a0
-
-	# context_save returns 1
-	j $ra
-	li $v0, 1	
-	
-context_restore:
-	CONTEXT_LOAD $a0
-
-	# Just for the jump into first function, but one instruction
-	# should not bother us
-	move $t9, $ra	
-	# context_restore returns 0
-	j $ra
-	xor $v0, $v0	
-
