Index: uspace/drv/bus/isa/i8237.c
===================================================================
--- uspace/drv/bus/isa/i8237.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ uspace/drv/bus/isa/i8237.c	(revision f1380b76772fb5d1aa03637b5e57bd9b929fea61)
@@ -99,7 +99,7 @@
 	uint8_t channel_start3;
 	uint8_t channel_count3;
-	
+
 	uint8_t command_status;
-	
+
 	/** Memory to memory transfers, NOT implemented on PCs */
 	uint8_t request;
@@ -107,5 +107,5 @@
 	uint8_t mode;
 	uint8_t flip_flop;
-	
+
 	/*
 	 * Master reset sets Flip-Flop low, clears status,
@@ -136,5 +136,5 @@
 	uint8_t reserved6;
 	uint8_t channel_count7;
-	
+
 	uint8_t command_status;
 	uint8_t reserved8;
@@ -230,5 +230,5 @@
 			.flip_flop_address = (uint8_t *) 0x0c,
 		},
-		
+
 		/* The second chip 16-bit */
 		{ /* Channel 4 - Unusable */
@@ -265,5 +265,5 @@
 		},
 	},
-	
+
 	.page_table = NULL,
 	.first = NULL,
@@ -286,21 +286,21 @@
 	if (ret != EOK)
 		return EIO;
-	
+
 	ret = pio_enable(DMA_CONTROLLER_FIRST_BASE,
 	    sizeof(dma_controller_regs_first_t), (void **) &controller->first);
 	if (ret != EOK)
 		return EIO;
-	
+
 	ret = pio_enable(DMA_CONTROLLER_SECOND_BASE,
 		sizeof(dma_controller_regs_second_t), (void **) &controller->second);
 	if (ret != EOK)
 		return EIO;
-	
+
 	controller->initialized = true;
-	
+
 	/* Reset the controller */
 	pio_write_8(&controller->second->master_reset, 0xff);
 	pio_write_8(&controller->first->master_reset, 0xff);
-	
+
 	return EOK;
 }
@@ -347,9 +347,9 @@
 	if ((channel == 0) || (channel == 4))
 		return ENOTSUP;
-	
+
 	/* DMA is limited to 24bit addresses. */
 	if (pa >= (1 << 24))
 		return EINVAL;
-	
+
 	/* 8 bit channels use only 4 bits from the page register. */
 	if (is_dma8(channel) && (pa >= (1 << 20)))
@@ -359,15 +359,15 @@
 	if ((pa & 0xffff0000) != ((pa + size - 1) & 0xffff0000))
 		return EINVAL;
-	
+
 	fibril_mutex_lock(&guard);
-	
+
 	if (!controller_8237.initialized)
 		dma_controller_init(&controller_8237);
-	
+
 	if (!controller_8237.initialized) {
 		fibril_mutex_unlock(&guard);
 		return EIO;
 	}
-	
+
 	/* 16 bit transfers are a bit special */
 	ddf_msg(LVL_DEBUG, "Unspoiled address %#" PRIx32 " (size %" PRIu32 ")",
@@ -384,15 +384,15 @@
 		pa = ((pa & 0xffff) >> 1) | (pa & 0xff0000);
 	}
-	
+
 	const dma_channel_t dma_channel = controller_8237.channels[channel];
-	
+
 	ddf_msg(LVL_DEBUG, "Setting channel %u to address %#" PRIx32 " "
 	    "(size %" PRIu32 "), mode %hhx.", channel, pa, size, mode);
-	
+
 	/* Mask DMA request */
 	uint8_t value = DMA_SINGLE_MASK_CHAN_TO_REG(channel) |
 	    DMA_SINGLE_MASK_MASKED_FLAG;
 	pio_write_8(dma_channel.single_mask_address, value);
-	
+
 	/* Set mode */
 	value = DMA_MODE_CHAN_TO_REG(channel) | mode;
@@ -400,8 +400,8 @@
 	    dma_channel.mode_address, value);
 	pio_write_8(dma_channel.mode_address, value);
-	
+
 	/* Set address - reset flip-flop */
 	pio_write_8(dma_channel.flip_flop_address, 0);
-	
+
 	/* Low byte */
 	value = pa & 0xff;
@@ -409,5 +409,5 @@
 	    dma_channel.offset_reg_address, value);
 	pio_write_8(dma_channel.offset_reg_address, value);
-	
+
 	/* High byte */
 	value = (pa >> 8) & 0xff;
@@ -415,5 +415,5 @@
 	    dma_channel.offset_reg_address, value);
 	pio_write_8(dma_channel.offset_reg_address, value);
-	
+
 	/* Page address - third byte */
 	value = (pa >> 16) & 0xff;
@@ -421,8 +421,8 @@
 	    dma_channel.page_reg_address, value);
 	pio_write_8(dma_channel.page_reg_address, value);
-	
+
 	/* Set size - reset flip-flop */
 	pio_write_8(dma_channel.flip_flop_address, 0);
-	
+
 	/* Low byte */
 	value = (size - 1) & 0xff;
@@ -430,5 +430,5 @@
 	    dma_channel.size_reg_address, value);
 	pio_write_8(dma_channel.size_reg_address, value);
-	
+
 	/* High byte */
 	value = ((size - 1) >> 8) & 0xff;
@@ -436,11 +436,11 @@
 	    dma_channel.size_reg_address, value);
 	pio_write_8(dma_channel.size_reg_address, value);
-	
+
 	/* Unmask DMA request */
 	value = DMA_SINGLE_MASK_CHAN_TO_REG(channel);
 	pio_write_8(dma_channel.single_mask_address, value);
-	
+
 	fibril_mutex_unlock(&guard);
-	
+
 	return EOK;
 }
@@ -459,8 +459,8 @@
 	if (!is_dma8(channel) && !is_dma16(channel))
 		return ENOENT;
-	
+
 	if ((channel == 0) || (channel == 4))
 		return ENOTSUP;
-	
+
 	fibril_mutex_lock(&guard);
 	if (!controller_8237.initialized) {
@@ -472,10 +472,10 @@
 	/* Get size - reset flip-flop */
 	pio_write_8(dma_channel.flip_flop_address, 0);
-	
+
 	/* Low byte */
 	const uint8_t value_low = pio_read_8(dma_channel.size_reg_address);
 	ddf_msg(LVL_DEBUG2, "Read size low byte: %p:%x.",
 	    dma_channel.size_reg_address, value_low);
-	
+
 	/* High byte */
 	const uint8_t value_high = pio_read_8(dma_channel.size_reg_address);
Index: uspace/drv/bus/isa/isa.c
===================================================================
--- uspace/drv/bus/isa/isa.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ uspace/drv/bus/isa/isa.c	(revision f1380b76772fb5d1aa03637b5e57bd9b929fea61)
@@ -402,14 +402,14 @@
 	size_t count = fun->hw_resources.count;
 	hw_resource_t *resources = fun->hw_resources.resources;
-	
+
 	if (count < ISA_MAX_HW_RES) {
 		if ((dma > 0) && (dma < 4)) {
 			resources[count].type = DMA_CHANNEL_8;
 			resources[count].res.dma_channel.dma8 = dma;
-			
+
 			fun->hw_resources.count++;
 			ddf_msg(LVL_NOTE, "Added dma 0x%x to function %s", dma,
 			    ddf_fun_get_name(fun->fnode));
-			
+
 			return;
 		}
@@ -418,12 +418,12 @@
 			resources[count].type = DMA_CHANNEL_16;
 			resources[count].res.dma_channel.dma16 = dma;
-			
+
 			fun->hw_resources.count++;
 			ddf_msg(LVL_NOTE, "Added dma 0x%x to function %s", dma,
 			    ddf_fun_get_name(fun->fnode));
-			
+
 			return;
 		}
-		
+
 		ddf_msg(LVL_WARN, "Skipped dma 0x%x for function %s", dma,
 		    ddf_fun_get_name(fun->fnode));
@@ -492,8 +492,8 @@
 {
 	char *end = NULL;
-	
+
 	val = skip_spaces(val);
 	const int dma = strtol(val, &end, 10);
-	
+
 	if (val != end)
 		isa_fun_add_dma(fun, dma);
@@ -733,5 +733,5 @@
 	if (rc != EOK)
 		return rc;
-	
+
 	rc = pio_window_get(sess, &isa->pio_win);
 	if (rc != EOK) {