Index: HelenOS.config =================================================================== --- HelenOS.config (revision 716357ff5db66f096f15e81dc5b3aa611c7a9ff0) +++ HelenOS.config (revision eef14771b77663fec606dbe440c7f1f7cb1f78be) @@ -487,12 +487,9 @@ ! [PLATFORM=arm32&MACHINE=gta02] CONFIG_S3C24XX_IRQC (y) -% Support for TI AM335x on-chip UART -! [(CONFIG_HID_OUT=generic|CONFIG_HID_OUT=serial)&PLATFORM=arm32&MACHINE=beaglebone] CONFIG_AM335X_UART (y/n) - % Support for TI AM335x timers support ! [PLATFORM=arm32&MACHINE=beaglebone] CONFIG_AM335X_TIMERS (y) -% Support for TI AMDM37x on-chip UART -! [(CONFIG_HID_OUT=generic|CONFIG_HID_OUT=serial)&PLATFORM=arm32&MACHINE=beagleboardxm] CONFIG_AMDM37X_UART (y/n) +% Support for OMAP on-chip UART +! [(CONFIG_HID_OUT=generic|CONFIG_HID_OUT=serial)&PLATFORM=arm32&(MACHINE=beagleboardxm|MACHINE=beaglebone)] CONFIG_OMAP_UART (y/n) % Support for i8042 controller @@ -515,5 +512,5 @@ % Serial line input module -! [CONFIG_DSRLNIN=y|(PLATFORM=arm32&MACHINE=gta02)|(PLATFORM=arm32&MACHINE=integratorcp&CONFIG_ARM926_UART=y)|(PLATFORM=arm32&MACHINE=beaglebone&CONFIG_AM335X_UART=y)|(PLATFORM=arm32&MACHINE=beagleboardxm&CONFIG_AMDM37X_UART=y)|(PLATFORM=ia64&MACHINE=i460GX&CONFIG_NS16550=y)|(PLATFORM=ia64&MACHINE=ski)|(PLATFORM=sparc64&PROCESSOR=sun4v)] CONFIG_SRLN (y) +! [CONFIG_DSRLNIN=y|(PLATFORM=arm32&MACHINE=gta02)|(PLATFORM=arm32&MACHINE=integratorcp&CONFIG_ARM926_UART=y)|(PLATFORM=arm32&MACHINE=beaglebone&CONFIG_OMAP_UART=y)|(PLATFORM=arm32&MACHINE=beagleboardxm&CONFIG_OMAP_UART=y)|(PLATFORM=ia64&MACHINE=i460GX&CONFIG_NS16550=y)|(PLATFORM=ia64&MACHINE=ski)|(PLATFORM=sparc64&PROCESSOR=sun4v)] CONFIG_SRLN (y) % EGA support Index: kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c =================================================================== --- kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c (revision 716357ff5db66f096f15e81dc5b3aa611c7a9ff0) +++ kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c (revision eef14771b77663fec606dbe440c7f1f7cb1f78be) @@ -61,5 +61,5 @@ static struct beagleboard { amdm37x_irc_regs_t *irc_addr; - amdm37x_uart_t uart; + omap_uart_t uart; amdm37x_gpt_t timer; } beagleboard; @@ -167,21 +167,25 @@ static void bbxm_output_init(void) { +#ifdef CONFIG_OMAP_UART /* UART3 is wired to external RS232 connector */ - const bool ok = amdm37x_uart_init(&beagleboard.uart, + const bool ok = omap_uart_init(&beagleboard.uart, AMDM37x_UART3_IRQ, AMDM37x_UART3_BASE_ADDRESS, AMDM37x_UART3_SIZE); if (ok) { stdout_wire(&beagleboard.uart.outdev); } +#endif } static void bbxm_input_init(void) { +#ifdef CONFIG_OMAP_UART srln_instance_t *srln_instance = srln_init(); if (srln_instance) { indev_t *sink = stdin_wire(); indev_t *srln = srln_wire(srln_instance, sink); - amdm37x_uart_input_wire(&beagleboard.uart, srln); + omap_uart_input_wire(&beagleboard.uart, srln); amdm37x_irc_enable(beagleboard.irc_addr, AMDM37x_UART3_IRQ); } +#endif } Index: kernel/arch/arm32/src/mach/beaglebone/beaglebone.c =================================================================== --- kernel/arch/arm32/src/mach/beaglebone/beaglebone.c (revision 716357ff5db66f096f15e81dc5b3aa611c7a9ff0) +++ kernel/arch/arm32/src/mach/beaglebone/beaglebone.c (revision eef14771b77663fec606dbe440c7f1f7cb1f78be) @@ -68,5 +68,5 @@ am335x_ctrl_module_t *ctrl_module; am335x_timer_t timer; - am335x_uart_t uart; + omap_uart_t uart; } bbone; @@ -195,5 +195,6 @@ static void bbone_output_init(void) { - const bool ok = am335x_uart_init(&bbone.uart, +#ifdef CONFIG_OMAP_UART + const bool ok = omap_uart_init(&bbone.uart, AM335x_UART0_IRQ, AM335x_UART0_BASE_ADDRESS, AM335x_UART0_SIZE); @@ -201,15 +202,18 @@ if (ok) stdout_wire(&bbone.uart.outdev); +#endif } static void bbone_input_init(void) { +#ifdef CONFIG_OMAP_UART srln_instance_t *srln_instance = srln_init(); if (srln_instance) { indev_t *sink = stdin_wire(); indev_t *srln = srln_wire(srln_instance, sink); - am335x_uart_input_wire(&bbone.uart, srln); + omap_uart_input_wire(&bbone.uart, srln); am335x_irc_enable(bbone.irc_addr, AM335x_UART0_IRQ); } +#endif } Index: kernel/genarch/Makefile.inc =================================================================== --- kernel/genarch/Makefile.inc (revision 716357ff5db66f096f15e81dc5b3aa611c7a9ff0) +++ kernel/genarch/Makefile.inc (revision eef14771b77663fec606dbe440c7f1f7cb1f78be) @@ -105,7 +105,7 @@ endif -ifeq ($(CONFIG_AM335X_UART),y) +ifeq ($(CONFIG_OMAP_UART),y) GENARCH_SOURCES += \ - genarch/src/drivers/am335x/uart.c + genarch/src/drivers/omap/uart.c endif @@ -113,9 +113,4 @@ GENARCH_SOURCES += \ genarch/src/drivers/am335x/timer.c -endif - -ifeq ($(CONFIG_AMDM37X_UART),y) - GENARCH_SOURCES += \ - genarch/src/drivers/amdm37x/uart.c endif Index: kernel/genarch/include/genarch/drivers/am335x/uart.h =================================================================== --- kernel/genarch/include/genarch/drivers/am335x/uart.h (revision 716357ff5db66f096f15e81dc5b3aa611c7a9ff0) +++ kernel/genarch/include/genarch/drivers/am335x/uart.h (revision eef14771b77663fec606dbe440c7f1f7cb1f78be) @@ -37,5 +37,5 @@ #define _KERN_AM335X_UART_H_ -#include "uart_regs.h" +#include #define AM335x_UART0_BASE_ADDRESS 0x44E09000 @@ -63,24 +63,4 @@ #define AM335x_UART5_IRQ 46 -typedef struct { - am335x_uart_regs_t *regs; - indev_t *indev; - outdev_t outdev; - irq_t irq; -} am335x_uart_t; - -#ifdef CONFIG_AM335X_UART -extern bool am335x_uart_init(am335x_uart_t *uart, inr_t interrupt, - uintptr_t addr, size_t size); - -extern void am335x_uart_input_wire(am335x_uart_t *uart, indev_t *indev); -#else -static bool am335x_uart_init(am335x_uart_t *uart, inr_t interrupt, - uintptr_t addr, size_t size) -{ return true; } - -static void am335x_uart_input_wire(am335x_uart_t *uart, indev_t *indev) {} -#endif - #endif Index: rnel/genarch/include/genarch/drivers/am335x/uart_regs.h =================================================================== --- kernel/genarch/include/genarch/drivers/am335x/uart_regs.h (revision 716357ff5db66f096f15e81dc5b3aa611c7a9ff0) +++ (revision ) @@ -1,431 +1,0 @@ -/* - * Copyright (c) 2012 Jan Vesely - * Copyright (c) 2012 Maurizio Lombardi - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** @addtogroup genarch - * @{ - */ -/** - * @file - * @brief Texas Instruments AM335x UART memory mapped registers. - */ - -#ifndef _KERN_AM335X_UART_REGS_H_ -#define _KERN_AM335X_UART_REGS_H_ - -#include -#include -#include - -typedef struct { - union { - /** Stores lower part of the 14-bit baud divisor */ - ioport32_t dll; -#define AM335x_UART_DLL_MASK (0xff) - - /** Receive holding register */ - const ioport32_t rhr; -#define AM335x_UART_RHR_MASK (0xff) - - /** Transmit holding register */ - ioport32_t thr; -#define AM335x_UART_THR_MASK (0xff) - }; - - union { - /** Stores higher part of the 14-bit baud divisor */ - ioport32_t dlh; -#define AM335x_UART_DLH_MASK (0x1f) - - /** Interrupt enable registers */ - ioport32_t ier; -#define AM335x_UART_IER_RHR_IRQ_FLAG (1 << 0) -#define AM335x_UART_IER_THR_IRQ_FLAG (1 << 1) -#define AM335x_UART_IER_LINE_STS_IRQ_FLAG (1 << 2) -#define AM335x_UART_IER_MODEM_STS_IRQ_FLAG (1 << 3) -#define AM335x_UART_IER_SLEEP_MODE_FLAG (1 << 4) -#define AM335x_UART_IER_XOFF_IRQ_FLAG (1 << 5) -#define AM335x_UART_IER_RTS_IRQ_FLAG (1 << 6) -#define AM335x_UART_IER_CTS_IRQ_FLAG (1 << 7) - -#define AM335x_CIR_IER_RHR_IRQ_FLAG (1 << 0) -#define AM335x_CIR_IER_THR_IRQ_FLAG (1 << 1) -#define AM335x_CIR_IER_RX_STOP_IRQ_FLAG (1 << 2) -#define AM335x_CIR_IER_RX_OVERRUN_IRQ_FLAG (1 << 3) -#define AM335x_CIR_IER_TX_STS_IRQ_FLAG (1 << 5) - -#define AM335x_IRDA_IER_RHR_IRQ_FLAG (1 << 0) -#define AM335x_IRDA_IER_THR_IRQ_FLAG (1 << 1) -#define AM335x_IRDA_IER_LAST_RX_BYTE_IRQ_FLAG (1 << 2) -#define AM335x_IRDA_IER_RX_OVERRUN_IRQ_FLAG (1 << 3) -#define AM335x_IRDA_IER_STS_FIFO_TRIG_IRQ_FLAG (1 << 4) -#define AM335x_IRDA_IER_TX_STS_IRQ_FLAG (1 << 5) -#define AM335x_IRDA_IER_LINE_STS_IRQ_FLAG (1 << 6) -#define AM335x_IRDA_IER_EOF_IRQ_FLAG (1 << 7) - }; - - union { - /** Interrupt identification register */ - const ioport32_t iir; -#define AM335x_UART_IIR_IRQ_PENDING_FLAG (1 << 0) -#define AM335x_UART_IIR_TYPE_MASK (0x1f) -#define AM335x_UART_IIR_TYPE_SHIFT (1) -#define AM335x_UART_IIR_FCR_MASK (0x3) -#define AM335x_UART_IIR_FCR_SHIFT (6) - -#define AM335x_CIR_IIR_RHR_IRQ_FLAG (1 << 0) -#define AM335x_CIR_IIR_THR_IRQ_FLAG (1 << 1) -#define AM335x_CIR_IIR_RX_STOP_IRQ_FLAG (1 << 2) -#define AM335x_CIR_IIR_RX_OE_IRQ_FLAG (1 << 3) -#define AM335x_CIR_IIR_TX_STS_IRQ_FLAG (1 << 5) - -#define AM335x_IRDA_IIR_RHR_IRQ_FLAG (1 << 0) -#define AM335x_IRDA_IIR_THR_IRQ_FLAG (1 << 1) -#define AM335x_IRDA_IIR_RX_FIFO_LB_IRQ_FLAG (1 << 2) -#define AM335x_IRDA_IIR_RX_OE_IRQ_FLAG (1 << 3) -#define AM335x_IRDA_IIR_STS_FIFO_IRQ_FLAG (1 << 4) -#define AM335x_IRDA_IIR_TX_STS_IRQ_FLAG (1 << 5) -#define AM335x_IRDA_IIR_LINE_STS_IRQ_FLAG (1 << 6) -#define AM335x_IRDA_IIR_EOF_IRQ_FLAG (1 << 7) - - /** FIFO control register */ - ioport32_t fcr; -#define AM335x_UART_FCR_FIFO_EN_FLAG (1 << 0) -#define AM335x_UART_FCR_RX_FIFO_CLR_FLAG (1 << 1) -#define AM335x_UART_FCR_TX_FIFO_CLR_FLAG (1 << 3) -#define AM335x_UART_FCR_DMA_MODE_FLAG (1 << 4) - -#define AM335x_UART_FCR_TX_FIFO_TRIG_MASK (0x3) -#define AM335x_UART_FCR_TX_FIFO_TRIG_SHIFT (4) - -#define AM335x_UART_FCR_RX_FIFO_TRIG_MASK (0x3) -#define AM335x_UART_FCR_RX_FIFO_TRIG_SHIFT (6) - - /** Enhanced feature register */ - ioport32_t efr; -#define AM335x_UART_EFR_SW_FLOW_CTRL_RX_MASK (0x3) -#define AM335x_UART_EFR_SW_FLOW_CTRL_RX_SHIFT (0) -#define AM335x_UART_EFR_SW_FLOW_CTRL_TX_MASK (0x3) -#define AM335x_UART_EFR_SW_FLOW_CTRL_TX_SHIFT (2) - -#define AM335x_UART_EFR_SW_FLOW_CTRL_NONE (0x0) -#define AM335x_UART_EFR_SW_FLOW_CTRL_X2 (0x1) -#define AM335x_UART_EFR_SW_FLOW_CTRL_X1 (0x2) -#define AM335x_UART_EFR_SW_FLOW_CTRL_XBOTH (0x3) - -#define AM335x_UART_EFR_ENH_FLAG (1 << 4) -#define AM335x_UART_EFR_SPEC_CHAR_FLAG (1 << 5) -#define AM335x_UART_EFR_AUTO_RTS_EN_FLAG (1 << 6) -#define AM335x_UART_EFR_AUTO_CTS_EN_FLAG (1 << 7) - }; - - /** Line control register */ - ioport32_t lcr; -#define AM335x_UART_LCR_CHAR_LENGTH_MASK (0x3) -#define AM335x_UART_LCR_CHAR_LENGTH_SHIFT (0) -#define AM335x_UART_LCR_CHAR_LENGTH_5BITS (0x0) -#define AM335x_UART_LCR_CHAR_LENGTH_6BITS (0x1) -#define AM335x_UART_LCR_CHAR_LENGTH_7BITS (0x2) -#define AM335x_UART_LCR_CHAR_LENGTH_8BITS (0x3) -#define AM335x_UART_LCR_NB_STOP_FLAG (1 << 2) -#define AM335x_UART_LCR_PARITY_EN_FLAG (1 << 3) -#define AM335x_UART_LCR_PARITY_TYPE1_FLAG (1 << 4) -#define AM335x_UART_LCR_PARITY_TYPE2_FLAG (1 << 5) -#define AM335x_UART_LCR_BREAK_EN_FLAG (1 << 6) -#define AM335x_UART_LCR_DIV_EN_FLAG (1 << 7) - - - union { - /** Modem control register */ - ioport32_t mcr; -#define AM335x_UART_MCR_DTR_FLAG (1 << 0) -#define AM335x_UART_MCR_RTS_FLAG (1 << 1) -#define AM335x_UART_MCR_RI_STS_CH_FLAG (1 << 2) -#define AM335x_UART_MCR_CD_STS_CH_FLAG (1 << 3) -#define AM335x_UART_MCR_LOOPBACK_EN_FLAG (1 << 4) -#define AM335x_UART_MCR_XON_EN_FLAG (1 << 5) -#define AM335x_UART_MCR_TCR_TLR_FLAG (1 << 6) - - /** UART: XON1 char, IRDA: ADDR1 address */ - ioport32_t xon1_addr1; -#define AM335x_UART_XON1_ADDR1_MASK (0xff) - }; - - union { - /** Line status register */ - const ioport32_t lsr; -#define AM335x_UART_LSR_RX_FIFO_E_FLAG (1 << 0) -#define AM335x_UART_LSR_RX_OE_FLAG (1 << 1) -#define AM335x_UART_LSR_RX_PE_FLAG (1 << 2) -#define AM335x_UART_LSR_RX_FE_FLAG (1 << 3) -#define AM335x_UART_LSR_RX_BI_FLAG (1 << 4) -#define AM335x_UART_LSR_TX_FIFO_E_FLAG (1 << 5) -#define AM335x_UART_LSR_TX_SR_E_FLAG (1 << 6) -#define AM335x_UART_LSR_RX_FIFO_STS_FLAG (1 << 7) - -#define AM335x_CIR_LSR_RX_FIFO_E_FLAG (1 << 0) -#define AM335x_CIR_LSR_RX_STOP_FLAG (1 << 5) -#define AM335x_CIR_LSR_THR_EMPTY_FLAG (1 << 7) - -#define AM335x_IRDA_LSR_RX_FIFO_E_FLAG (1 << 0) -#define AM335x_IRDA_LSR_STS_FIFO_E_FLAG (1 << 1) -#define AM335x_IRDA_LSR_CRC_FLAG (1 << 2) -#define AM335x_IRDA_LSR_ABORT_FLAG (1 << 3) -#define AM335x_IRDA_LSR_FTL_FLAG (1 << 4) -#define AM335x_IRDA_LSR_RX_LAST_FLAG (1 << 5) -#define AM335x_IRDA_LSR_STS_FIFO_FULL_FLAG (1 << 6) -#define AM335x_IRDA_LSR_THR_EMPTY_FLAG (1 << 7) - - /** UART: XON2 char, IRDA: ADDR2 address */ - ioport32_t xon2_addr2; - }; - - union { - /** Modem status register */ - const ioport32_t msr; -#define AM335x_UART_MSR_CTS_STS_FLAG (1 << 0) -#define AM335x_UART_MSR_DSR_STS_FLAG (1 << 1) -#define AM335x_UART_MSR_RI_STS_FLAG (1 << 2) -#define AM335x_UART_MSR_DCD_STS_FLAG (1 << 3) -#define AM335x_UART_MSR_NCTS_STS_FLAG (1 << 4) -#define AM335x_UART_MSR_NDSR_STS_FLAG (1 << 5) -#define AM335x_UART_MSR_NRI_STS_FLAG (1 << 6) -#define AM335x_UART_MSR_NCD_STS_FLAG (1 << 7) - - /** Transmission control register */ - ioport32_t tcr; -#define AM335x_UART_TCR_FIFO_TRIG_MASK (0xf) -#define AM335x_UART_TCR_FIFO_TRIG_HALT_SHIFT (0) -#define AM335x_UART_TCR_FIFO_TRIG_START_SHIFT (4) - - /** UART: XOFF1 char */ - ioport32_t xoff1; -#define AM335x_UART_XOFF1_MASK (0xff) - }; - - union { - /* Scratchpad register, does nothing */ - ioport32_t spr; -#define AM335x_UART_SPR_MASK (0xff) - - /* Trigger level register */ - ioport32_t tlr; -#define AM335x_UART_TLR_LEVEL_MASK (0xf) -#define AM335x_UART_TLR_TX_FIFO_TRIG_SHIFT (0) -#define AM335x_UART_TLR_RX_FIFO_TRIG_SHIFT (4) - - /** UART: XOFF2 char */ - ioport32_t xoff2; -#define AM335x_UART_XOFF2_MASK (0xff) - }; - - /** Mode definition register. */ - ioport32_t mdr1; -#define AM335x_UART_MDR_MS_MASK (0x7) -#define AM335x_UART_MDR_MS_SHIFT (0) -#define AM335x_UART_MDR_MS_UART16 (0x0) -#define AM335x_UART_MDR_MS_SIR (0x1) -#define AM335x_UART_MDR_MS_UART16_AUTO (0x2) -#define AM335x_UART_MDR_MS_UART13 (0x3) -#define AM335x_UART_MDR_MS_MIR (0x4) -#define AM335x_UART_MDR_MS_FIR (0x5) -#define AM335x_UART_MDR_MS_CIR (0x6) -#define AM335x_UART_MDR_MS_DISABLE (0x7) - -#define AM335x_UART_MDR_IR_SLEEP_FLAG (1 << 3) -#define AM335x_UART_MDR_SET_TXIR_FLAG (1 << 4) -#define AM335x_UART_MDR_SCT_FLAG (1 << 5) -#define AM335x_UART_MDR_SIP_FLAG (1 << 6) -#define AM335x_UART_MDR_FRAME_END_MODE_FLAG (1 << 7) - - /** Mode definition register */ - ioport32_t mdr2; -#define AM335x_UART_MDR_IRTX_UNDERRUN_FLAG (1 << 0) -#define AM335x_UART_MDR_STS_FIFO_TRIG_MASK (0x3) -#define AM335x_UART_MDR_STS_FIFO_TRIG_SHIFT (1) -#define AM335x_UART_MDR_PULSE_SHAPING_FLAG (1 << 3) -#define AM335x_UART_MDR_CIR_PULSE_MODE_MASK (0x3) -#define AM335x_UART_MDR_CIR_PULSE_MODE_SHIFT (4) -#define AM335x_UART_MDR_IRRXINVERT_FLAG (1 << 6) - - union { - /** Status FIFO line status register (IrDA only) */ - const ioport32_t sflsr; -#define AM335x_IRDA_SFLSR_CRC_ERROR_FLAG (1 << 1) -#define AM335x_IRDA_SFLSR_ABORT_FLAG (1 << 2) -#define AM335x_IRDA_SFLSR_FTL_FLAG (1 << 3) -#define AM335x_IRDA_SFLSR_OE_FLAG (1 << 4) - - /** Transmit frame length low (IrDA only) */ - ioport32_t txfll; -#define AM335x_UART_TXFLL_MASK (0xff) - }; - - union { - /** Dummy register to restart TX or RX (IrDA only) */ - const ioport32_t resume; - /** Transmit frame length high (IrDA only) */ - ioport32_t txflh; -#define AM335x_UART_TXFLH_MASK (0xff) - }; - - union { - /** Status FIFO register low (IrDA only) */ - const ioport32_t sfregl; -#define AM335x_UART_SFREGL_MASK (0xff) - /** Received frame length low (IrDA only) */ - ioport32_t rxfll; -#define AM335x_UART_RXFLL_MASK (0xff) - }; - - union { - /** Status FIFO register high (IrDA only) */ - const ioport32_t sfregh; -#define AM335x_UART_SFREGH_MASK (0xf) - /** Received frame length high (IrDA only) */ - ioport32_t rxflh; -#define AM335x_UART_RXFLH_MASK (0xf) - }; - - union { - /** UART autobauding status register */ - const ioport32_t uasr; -#define AM335x_UART_UASR_SPEED_MASK (0x1f) -#define AM335x_UART_UASR_SPEED_SHIFT (0) -#define AM335x_UART_UASR_8BIT_CHAR_FLAG (1 << 5) -#define AM335x_UART_UASR_PARITY_MASK (0x3) -#define AM335x_UART_UASR_PARITY_SHIFT (6) - - /** BOF control register (IrDA only) */ - ioport32_t blr; -#define AM335x_IRDA_BLR_XBOF_TYPE_FLAG (1 << 6) -#define AM335x_IRDA_BLR_STS_FIFO_RESET (1 << 7) - }; - - /** Auxiliary control register (IrDA only) */ - ioport32_t acreg; -#define AM335x_IRDA_ACREG_EOT_EN_FLAG (1 << 0) -#define AM335x_IRDA_ACREG_ABORT_EN_FLAG (1 << 1) -#define AM335x_IRDA_ACREG_SCTX_EN_FLAG (1 << 2) -#define AM335x_IRDA_ACREG_SEND_SIP_FLAG (1 << 3) -#define AM335x_IRDA_ACREG_DIS_TX_UNDERRUN_FLAG (1 << 4) -#define AM335x_IRDA_ACREG_DIS_IR_RX_FLAG (1 << 5) -#define AM335x_IRDA_ACREG_SD_MOD_FLAG (1 << 6) -#define AM335x_IRDA_ACREG_PULSE_TYPE_FLAG (1 << 7) - - /** Supplementary control register */ - ioport32_t scr; -#define AM335x_UART_SCR_DMA_MODE_CTL_FLAG (1 << 0) -#define AM335x_UART_SCR_DMA_MODE_MASK (0x3) -#define AM335x_UART_SCR_DMA_MODE_SHIFT (1) -#define AM335x_UART_SCR_TX_EMPTY_CTL_IRQ_FLAG (1 << 3) -#define AM335x_UART_SCR_RX_CTS_WU_EN_FLAG (1 << 4) -#define AM335x_UART_SCR_TX_TRIG_GRANU1_FLAG (1 << 6) -#define AM335x_UART_SCR_RX_TRIG_GRANU1_FLAG (1 << 7) - - /** Supplementary status register */ - const ioport32_t ssr; -#define AM335x_UART_SSR_TX_FIFO_FULL_FLAG (1 << 0) -#define AM335x_UART_SSR_RX_CTS_WU_STS_FLAG (1 << 1) -#define AM335x_UART_SSR_DMA_COUNTER_RESET_FLAG (1 << 2) - - /** BOF Length register (IrDA only)*/ - ioport32_t eblr; -#define AM335x_IRDA_EBLR_DISABLED (0x00) -#define AM335x_IRDA_EBLR_RX_STOP_BITS(bits) (bits & 0xff) - - uint32_t padd0_; - - /** Module version register */ - const ioport32_t mvr; -#define AM335x_UART_MVR_MINOR_MASK (0xf) -#define AM335x_UART_MVR_MINOR_SHIFT (0) -#define AM335x_UART_MVR_MAJOR_MASK (0xf) -#define AM335x_UART_MVR_MAJOR_SHIFT (4) - - /** System configuration register */ - ioport32_t sysc; -#define AM335x_UART_SYSC_AUTOIDLE_FLAG (1 << 0) -#define AM335x_UART_SYSC_SOFTRESET_FLAG (1 << 1) -#define AM335x_UART_SYSC_ENWAKEUP_FLAG (1 << 2) -#define AM335x_UART_SYSC_IDLE_MODE_MASK (0x3) -#define AM335x_UART_SYSC_IDLE_MODE_SHIFT (3) -#define AM335x_UART_SYSC_IDLE_MODE_FORCE (0x0) -#define AM335x_UART_SYSC_IDLE_MODE_NO (0x1) -#define AM335x_UART_SYSC_IDLE_MODE_SMART (0x2) - - /** System status register */ - const ioport32_t syss; -#define AM335x_UART_SYSS_RESETDONE_FLAG (1 << 0) - - /** Wake-up enable register */ - ioport32_t wer; -#define AM335x_UART_WER_CTS_ACTIVITY_FLAG (1 << 0) -#define AM335x_UART_WER_RI_ACTIVITY_FLAG (1 << 2) -#define AM335x_UART_WER_RX_ACTIVITY_FLAG (1 << 4) -#define AM335x_UART_WER_RHR_IRQ_FLAG (1 << 5) -#define AM335x_UART_WER_RLS_IRQ_FLAG (1 << 6) -#define AM335x_UART_WER_TX_WAKEUP_EN_FLAG (1 << 7) - - /** Carrier frequency prescaler */ - ioport32_t cfps; -#define AM335x_UART_CFPS_MASK (0xff) - - /** Number of bytes in RX fifo */ - const ioport32_t rx_fifo_lvl; -#define AM335x_UART_RX_FIFO_LVL_MASK (0xff) - - /** Number of bytes in TX fifo */ - const ioport32_t tx_fifo_lvl; -#define AM335x_UART_TX_FIFO_LVL_MASK (0xff) - - /** RX/TX empty interrupts */ - ioport32_t ier2; -#define AM335x_UART_IER2_RX_FIFO_EMPTY_IRQ_EN_FLAG (1 << 0) -#define AM335x_UART_IER2_TX_FIFO_EMPTY_IRQ_EN_FLAG (1 << 1) - - /** RX/TX empty status */ - ioport32_t isr2; -#define AM335x_UART_ISR2_RX_FIFO_EMPTY_FLAG (1 << 0) -#define AM335x_UART_ISR2_TX_FIFO_EMPTY_FLAG (1 << 1) - - /** Set the sample per bit if non default frequency is used */ - ioport32_t freq_sel; -#define AM335x_UART_FREQ_SEL_MASK (0x000000FF) - - uint32_t padd2_[2]; - - /** Mode definition register 3 */ - ioport32_t mdr3; -#define AM335x_UART_MDR3_DIS_CIR_RX_DEMOD_FLAG (1 << 0) -} am335x_uart_regs_t; - -#endif - -/** - * @} - */ Index: kernel/genarch/include/genarch/drivers/amdm37x/uart.h =================================================================== --- kernel/genarch/include/genarch/drivers/amdm37x/uart.h (revision 716357ff5db66f096f15e81dc5b3aa611c7a9ff0) +++ kernel/genarch/include/genarch/drivers/amdm37x/uart.h (revision eef14771b77663fec606dbe440c7f1f7cb1f78be) @@ -37,5 +37,5 @@ #define _AMDM37x_UART_H_ -#include "uart_regs.h" +#include /* AMDM37x TRM p. 2950 */ @@ -56,15 +56,4 @@ #define AMDM37x_UART4_IRQ 80 /* AMDM37x TRM p. 2418 */ -typedef struct { - amdm37x_uart_regs_t *regs; - indev_t *indev; - outdev_t outdev; - irq_t irq; -} amdm37x_uart_t; - - -bool amdm37x_uart_init(amdm37x_uart_t *, inr_t, uintptr_t, size_t); -void amdm37x_uart_input_wire(amdm37x_uart_t *, indev_t *); - #endif Index: rnel/genarch/include/genarch/drivers/amdm37x/uart_regs.h =================================================================== --- kernel/genarch/include/genarch/drivers/amdm37x/uart_regs.h (revision 716357ff5db66f096f15e81dc5b3aa611c7a9ff0) +++ (revision ) @@ -1,431 +1,0 @@ -/* - * Copyright (c) 2012 Jan Vesely - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** @addtogroup genarch - * @{ - */ -/** - * @file - * @brief Texas Instruments AMDM37x UART memory mapped registers. - */ - -#ifndef KERN_AMDM37x_UART_H_ -#define KERN_AMDM37x_UART_H_ - -#include -#include -#include - -typedef struct { - union { - /** Stores lower part of the 14-bit baud divisor */ - ioport32_t dll; -#define AMDM37x_UART_DLL_MASK (0xff) - - /** Receive holding register */ - const ioport32_t rhr; -#define AMDM37x_UART_RHR_MASK (0xff) - - /** Transmit holding register */ - ioport32_t thr; -#define AMDM37x_UART_THR_MASK (0xff) - }; - - union { - /** Stores higher part of the 14-bit baud divisor */ - ioport32_t dlh; -#define AMDM37x_UART_DLH_MASK (0x1f) - - /** Interrupt enable registers */ - ioport32_t ier; -#define AMDM37x_UART_IER_RHR_IRQ_FLAG (1 << 0) -#define AMDM37x_UART_IER_THR_IRQ_FLAG (1 << 1) -#define AMDM37x_UART_IER_LINE_STS_IRQ_FLAG (1 << 2) -#define AMDM37x_UART_IER_MODEM_STS_IRQ_FLAG (1 << 3) -#define AMDM37x_UART_IER_SLEEP_MODE_FLAG (1 << 4) -#define AMDM37x_UART_IER_XOFF_IRQ_FLAG (1 << 5) -#define AMDM37x_UART_IER_RTS_IRQ_FLAG (1 << 6) -#define AMDM37x_UART_IER_CTS_IRQ_FLAG (1 << 7) - -#define AMDM37x_CIR_IER_RHR_IRQ_FLAG (1 << 0) -#define AMDM37x_CIR_IER_THR_IRQ_FLAG (1 << 1) -#define AMDM37x_CIR_IER_RX_STOP_IRQ_FLAG (1 << 2) -#define AMDM37x_CIR_IER_RX_OVERRUN_IRQ_FLAG (1 << 3) -#define AMDM37x_CIR_IER_TX_STS_IRQ_FLAG (1 << 5) - -#define AMDM37x_IRDA_IER_RHR_IRQ_FLAG (1 << 0) -#define AMDM37x_IRDA_IER_THR_IRQ_FLAG (1 << 1) -#define AMDM37x_IRDA_IER_LAST_RX_BYTE_IRQ_FLAG (1 << 2) -#define AMDM37x_IRDA_IER_RX_OVERRUN_IRQ_FLAG (1 << 3) -#define AMDM37x_IRDA_IER_STS_FIFO_TRIG_IRQ_FLAG (1 << 4) -#define AMDM37x_IRDA_IER_TX_STS_IRQ_FLAG (1 << 5) -#define AMDM37x_IRDA_IER_LINE_STS_IRQ_FLAG (1 << 6) -#define AMDM37x_IRDA_IER_EOF_IRQ_FLAG (1 << 7) - }; - - union { - /** Interrupt identification register */ - const ioport32_t iir; -#define AMDM37x_UART_IIR_IRQ_PENDING_FLAG (1 << 0) -#define AMDM37x_UART_IIR_TYPE_MASK (0x1f) -#define AMDM37x_UART_IIR_TYPE_SHIFT (1) -#define AMDM37x_UART_IIR_FCR_MASK (0x3) -#define AMDM37x_UART_IIR_FCR_SHIFT (6) - -#define AMDM37x_CIR_IIR_RHR_IRQ_FLAG (1 << 0) -#define AMDM37x_CIR_IIR_THR_IRQ_FLAG (1 << 1) -#define AMDM37x_CIR_IIR_RX_STOP_IRQ_FLAG (1 << 2) -#define AMDM37x_CIR_IIR_RX_OE_IRQ_FLAG (1 << 3) -#define AMDM37x_CIR_IIR_TX_STS_IRQ_FLAG (1 << 5) - -#define AMDM37x_IRDA_IIR_RHR_IRQ_FLAG (1 << 0) -#define AMDM37x_IRDA_IIR_THR_IRQ_FLAG (1 << 1) -#define AMDM37x_IRDA_IIR_RX_FIFO_LB_IRQ_FLAG (1 << 2) -#define AMDM37x_IRDA_IIR_RX_OE_IRQ_FLAG (1 << 3) -#define AMDM37x_IRDA_IIR_STS_FIFO_IRQ_FLAG (1 << 4) -#define AMDM37x_IRDA_IIR_TX_STS_IRQ_FLAG (1 << 5) -#define AMDM37x_IRDA_IIR_LINE_STS_IRQ_FLAG (1 << 6) -#define AMDM37x_IRDA_IIR_EOF_IRQ_FLAG (1 << 7) - - /** FIFO control register */ - ioport32_t fcr; -#define AMDM37x_UART_FCR_FIFO_EN_FLAG (1 << 0) -#define AMDM37x_UART_FCR_RX_FIFO_CLR_FLAG (1 << 1) -#define AMDM37x_UART_FCR_TX_FIFO_CLR_FLAG (1 << 3) -#define AMDM37x_UART_FCR_DMA_MODE_FLAG (1 << 4) - -#define AMDM37x_UART_FCR_TX_FIFO_TRIG_MASK (0x3) -#define AMDM37x_UART_FCR_TX_FIFO_TRIG_SHIFT (4) - -#define AMDM37x_UART_FCR_RX_FIFO_TRIG_MASK (0x3) -#define AMDM37x_UART_FCR_RX_FIFO_TRIG_SHIFT (6) - - /** Enhanced feature register */ - ioport32_t efr; -#define AMDM37x_UART_EFR_SW_FLOW_CTRL_RX_MASK (0x3) -#define AMDM37x_UART_EFR_SW_FLOW_CTRL_RX_SHIFT (0) -#define AMDM37x_UART_EFR_SW_FLOW_CTRL_TX_MASK (0x3) -#define AMDM37x_UART_EFR_SW_FLOW_CTRL_TX_SHIFT (2) - -#define AMDM37x_UART_EFR_SW_FLOW_CTRL_NONE (0x0) -#define AMDM37x_UART_EFR_SW_FLOW_CTRL_X2 (0x1) -#define AMDM37x_UART_EFR_SW_FLOW_CTRL_X1 (0x2) -#define AMDM37x_UART_EFR_SW_FLOW_CTRL_XBOTH (0x3) - -#define AMDM37x_UART_EFR_ENH_FLAG (1 << 4) -#define AMDM37x_UART_EFR_SPEC_CHAR_FLAG (1 << 5) -#define AMDM37x_UART_EFR_AUTO_RTS_EN_FLAG (1 << 6) -#define AMDM37x_UART_EFR_AUTO_CTS_EN_FLAG (1 << 7) - }; - - /** Line control register */ - ioport32_t lcr; -#define AMDM37x_UART_LCR_CHAR_LENGTH_MASK (0x3) -#define AMDM37x_UART_LCR_CHAR_LENGTH_SHIFT (0) -#define AMDM37x_UART_LCR_CHAR_LENGTH_5BITS (0x0) -#define AMDM37x_UART_LCR_CHAR_LENGTH_6BITS (0x1) -#define AMDM37x_UART_LCR_CHAR_LENGTH_7BITS (0x2) -#define AMDM37x_UART_LCR_CHAR_LENGTH_8BITS (0x3) -#define AMDM37x_UART_LCR_NB_STOP_FLAG (1 << 2) -#define AMDM37x_UART_LCR_PARITY_EN_FLAG (1 << 3) -#define AMDM37x_UART_LCR_PARITY_TYPE1_FLAG (1 << 4) -#define AMDM37x_UART_LCR_PARITY_TYPE2_FLAG (1 << 5) -#define AMDM37x_UART_LCR_BREAK_EN_FLAG (1 << 6) -#define AMDM37x_UART_LCR_DIV_EN_FLAG (1 << 7) - - - union { - /** Modem control register */ - ioport32_t mcr; -#define AMDM37x_UART_MCR_DTR_FLAG (1 << 0) -#define AMDM37x_UART_MCR_RTS_FLAG (1 << 1) -#define AMDM37x_UART_MCR_RI_STS_CH_FLAG (1 << 2) -#define AMDM37x_UART_MCR_CD_STS_CH_FLAG (1 << 3) -#define AMDM37x_UART_MCR_LOOPBACK_EN_FLAG (1 << 4) -#define AMDM37x_UART_MCR_XON_EN_FLAG (1 << 5) -#define AMDM37x_UART_MCR_TCR_TLR_FLAG (1 << 6) - - /** UART: XON1 char, IRDA: ADDR1 address */ - ioport32_t xon1_addr1; -#define AMDM37x_UART_XON1_ADDR1_MASK (0xff) - }; - - union { - /** Line status register */ - const ioport32_t lsr; -#define AMDM37x_UART_LSR_RX_FIFO_E_FLAG (1 << 0) -#define AMDM37x_UART_LSR_RX_OE_FLAG (1 << 1) -#define AMDM37x_UART_LSR_RX_PE_FLAG (1 << 2) -#define AMDM37x_UART_LSR_RX_FE_FLAG (1 << 3) -#define AMDM37x_UART_LSR_RX_BI_FLAG (1 << 4) -#define AMDM37x_UART_LSR_TX_FIFO_E_FLAG (1 << 5) -#define AMDM37x_UART_LSR_TX_SR_E_FLAG (1 << 6) -#define AMDM37x_UART_LSR_RX_FIFO_STS_FLAG (1 << 7) - -#define AMDM37x_CIR_LSR_RX_FIFO_E_FLAG (1 << 0) -#define AMDM37x_CIR_LSR_RX_STOP_FLAG (1 << 5) -#define AMDM37x_CIR_LSR_THR_EMPTY_FLAG (1 << 7) - -#define AMDM37x_IRDA_LSR_RX_FIFO_E_FLAG (1 << 0) -#define AMDM37x_IRDA_LSR_STS_FIFO_E_FLAG (1 << 1) -#define AMDM37x_IRDA_LSR_CRC_FLAG (1 << 2) -#define AMDM37x_IRDA_LSR_ABORT_FLAG (1 << 3) -#define AMDM37x_IRDA_LSR_FTL_FLAG (1 << 4) -#define AMDM37x_IRDA_LSR_RX_LAST_FLAG (1 << 5) -#define AMDM37x_IRDA_LSR_STS_FIFO_FULL_FLAG (1 << 6) -#define AMDM37x_IRDA_LSR_THR_EMPTY_FLAG (1 << 7) - - /** UART: XON2 char, IRDA: ADDR2 address */ - ioport32_t xon2_addr2; - }; - - union { - /** Modem status register */ - const ioport32_t msr; -#define AMDM37x_UART_MSR_CTS_STS_FLAG (1 << 0) -#define AMDM37x_UART_MSR_DSR_STS_FLAG (1 << 1) -#define AMDM37x_UART_MSR_RI_STS_FLAG (1 << 2) -#define AMDM37x_UART_MSR_DCD_STS_FLAG (1 << 3) -#define AMDM37x_UART_MSR_NCTS_STS_FLAG (1 << 4) -#define AMDM37x_UART_MSR_NDSR_STS_FLAG (1 << 5) -#define AMDM37x_UART_MSR_NRI_STS_FLAG (1 << 6) -#define AMDM37x_UART_MSR_NCD_STS_FLAG (1 << 7) - - /** Transmission control register */ - ioport32_t tcr; -#define AMDM37x_UART_TCR_FIFO_TRIG_MASK (0xf) -#define AMDM37x_UART_TCR_FIFO_TRIG_HALT_SHIFT (0) -#define AMDM37x_UART_TCR_FIFO_TRIG_START_SHIFT (4) - - /** UART: XOFF1 char */ - ioport32_t xoff1; -#define AMDM37x_UART_XOFF1_MASK (0xff) - }; - - union { - /* Scratchpad register, does nothing */ - ioport32_t spr; -#define AMDM37x_UART_SPR_MASK (0xff) - - /* Trigger level register */ - ioport32_t tlr; -#define AMDM37x_UART_TLR_LEVEL_MASK (0xf) -#define AMDM37x_UART_TLR_TX_FIFO_TRIG_SHIFT (0) -#define AMDM37x_UART_TLR_RX_FIFO_TRIG_SHIFT (4) - - /** UART: XOFF2 char */ - ioport32_t xoff2; -#define AMDM37x_UART_XOFF2_MASK (0xff) - }; - - /** Mode definition register. */ - ioport32_t mdr1; -#define AMDM37x_UART_MDR_MS_MASK (0x7) -#define AMDM37x_UART_MDR_MS_SHIFT (0) -#define AMDM37x_UART_MDR_MS_UART16 (0x0) -#define AMDM37x_UART_MDR_MS_SIR (0x1) -#define AMDM37x_UART_MDR_MS_UART16_AUTO (0x2) -#define AMDM37x_UART_MDR_MS_UART13 (0x3) -#define AMDM37x_UART_MDR_MS_MIR (0x4) -#define AMDM37x_UART_MDR_MS_FIR (0x5) -#define AMDM37x_UART_MDR_MS_CIR (0x6) -#define AMDM37x_UART_MDR_MS_DISABLE (0x7) - -#define AMDM37x_UART_MDR_IR_SLEEP_FLAG (1 << 3) -#define AMDM37x_UART_MDR_SET_TXIR_FLAG (1 << 4) -#define AMDM37x_UART_MDR_SCT_FLAG (1 << 5) -#define AMDM37x_UART_MDR_SIP_FLAG (1 << 6) -#define AMDM37x_UART_MDR_FRAME_END_MODE_FLAG (1 << 7) - - /** Mode definition register */ - ioport32_t mdr2; -#define AMDM37x_UART_MDR_IRTX_UNDERRUN_FLAG (1 << 0) -#define AMDM37x_UART_MDR_STS_FIFO_TRIG_MASK (0x3) -#define AMDM37x_UART_MDR_STS_FIFO_TRIG_SHIFT (1) -#define AMDM37x_UART_MDR_PULSE_SHAPING_FLAG (1 << 3) -#define AMDM37x_UART_MDR_CIR_PULSE_MODE_MASK (0x3) -#define AMDM37x_UART_MDR_CIR_PULSE_MODE_SHIFT (4) -#define AMDM37x_UART_MDR_IRRXINVERT_FLAG (1 << 6) - - - /* UART3 specific */ - union { - /** Status FIFO line status register (IrDA only) */ - const ioport32_t sflsr; -#define AMDM37x_IRDA_SFLSR_CRC_ERROR_FLAG (1 << 1) -#define AMDM37x_IRDA_SFLSR_ABORT_FLAG (1 << 2) -#define AMDM37x_IRDA_SFLSR_FTL_FLAG (1 << 3) -#define AMDM37x_IRDA_SFLSR_OE_FLAG (1 << 4) - - /** Transmit frame length low (IrDA only) */ - ioport32_t txfll; -#define AMDM37x_UART_TXFLL_MASK (0xff) - }; - - /* UART3 specific */ - union { - /** Dummy register to restart TX or RX (IrDA only) */ - const ioport32_t resume; - /** Transmit frame length high (IrDA only) */ - ioport32_t txflh; -#define AMDM37x_UART_TXFLH_MASK (0xff) - }; - - /* UART3 specific */ - union { - /** Status FIFO register low (IrDA only) */ - const ioport32_t sfregl; -#define AMDM37x_UART_SFREGL_MASK (0xff) - /** Received frame length low (IrDA only) */ - ioport32_t rxfll; -#define AMDM37x_UART_RXFLL_MASK (0xff) - }; - - /* UART3 specific */ - union { - /** Status FIFO register high (IrDA only) */ - const ioport32_t sfregh; -#define AMDM37x_UART_SFREGH_MASK (0xf) - /** Received frame length high (IrDA only) */ - ioport32_t rxflh; -#define AMDM37x_UART_RXFLH_MASK (0xf) - }; - - union { - /** UART autobauding status register */ - const ioport32_t uasr; -#define AMDM37x_UART_UASR_SPEED_MASK (0x1f) -#define AMDM37x_UART_UASR_SPEED_SHIFT (0) -#define AMDM37x_UART_UASR_8BIT_CHAR_FLAG (1 << 5) -#define AMDM37x_UART_UASR_PARITY_MASK (0x3) -#define AMDM37x_UART_UASR_PARITY_SHIFT (6) - - /** BOF control register (IrDA only) */ - ioport32_t blr; /* UART3 specific */ -#define AMDM37x_IRDA_BLR_XBOF_TYPE_FLAG (1 << 6) -#define AMDM37x_IRDA_BLR_STS_FIFO_RESET (1 << 7) - }; - - /** Auxiliary control register (IrDA only) */ - ioport32_t acreg; /* UART3 specific */ -#define AMDM37x_IRDA_ACREG_EOT_EN_FLAG (1 << 0) -#define AMDM37x_IRDA_ACREG_ABORT_EN_FLAG (1 << 1) -#define AMDM37x_IRDA_ACREG_SCTX_EN_FLAG (1 << 2) -#define AMDM37x_IRDA_ACREG_SEND_SIP_FLAG (1 << 3) -#define AMDM37x_IRDA_ACREG_DIS_TX_UNDERRUN_FLAG (1 << 4) -#define AMDM37x_IRDA_ACREG_DIS_IR_RX_FLAG (1 << 5) -#define AMDM37x_IRDA_ACREG_SD_MOD_FLAG (1 << 6) -#define AMDM37x_IRDA_ACREG_PULSE_TYPE_FLAG (1 << 7) - - /** Supplementary control register */ - ioport32_t scr; -#define AMDM37x_UART_SCR_DMA_MODE_CTL_FLAG (1 << 0) -#define AMDM37x_UART_SCR_DMA_MODE_MASK (0x3) -#define AMDM37x_UART_SCR_DMA_MODE_SHIFT (1) -#define AMDM37x_UART_SCR_TX_EMPTY_CTL_IRQ_FLAG (1 << 3) -#define AMDM37x_UART_SCR_RX_CTS_WU_EN_FLAG (1 << 4) -#define AMDM37x_UART_SCR_TX_TRIG_GRANU1_FLAG (1 << 6) -#define AMDM37x_UART_SCR_RX_TRIG_GRANU1_FLAG (1 << 7) - - /** Supplementary status register */ - const ioport32_t ssr; -#define AMDM37x_UART_SSR_TX_FIFO_FULL_FLAG (1 << 0) -#define AMDM37x_UART_SSR_RX_CTS_WU_STS_FLAG (1 << 1) -#define AMDM37x_UART_SSR_DMA_COUNTER_RESET_FLAG (1 << 2) - - /** BOF Length register (IrDA only)*/ - ioport32_t eblr; /* UART3 specific */ -#define AMDM37x_IRDA_EBLR_DISABLED (0x00) -#define AMDM37x_IRDA_EBLR_RX_STOP_BITS(bits) (bits & 0xff) - - uint32_t padd0_; - - /** Module version register */ - const ioport32_t mvr; -#define AMDM37x_UART_MVR_MINOR_MASK (0xf) -#define AMDM37x_UART_MVR_MINOR_SHIFT (0) -#define AMDM37x_UART_MVR_MAJOR_MASK (0xf) -#define AMDM37x_UART_MVR_MAJOR_SHIFT (4) - - /** System configuration register */ - ioport32_t sysc; -#define AMDM37x_UART_SYSC_AUTOIDLE_FLAG (1 << 0) -#define AMDM37x_UART_SYSC_SOFTRESET_FLAG (1 << 1) -#define AMDM37x_UART_SYSC_ENWAKEUP_FLAG (1 << 2) -#define AMDM37x_UART_SYSC_IDLE_MODE_MASK (0x3) -#define AMDM37x_UART_SYSC_IDLE_MODE_SHIFT (3) -#define AMDM37x_UART_SYSC_IDLE_MODE_FORCE (0x0) -#define AMDM37x_UART_SYSC_IDLE_MODE_NO (0x1) -#define AMDM37x_UART_SYSC_IDLE_MODE_SMART (0x2) - - /** System status register */ - const ioport32_t syss; -#define AMDM37x_UART_SYSS_RESETDONE_FLAG (1 << 0) - - /** Wake-up enable register */ - ioport32_t wer; -#define AMDM37x_UART_WER_CTS_ACTIVITY_FLAG (1 << 0) -#define AMDM37x_UART_WER_RI_ACTIVITY_FLAG (1 << 2) -#define AMDM37x_UART_WER_RX_ACTIVITY_FLAG (1 << 4) -#define AMDM37x_UART_WER_RHR_IRQ_FLAG (1 << 5) -#define AMDM37x_UART_WER_RLS_IRQ_FLAG (1 << 6) -#define AMDM37x_UART_WER_TX_WAKEUP_EN_FLAG (1 << 7) - - /** Carrier frequency prescaler */ - ioport32_t cfps; /* UART3 specific */ -#define AMDM37x_UART_CFPS_MASK (0xff) - - /** Number of bytes in RX fifo */ - const ioport32_t rx_fifo_lvl; -#define AMDM37x_UART_RX_FIFO_LVL_MASK (0xff) - - /** Number of bytes in TX fifo */ - const ioport32_t tx_fifo_lvl; -#define AMDM37x_UART_TX_FIFO_LVL_MASK (0xff) - - /** RX/TX empty interrupts */ - ioport32_t ier2; -#define AMDM37x_UART_IER2_RX_FIFO_EMPTY_IRQ_EN_FLAG (1 << 0) -#define AMDM37x_UART_IER2_TX_FIFO_EMPTY_IRQ_EN_FLAG (1 << 1) - - /** RX/TX empty status */ - ioport32_t isr2; -#define AMDM37x_UART_ISR2_RX_FIFO_EMPTY_FLAG (1 << 0) -#define AMDM37x_UART_ISR2_TX_FIFO_EMPTY_FLAG (1 << 1) - - uint32_t padd2_[3]; - - /** Mode definition register 3 */ - ioport32_t mdr3; -#define AMDM37x_UART_MDR3_DIS_CIR_RX_DEMOD_FLAG (1 << 0) -} amdm37x_uart_regs_t; - -#endif - -/** - * @} - */ Index: kernel/genarch/include/genarch/drivers/omap/uart.h =================================================================== --- kernel/genarch/include/genarch/drivers/omap/uart.h (revision eef14771b77663fec606dbe440c7f1f7cb1f78be) +++ kernel/genarch/include/genarch/drivers/omap/uart.h (revision eef14771b77663fec606dbe440c7f1f7cb1f78be) @@ -0,0 +1,58 @@ +/* + * Copyright (c) Maurizio Lombardi + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** @addtogroup genarch + * @{ + */ +/** + * @file + * @brief Texas Instruments OMAP UART driver. + */ + +#ifndef _KERN_OMAP_UART_H_ +#define _KERN_OMAP_UART_H_ + +#include "uart_regs.h" + +typedef struct { + omap_uart_regs_t *regs; + indev_t *indev; + outdev_t outdev; + irq_t irq; +} omap_uart_t; + +extern bool omap_uart_init(omap_uart_t *uart, inr_t interrupt, + uintptr_t addr, size_t size); + +extern void omap_uart_input_wire(omap_uart_t *uart, indev_t *indev); + +#endif + +/** + * @} + */ + Index: kernel/genarch/include/genarch/drivers/omap/uart_regs.h =================================================================== --- kernel/genarch/include/genarch/drivers/omap/uart_regs.h (revision eef14771b77663fec606dbe440c7f1f7cb1f78be) +++ kernel/genarch/include/genarch/drivers/omap/uart_regs.h (revision eef14771b77663fec606dbe440c7f1f7cb1f78be) @@ -0,0 +1,431 @@ +/* + * Copyright (c) 2012 Jan Vesely + * Copyright (c) 2012 Maurizio Lombardi + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** @addtogroup genarch + * @{ + */ +/** + * @file + * @brief Texas Instruments OMAP UART memory mapped registers. + */ + +#ifndef _KERN_OMAP_UART_REGS_H_ +#define _KERN_OMAP_UART_REGS_H_ + +#include +#include +#include + +typedef struct { + union { + /** Stores lower part of the 14-bit baud divisor */ + ioport32_t dll; +#define OMAP_UART_DLL_MASK (0xff) + + /** Receive holding register */ + const ioport32_t rhr; +#define OMAP_UART_RHR_MASK (0xff) + + /** Transmit holding register */ + ioport32_t thr; +#define OMAP_UART_THR_MASK (0xff) + }; + + union { + /** Stores higher part of the 14-bit baud divisor */ + ioport32_t dlh; +#define OMAP_UART_DLH_MASK (0x1f) + + /** Interrupt enable registers */ + ioport32_t ier; +#define OMAP_UART_IER_RHR_IRQ_FLAG (1 << 0) +#define OMAP_UART_IER_THR_IRQ_FLAG (1 << 1) +#define OMAP_UART_IER_LINE_STS_IRQ_FLAG (1 << 2) +#define OMAP_UART_IER_MODEM_STS_IRQ_FLAG (1 << 3) +#define OMAP_UART_IER_SLEEP_MODE_FLAG (1 << 4) +#define OMAP_UART_IER_XOFF_IRQ_FLAG (1 << 5) +#define OMAP_UART_IER_RTS_IRQ_FLAG (1 << 6) +#define OMAP_UART_IER_CTS_IRQ_FLAG (1 << 7) + +#define OMAP_CIR_IER_RHR_IRQ_FLAG (1 << 0) +#define OMAP_CIR_IER_THR_IRQ_FLAG (1 << 1) +#define OMAP_CIR_IER_RX_STOP_IRQ_FLAG (1 << 2) +#define OMAP_CIR_IER_RX_OVERRUN_IRQ_FLAG (1 << 3) +#define OMAP_CIR_IER_TX_STS_IRQ_FLAG (1 << 5) + +#define OMAP_IRDA_IER_RHR_IRQ_FLAG (1 << 0) +#define OMAP_IRDA_IER_THR_IRQ_FLAG (1 << 1) +#define OMAP_IRDA_IER_LAST_RX_BYTE_IRQ_FLAG (1 << 2) +#define OMAP_IRDA_IER_RX_OVERRUN_IRQ_FLAG (1 << 3) +#define OMAP_IRDA_IER_STS_FIFO_TRIG_IRQ_FLAG (1 << 4) +#define OMAP_IRDA_IER_TX_STS_IRQ_FLAG (1 << 5) +#define OMAP_IRDA_IER_LINE_STS_IRQ_FLAG (1 << 6) +#define OMAP_IRDA_IER_EOF_IRQ_FLAG (1 << 7) + }; + + union { + /** Interrupt identification register */ + const ioport32_t iir; +#define OMAP_UART_IIR_IRQ_PENDING_FLAG (1 << 0) +#define OMAP_UART_IIR_TYPE_MASK (0x1f) +#define OMAP_UART_IIR_TYPE_SHIFT (1) +#define OMAP_UART_IIR_FCR_MASK (0x3) +#define OMAP_UART_IIR_FCR_SHIFT (6) + +#define OMAP_CIR_IIR_RHR_IRQ_FLAG (1 << 0) +#define OMAP_CIR_IIR_THR_IRQ_FLAG (1 << 1) +#define OMAP_CIR_IIR_RX_STOP_IRQ_FLAG (1 << 2) +#define OMAP_CIR_IIR_RX_OE_IRQ_FLAG (1 << 3) +#define OMAP_CIR_IIR_TX_STS_IRQ_FLAG (1 << 5) + +#define OMAP_IRDA_IIR_RHR_IRQ_FLAG (1 << 0) +#define OMAP_IRDA_IIR_THR_IRQ_FLAG (1 << 1) +#define OMAP_IRDA_IIR_RX_FIFO_LB_IRQ_FLAG (1 << 2) +#define OMAP_IRDA_IIR_RX_OE_IRQ_FLAG (1 << 3) +#define OMAP_IRDA_IIR_STS_FIFO_IRQ_FLAG (1 << 4) +#define OMAP_IRDA_IIR_TX_STS_IRQ_FLAG (1 << 5) +#define OMAP_IRDA_IIR_LINE_STS_IRQ_FLAG (1 << 6) +#define OMAP_IRDA_IIR_EOF_IRQ_FLAG (1 << 7) + + /** FIFO control register */ + ioport32_t fcr; +#define OMAP_UART_FCR_FIFO_EN_FLAG (1 << 0) +#define OMAP_UART_FCR_RX_FIFO_CLR_FLAG (1 << 1) +#define OMAP_UART_FCR_TX_FIFO_CLR_FLAG (1 << 3) +#define OMAP_UART_FCR_DMA_MODE_FLAG (1 << 4) + +#define OMAP_UART_FCR_TX_FIFO_TRIG_MASK (0x3) +#define OMAP_UART_FCR_TX_FIFO_TRIG_SHIFT (4) + +#define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3) +#define OMAP_UART_FCR_RX_FIFO_TRIG_SHIFT (6) + + /** Enhanced feature register */ + ioport32_t efr; +#define OMAP_UART_EFR_SW_FLOW_CTRL_RX_MASK (0x3) +#define OMAP_UART_EFR_SW_FLOW_CTRL_RX_SHIFT (0) +#define OMAP_UART_EFR_SW_FLOW_CTRL_TX_MASK (0x3) +#define OMAP_UART_EFR_SW_FLOW_CTRL_TX_SHIFT (2) + +#define OMAP_UART_EFR_SW_FLOW_CTRL_NONE (0x0) +#define OMAP_UART_EFR_SW_FLOW_CTRL_X2 (0x1) +#define OMAP_UART_EFR_SW_FLOW_CTRL_X1 (0x2) +#define OMAP_UART_EFR_SW_FLOW_CTRL_XBOTH (0x3) + +#define OMAP_UART_EFR_ENH_FLAG (1 << 4) +#define OMAP_UART_EFR_SPEC_CHAR_FLAG (1 << 5) +#define OMAP_UART_EFR_AUTO_RTS_EN_FLAG (1 << 6) +#define OMAP_UART_EFR_AUTO_CTS_EN_FLAG (1 << 7) + }; + + /** Line control register */ + ioport32_t lcr; +#define OMAP_UART_LCR_CHAR_LENGTH_MASK (0x3) +#define OMAP_UART_LCR_CHAR_LENGTH_SHIFT (0) +#define OMAP_UART_LCR_CHAR_LENGTH_5BITS (0x0) +#define OMAP_UART_LCR_CHAR_LENGTH_6BITS (0x1) +#define OMAP_UART_LCR_CHAR_LENGTH_7BITS (0x2) +#define OMAP_UART_LCR_CHAR_LENGTH_8BITS (0x3) +#define OMAP_UART_LCR_NB_STOP_FLAG (1 << 2) +#define OMAP_UART_LCR_PARITY_EN_FLAG (1 << 3) +#define OMAP_UART_LCR_PARITY_TYPE1_FLAG (1 << 4) +#define OMAP_UART_LCR_PARITY_TYPE2_FLAG (1 << 5) +#define OMAP_UART_LCR_BREAK_EN_FLAG (1 << 6) +#define OMAP_UART_LCR_DIV_EN_FLAG (1 << 7) + + + union { + /** Modem control register */ + ioport32_t mcr; +#define OMAP_UART_MCR_DTR_FLAG (1 << 0) +#define OMAP_UART_MCR_RTS_FLAG (1 << 1) +#define OMAP_UART_MCR_RI_STS_CH_FLAG (1 << 2) +#define OMAP_UART_MCR_CD_STS_CH_FLAG (1 << 3) +#define OMAP_UART_MCR_LOOPBACK_EN_FLAG (1 << 4) +#define OMAP_UART_MCR_XON_EN_FLAG (1 << 5) +#define OMAP_UART_MCR_TCR_TLR_FLAG (1 << 6) + + /** UART: XON1 char, IRDA: ADDR1 address */ + ioport32_t xon1_addr1; +#define OMAP_UART_XON1_ADDR1_MASK (0xff) + }; + + union { + /** Line status register */ + const ioport32_t lsr; +#define OMAP_UART_LSR_RX_FIFO_E_FLAG (1 << 0) +#define OMAP_UART_LSR_RX_OE_FLAG (1 << 1) +#define OMAP_UART_LSR_RX_PE_FLAG (1 << 2) +#define OMAP_UART_LSR_RX_FE_FLAG (1 << 3) +#define OMAP_UART_LSR_RX_BI_FLAG (1 << 4) +#define OMAP_UART_LSR_TX_FIFO_E_FLAG (1 << 5) +#define OMAP_UART_LSR_TX_SR_E_FLAG (1 << 6) +#define OMAP_UART_LSR_RX_FIFO_STS_FLAG (1 << 7) + +#define OMAP_CIR_LSR_RX_FIFO_E_FLAG (1 << 0) +#define OMAP_CIR_LSR_RX_STOP_FLAG (1 << 5) +#define OMAP_CIR_LSR_THR_EMPTY_FLAG (1 << 7) + +#define OMAP_IRDA_LSR_RX_FIFO_E_FLAG (1 << 0) +#define OMAP_IRDA_LSR_STS_FIFO_E_FLAG (1 << 1) +#define OMAP_IRDA_LSR_CRC_FLAG (1 << 2) +#define OMAP_IRDA_LSR_ABORT_FLAG (1 << 3) +#define OMAP_IRDA_LSR_FTL_FLAG (1 << 4) +#define OMAP_IRDA_LSR_RX_LAST_FLAG (1 << 5) +#define OMAP_IRDA_LSR_STS_FIFO_FULL_FLAG (1 << 6) +#define OMAP_IRDA_LSR_THR_EMPTY_FLAG (1 << 7) + + /** UART: XON2 char, IRDA: ADDR2 address */ + ioport32_t xon2_addr2; + }; + + union { + /** Modem status register */ + const ioport32_t msr; +#define OMAP_UART_MSR_CTS_STS_FLAG (1 << 0) +#define OMAP_UART_MSR_DSR_STS_FLAG (1 << 1) +#define OMAP_UART_MSR_RI_STS_FLAG (1 << 2) +#define OMAP_UART_MSR_DCD_STS_FLAG (1 << 3) +#define OMAP_UART_MSR_NCTS_STS_FLAG (1 << 4) +#define OMAP_UART_MSR_NDSR_STS_FLAG (1 << 5) +#define OMAP_UART_MSR_NRI_STS_FLAG (1 << 6) +#define OMAP_UART_MSR_NCD_STS_FLAG (1 << 7) + + /** Transmission control register */ + ioport32_t tcr; +#define OMAP_UART_TCR_FIFO_TRIG_MASK (0xf) +#define OMAP_UART_TCR_FIFO_TRIG_HALT_SHIFT (0) +#define OMAP_UART_TCR_FIFO_TRIG_START_SHIFT (4) + + /** UART: XOFF1 char */ + ioport32_t xoff1; +#define OMAP_UART_XOFF1_MASK (0xff) + }; + + union { + /* Scratchpad register, does nothing */ + ioport32_t spr; +#define OMAP_UART_SPR_MASK (0xff) + + /* Trigger level register */ + ioport32_t tlr; +#define OMAP_UART_TLR_LEVEL_MASK (0xf) +#define OMAP_UART_TLR_TX_FIFO_TRIG_SHIFT (0) +#define OMAP_UART_TLR_RX_FIFO_TRIG_SHIFT (4) + + /** UART: XOFF2 char */ + ioport32_t xoff2; +#define OMAP_UART_XOFF2_MASK (0xff) + }; + + /** Mode definition register. */ + ioport32_t mdr1; +#define OMAP_UART_MDR_MS_MASK (0x7) +#define OMAP_UART_MDR_MS_SHIFT (0) +#define OMAP_UART_MDR_MS_UART16 (0x0) +#define OMAP_UART_MDR_MS_SIR (0x1) +#define OMAP_UART_MDR_MS_UART16_AUTO (0x2) +#define OMAP_UART_MDR_MS_UART13 (0x3) +#define OMAP_UART_MDR_MS_MIR (0x4) +#define OMAP_UART_MDR_MS_FIR (0x5) +#define OMAP_UART_MDR_MS_CIR (0x6) +#define OMAP_UART_MDR_MS_DISABLE (0x7) + +#define OMAP_UART_MDR_IR_SLEEP_FLAG (1 << 3) +#define OMAP_UART_MDR_SET_TXIR_FLAG (1 << 4) +#define OMAP_UART_MDR_SCT_FLAG (1 << 5) +#define OMAP_UART_MDR_SIP_FLAG (1 << 6) +#define OMAP_UART_MDR_FRAME_END_MODE_FLAG (1 << 7) + + /** Mode definition register */ + ioport32_t mdr2; +#define OMAP_UART_MDR_IRTX_UNDERRUN_FLAG (1 << 0) +#define OMAP_UART_MDR_STS_FIFO_TRIG_MASK (0x3) +#define OMAP_UART_MDR_STS_FIFO_TRIG_SHIFT (1) +#define OMAP_UART_MDR_PULSE_SHAPING_FLAG (1 << 3) +#define OMAP_UART_MDR_CIR_PULSE_MODE_MASK (0x3) +#define OMAP_UART_MDR_CIR_PULSE_MODE_SHIFT (4) +#define OMAP_UART_MDR_IRRXINVERT_FLAG (1 << 6) + + union { + /** Status FIFO line status register (IrDA only) */ + const ioport32_t sflsr; +#define OMAP_IRDA_SFLSR_CRC_ERROR_FLAG (1 << 1) +#define OMAP_IRDA_SFLSR_ABORT_FLAG (1 << 2) +#define OMAP_IRDA_SFLSR_FTL_FLAG (1 << 3) +#define OMAP_IRDA_SFLSR_OE_FLAG (1 << 4) + + /** Transmit frame length low (IrDA only) */ + ioport32_t txfll; +#define OMAP_UART_TXFLL_MASK (0xff) + }; + + union { + /** Dummy register to restart TX or RX (IrDA only) */ + const ioport32_t resume; + /** Transmit frame length high (IrDA only) */ + ioport32_t txflh; +#define OMAP_UART_TXFLH_MASK (0xff) + }; + + union { + /** Status FIFO register low (IrDA only) */ + const ioport32_t sfregl; +#define OMAP_UART_SFREGL_MASK (0xff) + /** Received frame length low (IrDA only) */ + ioport32_t rxfll; +#define OMAP_UART_RXFLL_MASK (0xff) + }; + + union { + /** Status FIFO register high (IrDA only) */ + const ioport32_t sfregh; +#define OMAP_UART_SFREGH_MASK (0xf) + /** Received frame length high (IrDA only) */ + ioport32_t rxflh; +#define OMAP_UART_RXFLH_MASK (0xf) + }; + + union { + /** UART autobauding status register */ + const ioport32_t uasr; +#define OMAP_UART_UASR_SPEED_MASK (0x1f) +#define OMAP_UART_UASR_SPEED_SHIFT (0) +#define OMAP_UART_UASR_8BIT_CHAR_FLAG (1 << 5) +#define OMAP_UART_UASR_PARITY_MASK (0x3) +#define OMAP_UART_UASR_PARITY_SHIFT (6) + + /** BOF control register (IrDA only) */ + ioport32_t blr; +#define OMAP_IRDA_BLR_XBOF_TYPE_FLAG (1 << 6) +#define OMAP_IRDA_BLR_STS_FIFO_RESET (1 << 7) + }; + + /** Auxiliary control register (IrDA only) */ + ioport32_t acreg; +#define OMAP_IRDA_ACREG_EOT_EN_FLAG (1 << 0) +#define OMAP_IRDA_ACREG_ABORT_EN_FLAG (1 << 1) +#define OMAP_IRDA_ACREG_SCTX_EN_FLAG (1 << 2) +#define OMAP_IRDA_ACREG_SEND_SIP_FLAG (1 << 3) +#define OMAP_IRDA_ACREG_DIS_TX_UNDERRUN_FLAG (1 << 4) +#define OMAP_IRDA_ACREG_DIS_IR_RX_FLAG (1 << 5) +#define OMAP_IRDA_ACREG_SD_MOD_FLAG (1 << 6) +#define OMAP_IRDA_ACREG_PULSE_TYPE_FLAG (1 << 7) + + /** Supplementary control register */ + ioport32_t scr; +#define OMAP_UART_SCR_DMA_MODE_CTL_FLAG (1 << 0) +#define OMAP_UART_SCR_DMA_MODE_MASK (0x3) +#define OMAP_UART_SCR_DMA_MODE_SHIFT (1) +#define OMAP_UART_SCR_TX_EMPTY_CTL_IRQ_FLAG (1 << 3) +#define OMAP_UART_SCR_RX_CTS_WU_EN_FLAG (1 << 4) +#define OMAP_UART_SCR_TX_TRIG_GRANU1_FLAG (1 << 6) +#define OMAP_UART_SCR_RX_TRIG_GRANU1_FLAG (1 << 7) + + /** Supplementary status register */ + const ioport32_t ssr; +#define OMAP_UART_SSR_TX_FIFO_FULL_FLAG (1 << 0) +#define OMAP_UART_SSR_RX_CTS_WU_STS_FLAG (1 << 1) +#define OMAP_UART_SSR_DMA_COUNTER_RESET_FLAG (1 << 2) + + /** BOF Length register (IrDA only)*/ + ioport32_t eblr; +#define OMAP_IRDA_EBLR_DISABLED (0x00) +#define OMAP_IRDA_EBLR_RX_STOP_BITS(bits) (bits & 0xff) + + uint32_t padd0_; + + /** Module version register */ + const ioport32_t mvr; +#define OMAP_UART_MVR_MINOR_MASK (0xf) +#define OMAP_UART_MVR_MINOR_SHIFT (0) +#define OMAP_UART_MVR_MAJOR_MASK (0xf) +#define OMAP_UART_MVR_MAJOR_SHIFT (4) + + /** System configuration register */ + ioport32_t sysc; +#define OMAP_UART_SYSC_AUTOIDLE_FLAG (1 << 0) +#define OMAP_UART_SYSC_SOFTRESET_FLAG (1 << 1) +#define OMAP_UART_SYSC_ENWAKEUP_FLAG (1 << 2) +#define OMAP_UART_SYSC_IDLE_MODE_MASK (0x3) +#define OMAP_UART_SYSC_IDLE_MODE_SHIFT (3) +#define OMAP_UART_SYSC_IDLE_MODE_FORCE (0x0) +#define OMAP_UART_SYSC_IDLE_MODE_NO (0x1) +#define OMAP_UART_SYSC_IDLE_MODE_SMART (0x2) + + /** System status register */ + const ioport32_t syss; +#define OMAP_UART_SYSS_RESETDONE_FLAG (1 << 0) + + /** Wake-up enable register */ + ioport32_t wer; +#define OMAP_UART_WER_CTS_ACTIVITY_FLAG (1 << 0) +#define OMAP_UART_WER_RI_ACTIVITY_FLAG (1 << 2) +#define OMAP_UART_WER_RX_ACTIVITY_FLAG (1 << 4) +#define OMAP_UART_WER_RHR_IRQ_FLAG (1 << 5) +#define OMAP_UART_WER_RLS_IRQ_FLAG (1 << 6) +#define OMAP_UART_WER_TX_WAKEUP_EN_FLAG (1 << 7) + + /** Carrier frequency prescaler */ + ioport32_t cfps; +#define OMAP_UART_CFPS_MASK (0xff) + + /** Number of bytes in RX fifo */ + const ioport32_t rx_fifo_lvl; +#define OMAP_UART_RX_FIFO_LVL_MASK (0xff) + + /** Number of bytes in TX fifo */ + const ioport32_t tx_fifo_lvl; +#define OMAP_UART_TX_FIFO_LVL_MASK (0xff) + + /** RX/TX empty interrupts */ + ioport32_t ier2; +#define OMAP_UART_IER2_RX_FIFO_EMPTY_IRQ_EN_FLAG (1 << 0) +#define OMAP_UART_IER2_TX_FIFO_EMPTY_IRQ_EN_FLAG (1 << 1) + + /** RX/TX empty status */ + ioport32_t isr2; +#define OMAP_UART_ISR2_RX_FIFO_EMPTY_FLAG (1 << 0) +#define OMAP_UART_ISR2_TX_FIFO_EMPTY_FLAG (1 << 1) + + /** Set the sample per bit if non default frequency is used */ + ioport32_t freq_sel; +#define OMAP_UART_FREQ_SEL_MASK (0x000000FF) + + uint32_t padd2_[2]; + + /** Mode definition register 3 */ + ioport32_t mdr3; +#define OMAP_UART_MDR3_DIS_CIR_RX_DEMOD_FLAG (1 << 0) +} omap_uart_regs_t; + +#endif + +/** + * @} + */ Index: rnel/genarch/src/drivers/am335x/uart.c =================================================================== --- kernel/genarch/src/drivers/am335x/uart.c (revision 716357ff5db66f096f15e81dc5b3aa611c7a9ff0) +++ (revision ) @@ -1,183 +1,0 @@ -/* - * Copyright (c) 2012 Jan Vesely - * Copyright (c) 2013 Maurizio Lombardi - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** @addtogroup genarch - * @{ - */ -/** - * @file - * @brief Texas Instruments AM335x on-chip uart serial line driver. - */ - -#include -#include -#include -#include - -static void am335x_uart_txb(am335x_uart_t *uart, uint8_t b) -{ - /* Wait for buffer */ - while (uart->regs->ssr & AM335x_UART_SSR_TX_FIFO_FULL_FLAG); - /* Write to the outgoing fifo */ - uart->regs->thr = b; -} - -static void am335x_uart_putchar(outdev_t *dev, wchar_t ch) -{ - am335x_uart_t *uart = dev->data; - if (!ascii_check(ch)) { - am335x_uart_txb(uart, U_SPECIAL); - } else { - if (ch == '\n') - am335x_uart_txb(uart, '\r'); - am335x_uart_txb(uart, ch); - } -} - -static outdev_operations_t am335x_uart_ops = { - .redraw = NULL, - .write = am335x_uart_putchar, -}; - -static irq_ownership_t am335x_uart_claim(irq_t *irq) -{ - return IRQ_ACCEPT; -} - -static void am335x_uart_handler(irq_t *irq) -{ - am335x_uart_t *uart = irq->instance; - while ((uart->regs->rx_fifo_lvl)) { - const uint8_t val = uart->regs->rhr; - if (uart->indev && val) { - indev_push_character(uart->indev, val); - } - } -} - -bool am335x_uart_init( - am335x_uart_t *uart, inr_t interrupt, uintptr_t addr, size_t size) -{ - ASSERT(uart); - uart->regs = (void *)km_map(addr, size, PAGE_NOT_CACHEABLE); - - ASSERT(uart->regs); - - /* Soft reset the port */ - uart->regs->sysc = AM335x_UART_SYSC_SOFTRESET_FLAG; - while (!(uart->regs->syss & AM335x_UART_SYSS_RESETDONE_FLAG)); - - /* Disable the UART module */ - uart->regs->mdr1 |= AM335x_UART_MDR_MS_DISABLE; - - /* Enable access to EFR register */ - uart->regs->lcr = 0xbf; /* Sets config mode B */ - - /* Enable access to TCL_TLR register */ - const bool enhanced = uart->regs->efr & AM335x_UART_EFR_ENH_FLAG; - uart->regs->efr |= AM335x_UART_EFR_ENH_FLAG; /* Turn on enh. */ - uart->regs->lcr = 0x80; /* Config mode A */ - - /* Set default (val 0) triggers, disable DMA enable FIFOs */ - const bool tcl_tlr = uart->regs->mcr & AM335x_UART_MCR_TCR_TLR_FLAG; - /* Enable access to tcr and tlr registers */ - uart->regs->mcr |= AM335x_UART_MCR_TCR_TLR_FLAG; - - /* Enable FIFOs */ - uart->regs->fcr = AM335x_UART_FCR_FIFO_EN_FLAG; - - /* Enable fine granularity for RX FIFO and set trigger level to 1, - * TX FIFO, trigger level is irrelevant*/ - uart->regs->lcr = 0xBF; /* Sets config mode B */ - uart->regs->scr = AM335x_UART_SCR_RX_TRIG_GRANU1_FLAG; - uart->regs->tlr = 1 << AM335x_UART_TLR_RX_FIFO_TRIG_SHIFT; - - /* Sets config mode A */ - uart->regs->lcr = 0x80; - /* Restore tcl_tlr access flag */ - if (!tcl_tlr) - uart->regs->mcr &= ~AM335x_UART_MCR_TCR_TLR_FLAG; - /* Sets config mode B */ - uart->regs->lcr = 0xBF; - - /* Set the divisor value to get a baud rate of 115200 bps */ - uart->regs->dll = 0x1A; - uart->regs->dlh = 0x00; - - /* Restore enhanced */ - if (!enhanced) - uart->regs->efr &= ~AM335x_UART_EFR_ENH_FLAG; - - /* Set the DIV_EN bit to 0 */ - uart->regs->lcr &= ~AM335x_UART_LCR_DIV_EN_FLAG; - /* Set the BREAK_EN bit to 0 */ - uart->regs->lcr &= ~AM335x_UART_LCR_BREAK_EN_FLAG; - /* No parity */ - uart->regs->lcr &= ~AM335x_UART_LCR_PARITY_EN_FLAG; - /* Stop = 1 bit */ - uart->regs->lcr &= ~AM335x_UART_LCR_NB_STOP_FLAG; - /* Char length = 8 bits */ - uart->regs->lcr |= AM335x_UART_LCR_CHAR_LENGTH_8BITS; - - /* Enable the UART module */ - uart->regs->mdr1 &= (AM335x_UART_MDR_MS_UART16 & - ~AM335x_UART_MDR_MS_MASK); - - /* Disable interrupts */ - uart->regs->ier = 0; - - /* Setup outdev */ - outdev_initialize("am335x_uart_dev", &uart->outdev, &am335x_uart_ops); - uart->outdev.data = uart; - - /* Initialize IRQ */ - irq_initialize(&uart->irq); - uart->irq.devno = device_assign_devno(); - uart->irq.inr = interrupt; - uart->irq.claim = am335x_uart_claim; - uart->irq.handler = am335x_uart_handler; - uart->irq.instance = uart; - - return true; -} - -void am335x_uart_input_wire(am335x_uart_t *uart, indev_t *indev) -{ - ASSERT(uart); - /* Set indev */ - uart->indev = indev; - /* Register interrupt. */ - irq_register(&uart->irq); - /* Enable interrupt on receive */ - uart->regs->ier |= AM335x_UART_IER_RHR_IRQ_FLAG; -} - -/** - * @} - */ - Index: rnel/genarch/src/drivers/amdm37x/uart.c =================================================================== --- kernel/genarch/src/drivers/amdm37x/uart.c (revision 716357ff5db66f096f15e81dc5b3aa611c7a9ff0) +++ (revision ) @@ -1,163 +1,0 @@ -/* - * Copyright (c) 2012 Jan Vesely - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** @addtogroup genarch - * @{ - */ -/** - * @file - * @brief Texas Instruments AMDM37x on-chip uart serial line driver. - */ - -#include -#include -#include -#include - -static void amdm37x_uart_txb(amdm37x_uart_t *uart, uint8_t b) -{ - /* Wait for buffer */ - while (uart->regs->ssr & AMDM37x_UART_SSR_TX_FIFO_FULL_FLAG); - /* Write to the outgoing fifo */ - uart->regs->thr = b; -} - -static void amdm37x_uart_putchar(outdev_t *dev, wchar_t ch) -{ - amdm37x_uart_t *uart = dev->data; - if (!ascii_check(ch)) { - amdm37x_uart_txb(uart, U_SPECIAL); - } else { - if (ch == '\n') - amdm37x_uart_txb(uart, '\r'); - amdm37x_uart_txb(uart, ch); - } -} - -static outdev_operations_t amdm37x_uart_ops = { - .redraw = NULL, - .write = amdm37x_uart_putchar, -}; - -static irq_ownership_t amdm37x_uart_claim(irq_t *irq) -{ - return IRQ_ACCEPT; -} - -static void amdm37x_uart_handler(irq_t *irq) -{ - amdm37x_uart_t *uart = irq->instance; - while ((uart->regs->rx_fifo_lvl)) { - const uint8_t val = uart->regs->rhr; - if (uart->indev && val) { - indev_push_character(uart->indev, val); - } - } -} - -bool amdm37x_uart_init( - amdm37x_uart_t *uart, inr_t interrupt, uintptr_t addr, size_t size) -{ - ASSERT(uart); - uart->regs = (void *)km_map(addr, size, PAGE_NOT_CACHEABLE); - - ASSERT(uart->regs); - - /* See TI OMAP35X TRM ch 17.5.1.1 p. 2732 for startup routine */ -#if 0 - /* Soft reset the port */ - uart->regs->sysc = AMDM37x_UART_SYSC_SOFTRESET_FLAG; - while (!(uart->regs->syss & AMDM37x_UART_SYSS_RESETDONE_FLAG)) ; -#endif - - /* Enable access to EFR register */ - const uint8_t lcr = uart->regs->lcr; /* Save old value */ - uart->regs->lcr = 0xbf; /* Sets config mode B */ - - /* Enable access to TCL_TLR register */ - const bool enhanced = uart->regs->efr & AMDM37x_UART_EFR_ENH_FLAG; - uart->regs->efr |= AMDM37x_UART_EFR_ENH_FLAG; /* Turn on enh. */ - uart->regs->lcr = 0x80; /* Config mode A */ - - /* Set default (val 0) triggers, disable DMA enable FIFOs */ - const bool tcl_tlr = uart->regs->mcr & AMDM37x_UART_MCR_TCR_TLR_FLAG; - /* Enable access to tcr and tlr registers */ - uart->regs->mcr |= AMDM37x_UART_MCR_TCR_TLR_FLAG; - - /* Enable FIFOs */ - uart->regs->fcr = AMDM37x_UART_FCR_FIFO_EN_FLAG; - - /* Eneble fine granularity for RX FIFO and set trigger level to 1, - * TX FIFO, trigger level is irelevant*/ - uart->regs->lcr = 0xbf; /* Sets config mode B */ - uart->regs->scr = AMDM37x_UART_SCR_RX_TRIG_GRANU1_FLAG; - uart->regs->tlr = 1 << AMDM37x_UART_TLR_RX_FIFO_TRIG_SHIFT; - - /* Restore enhanced */ - if (!enhanced) - uart->regs->efr &= ~AMDM37x_UART_EFR_ENH_FLAG; - - uart->regs->lcr = 0x80; /* Config mode A */ - /* Restore tcl_lcr access flag*/ - if (!tcl_tlr) - uart->regs->mcr &= ~AMDM37x_UART_MCR_TCR_TLR_FLAG; - - /* Restore lcr */ - uart->regs->lcr = lcr; - - /* Disable interrupts */ - uart->regs->ier = 0; - - /* Setup outdev */ - outdev_initialize("amdm37x_uart_dev", &uart->outdev, &amdm37x_uart_ops); - uart->outdev.data = uart; - - /* Initialize IRQ */ - irq_initialize(&uart->irq); - uart->irq.devno = device_assign_devno(); - uart->irq.inr = interrupt; - uart->irq.claim = amdm37x_uart_claim; - uart->irq.handler = amdm37x_uart_handler; - uart->irq.instance = uart; - - return true; -} - -void amdm37x_uart_input_wire(amdm37x_uart_t *uart, indev_t *indev) -{ - ASSERT(uart); - /* Set indev */ - uart->indev = indev; - /* Register interrupt. */ - irq_register(&uart->irq); - /* Enable interrupt on receive */ - uart->regs->ier |= AMDM37x_UART_IER_RHR_IRQ_FLAG; -} - -/** - * @} - */ Index: kernel/genarch/src/drivers/omap/uart.c =================================================================== --- kernel/genarch/src/drivers/omap/uart.c (revision eef14771b77663fec606dbe440c7f1f7cb1f78be) +++ kernel/genarch/src/drivers/omap/uart.c (revision eef14771b77663fec606dbe440c7f1f7cb1f78be) @@ -0,0 +1,183 @@ +/* + * Copyright (c) 2012 Jan Vesely + * Copyright (c) 2013 Maurizio Lombardi + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** @addtogroup genarch + * @{ + */ +/** + * @file + * @brief Texas Instruments OMAP on-chip uart serial line driver. + */ + +#include +#include +#include +#include + +static void omap_uart_txb(omap_uart_t *uart, uint8_t b) +{ + /* Wait for buffer */ + while (uart->regs->ssr & OMAP_UART_SSR_TX_FIFO_FULL_FLAG); + /* Write to the outgoing fifo */ + uart->regs->thr = b; +} + +static void omap_uart_putchar(outdev_t *dev, wchar_t ch) +{ + omap_uart_t *uart = dev->data; + if (!ascii_check(ch)) { + omap_uart_txb(uart, U_SPECIAL); + } else { + if (ch == '\n') + omap_uart_txb(uart, '\r'); + omap_uart_txb(uart, ch); + } +} + +static outdev_operations_t omap_uart_ops = { + .redraw = NULL, + .write = omap_uart_putchar, +}; + +static irq_ownership_t omap_uart_claim(irq_t *irq) +{ + return IRQ_ACCEPT; +} + +static void omap_uart_handler(irq_t *irq) +{ + omap_uart_t *uart = irq->instance; + while ((uart->regs->rx_fifo_lvl)) { + const uint8_t val = uart->regs->rhr; + if (uart->indev && val) { + indev_push_character(uart->indev, val); + } + } +} + +bool omap_uart_init( + omap_uart_t *uart, inr_t interrupt, uintptr_t addr, size_t size) +{ + ASSERT(uart); + uart->regs = (void *)km_map(addr, size, PAGE_NOT_CACHEABLE); + + ASSERT(uart->regs); + + /* Soft reset the port */ + uart->regs->sysc = OMAP_UART_SYSC_SOFTRESET_FLAG; + while (!(uart->regs->syss & OMAP_UART_SYSS_RESETDONE_FLAG)); + + /* Disable the UART module */ + uart->regs->mdr1 |= OMAP_UART_MDR_MS_DISABLE; + + /* Enable access to EFR register */ + uart->regs->lcr = 0xbf; /* Sets config mode B */ + + /* Enable access to TCL_TLR register */ + const bool enhanced = uart->regs->efr & OMAP_UART_EFR_ENH_FLAG; + uart->regs->efr |= OMAP_UART_EFR_ENH_FLAG; /* Turn on enh. */ + uart->regs->lcr = 0x80; /* Config mode A */ + + /* Set default (val 0) triggers, disable DMA enable FIFOs */ + const bool tcl_tlr = uart->regs->mcr & OMAP_UART_MCR_TCR_TLR_FLAG; + /* Enable access to tcr and tlr registers */ + uart->regs->mcr |= OMAP_UART_MCR_TCR_TLR_FLAG; + + /* Enable FIFOs */ + uart->regs->fcr = OMAP_UART_FCR_FIFO_EN_FLAG; + + /* Enable fine granularity for RX FIFO and set trigger level to 1, + * TX FIFO, trigger level is irrelevant*/ + uart->regs->lcr = 0xBF; /* Sets config mode B */ + uart->regs->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_FLAG; + uart->regs->tlr = 1 << OMAP_UART_TLR_RX_FIFO_TRIG_SHIFT; + + /* Sets config mode A */ + uart->regs->lcr = 0x80; + /* Restore tcl_tlr access flag */ + if (!tcl_tlr) + uart->regs->mcr &= ~OMAP_UART_MCR_TCR_TLR_FLAG; + /* Sets config mode B */ + uart->regs->lcr = 0xBF; + + /* Set the divisor value to get a baud rate of 115200 bps */ + uart->regs->dll = 0x1A; + uart->regs->dlh = 0x00; + + /* Restore enhanced */ + if (!enhanced) + uart->regs->efr &= ~OMAP_UART_EFR_ENH_FLAG; + + /* Set the DIV_EN bit to 0 */ + uart->regs->lcr &= ~OMAP_UART_LCR_DIV_EN_FLAG; + /* Set the BREAK_EN bit to 0 */ + uart->regs->lcr &= ~OMAP_UART_LCR_BREAK_EN_FLAG; + /* No parity */ + uart->regs->lcr &= ~OMAP_UART_LCR_PARITY_EN_FLAG; + /* Stop = 1 bit */ + uart->regs->lcr &= ~OMAP_UART_LCR_NB_STOP_FLAG; + /* Char length = 8 bits */ + uart->regs->lcr |= OMAP_UART_LCR_CHAR_LENGTH_8BITS; + + /* Enable the UART module */ + uart->regs->mdr1 &= (OMAP_UART_MDR_MS_UART16 & + ~OMAP_UART_MDR_MS_MASK); + + /* Disable interrupts */ + uart->regs->ier = 0; + + /* Setup outdev */ + outdev_initialize("omap_uart_dev", &uart->outdev, &omap_uart_ops); + uart->outdev.data = uart; + + /* Initialize IRQ */ + irq_initialize(&uart->irq); + uart->irq.devno = device_assign_devno(); + uart->irq.inr = interrupt; + uart->irq.claim = omap_uart_claim; + uart->irq.handler = omap_uart_handler; + uart->irq.instance = uart; + + return true; +} + +void omap_uart_input_wire(omap_uart_t *uart, indev_t *indev) +{ + ASSERT(uart); + /* Set indev */ + uart->indev = indev; + /* Register interrupt. */ + irq_register(&uart->irq); + /* Enable interrupt on receive */ + uart->regs->ier |= OMAP_UART_IER_RHR_IRQ_FLAG; +} + +/** + * @} + */ +