Index: kernel/arch/ppc32/include/asm.h
===================================================================
--- kernel/arch/ppc32/include/asm.h	(revision 31198c1215c4e4a979a6f8e80df9c8c170c13886)
+++ kernel/arch/ppc32/include/asm.h	(revision ecbd287d08e56d5b82b3cf4a9278f19f638af5c9)
@@ -38,4 +38,25 @@
 #include <typedefs.h>
 #include <config.h>
+#include <arch/cpu.h>
+
+static inline uint32_t msr_read(void)
+{
+	uint32_t msr;
+	
+	asm volatile (
+		"mfmsr %[msr]\n"
+		: [msr] "=r" (msr)
+	);
+	
+	return msr;
+}
+
+static inline void msr_write(uint32_t msr)
+{
+	asm volatile (
+		"mtmsr %[msr]\n"
+		:: [msr] "r" (msr)
+	);
+}
 
 /** Enable interrupts.
@@ -45,18 +66,11 @@
  *
  * @return Old interrupt priority level.
+ *
  */
 static inline ipl_t interrupts_enable(void)
 {
-	ipl_t v;
-	ipl_t tmp;
-	
-	asm volatile (
-		"mfmsr %0\n"
-		"mfmsr %1\n"
-		"ori %1, %1, 1 << 15\n"
-		"mtmsr %1\n"
-		: "=r" (v), "=r" (tmp)
-	);
-	return v;
+	ipl_t ipl = msr_read();
+	msr_write(ipl | MSR_EE);
+	return ipl;
 }
 
@@ -67,18 +81,11 @@
  *
  * @return Old interrupt priority level.
+ *
  */
 static inline ipl_t interrupts_disable(void)
 {
-	ipl_t v;
-	ipl_t tmp;
-	
-	asm volatile (
-		"mfmsr %0\n"
-		"mfmsr %1\n"
-		"rlwinm %1, %1, 0, 17, 15\n"
-		"mtmsr %1\n"
-		: "=r" (v), "=r" (tmp)
-	);
-	return v;
+	ipl_t ipl = msr_read();
+	msr_write(ipl & (~MSR_EE));
+	return ipl;
 }
 
@@ -88,20 +95,9 @@
  *
  * @param ipl Saved interrupt priority level.
+ *
  */
 static inline void interrupts_restore(ipl_t ipl)
 {
-	ipl_t tmp;
-	
-	asm volatile (
-		"mfmsr %1\n"
-		"rlwimi  %0, %1, 0, 17, 15\n"
-		"cmpw 0, %0, %1\n"
-		"beq 0f\n"
-		"mtmsr %0\n"
-		"0:\n"
-		: "=r" (ipl), "=r" (tmp)
-		: "0" (ipl)
-		: "cr0"
-	);
+	msr_write((msr_read() & (~MSR_EE)) | (ipl & MSR_EE));
 }
 
@@ -111,14 +107,19 @@
  *
  * @return Current interrupt priority level.
+ *
  */
 static inline ipl_t interrupts_read(void)
 {
-	ipl_t v;
-	
-	asm volatile (
-		"mfmsr %0\n"
-		: "=r" (v)
-	);
-	return v;
+	return msr_read();
+}
+
+/** Check whether interrupts are disabled.
+ *
+ * @return True if interrupts are disabled.
+ *
+ */
+static inline bool interrupts_disabled(void)
+{
+	return ((msr_read() & MSR_EE) == 0);
 }
 
@@ -128,15 +129,17 @@
  * The stack is assumed to be STACK_SIZE bytes long.
  * The stack must start on page boundary.
+ *
  */
 static inline uintptr_t get_stack_base(void)
 {
-	uintptr_t v;
+	uintptr_t base;
 	
 	asm volatile (
-		"and %0, %%sp, %1\n"
-		: "=r" (v)
-		: "r" (~(STACK_SIZE - 1))
+		"and %[base], %%sp, %[mask]\n"
+		: [base] "=r" (base)
+		: [mask] "r" (~(STACK_SIZE - 1))
 	);
-	return v;
+	
+	return base;
 }
 
Index: kernel/arch/ppc32/include/cpu.h
===================================================================
--- kernel/arch/ppc32/include/cpu.h	(revision 31198c1215c4e4a979a6f8e80df9c8c170c13886)
+++ kernel/arch/ppc32/include/cpu.h	(revision ecbd287d08e56d5b82b3cf4a9278f19f638af5c9)
@@ -36,11 +36,36 @@
 #define KERN_ppc32_CPU_H_
 
-#include <arch/asm.h>
+/* MSR bits */
+#define MSR_DR  (1 << 4)
+#define MSR_IR  (1 << 5)
+#define MSR_PR  (1 << 14)
+#define MSR_EE  (1 << 15)
+
+/* HID0 bits */
+#define HID0_STEN  (1 << 24)
+#define HID0_ICE   (1 << 15)
+#define HID0_DCE   (1 << 14)
+#define HID0_ICFI  (1 << 11)
+#define HID0_DCI   (1 << 10)
+
+#ifndef __ASM__
+
+#include <typedefs.h>
 
 typedef struct {
-	int version;
-	int revision;
-} cpu_arch_t;
-	
+	uint16_t version;
+	uint16_t revision;
+} __attribute__ ((packed)) cpu_arch_t;
+
+static inline void cpu_version(cpu_arch_t *info)
+{
+	asm volatile (
+		"mfpvr %[cpu_info]\n"
+		: [cpu_info] "=r" (*info)
+	);
+}
+
+#endif /* __ASM__ */
+
 #endif
 
Index: kernel/arch/ppc32/include/cpuid.h
===================================================================
--- kernel/arch/ppc32/include/cpuid.h	(revision 31198c1215c4e4a979a6f8e80df9c8c170c13886)
+++ 	(revision )
@@ -1,56 +1,0 @@
-/*
- * Copyright (c) 2006 Martin Decky
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * - Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in the
- *   documentation and/or other materials provided with the distribution.
- * - The name of the author may not be used to endorse or promote products
- *   derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/** @addtogroup ppc32
- * @{
- */
-/** @file
- */
-
-#ifndef KERN_ppc32_CPUID_H_
-#define KERN_ppc32_CPUID_H_
-
-#include <typedefs.h>
-
-typedef struct {
-	uint16_t version;
-	uint16_t revision;
-} __attribute__ ((packed)) cpu_info_t;
-
-static inline void cpu_version(cpu_info_t *info)
-{
-	asm volatile (
-		"mfpvr %0\n"
-		: "=r" (*info)
-	);
-}
-
-#endif
-
-/** @}
- */