Changeset ec08286 in mainline


Ignore:
Timestamp:
2010-07-25T14:35:05Z (14 years ago)
Author:
Jiri Svoboda <jiri@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
277cf60
Parents:
24697c3
Message:

Kernel input device for gta02 serial console. Move s3c24xx interrupt controller functionality into a separate C file.

Files:
1 added
6 edited

Legend:

Unmodified
Added
Removed

  • HelenOS.config

    r24697c3 rec08286  
    441441! [(CONFIG_HID_OUT=generic|CONFIG_HID_OUT=serial)&PLATFORM=arm32&MACHINE=gta02] CONFIG_S3C24XX_UART (y/n)
    442442
     443% Support for Samsung S3C24XX on-chip interrupt controller
     444! [PLATFORM=arm32&MACHINE=gta02] CONFIG_S3C24XX_IRQC (y)
     445
    443446% Support for Z8530 controller
    444447! [(CONFIG_HID_IN=generic|CONFIG_HID_IN=keyboard)&PLATFORM=sparc64&MACHINE=generic] CONFIG_Z8530 (y/n)
    … …  
    469472
    470473% Serial line input module
    471 ! [CONFIG_DSRLNIN=y|(PLATFORM=ia64&MACHINE=i460GX&CONFIG_NS16550=y)|(PLATFORM=ia64&MACHINE=ski)|(PLATFORM=sparc64&MACHINE=serengeti&CONFIG_SGCN_KBD=y)|(PLATFORM=sparc64&PROCESSOR=sun4v)] CONFIG_SRLN (y)
     474! [CONFIG_DSRLNIN=y|(PLATFORM=arm32&MACHINE=gta02)|(PLATFORM=ia64&MACHINE=i460GX&CONFIG_NS16550=y)|(PLATFORM=ia64&MACHINE=ski)|(PLATFORM=sparc64&MACHINE=serengeti&CONFIG_SGCN_KBD=y)|(PLATFORM=sparc64&PROCESSOR=sun4v)] CONFIG_SRLN (y)
    472475
    473476% EGA support

  • kernel/arch/arm32/src/mach/gta02/gta02.c

    r24697c3 rec08286  
    4343#include <genarch/drivers/s3c24xx_irqc/s3c24xx_irqc.h>
    4444#include <genarch/drivers/s3c24xx_timer/s3c24xx_timer.h>
     45#include <genarch/srln/srln.h>
    4546#include <interrupt.h>
    4647#include <ddi/ddi.h>
    … …  
    7576
    7677static void *gta02_scons_out;
    77 static s3c24xx_irqc_t *gta02_irqc;
     78static outdev_t *gta02_scons_dev;
     79static s3c24xx_irqc_t gta02_irqc;
    7880static s3c24xx_timer_t *gta02_timer;
    7981
    … …  
    9395static void gta02_init(void)
    9496{
     97        s3c24xx_irqc_regs_t *irqc_regs;
     98
    9599        gta02_scons_out = (void *) hw_map(GTA02_SCONS_BASE, PAGE_SIZE);
    96         gta02_irqc = (void *) hw_map(S3C24XX_IRQC_ADDRESS, PAGE_SIZE);
    97100        gta02_timer = (void *) hw_map(S3C24XX_TIMER_ADDRESS, PAGE_SIZE);
    98 
    99         /* Make all interrupt sources use IRQ mode (not FIQ). */
    100         pio_write_32(&gta02_irqc->intmod, 0x00000000);
    101 
    102         /* Disable all interrupt sources. */
    103         pio_write_32(&gta02_irqc->intmsk, 0xffffffff);
    104 
    105         /* Disable interrupts from all sub-sources. */
    106         pio_write_32(&gta02_irqc->intsubmsk, 0xffffffff);
     101        irqc_regs = (void *) hw_map(S3C24XX_IRQC_ADDRESS, PAGE_SIZE);
     102
     103        /* Initialize interrupt controller. */
     104        s3c24xx_irqc_init(&gta02_irqc, irqc_regs);
    107105}
    108106
    … …  
    132130        uint32_t inum;
    133131
    134         inum = pio_read_32(&gta02_irqc->intoffset);
     132        /* Determine IRQ number. */
     133        inum = s3c24xx_irqc_inum_get(&gta02_irqc);
     134
     135        /* Clear interrupt condition in the interrupt controller. */
     136        s3c24xx_irqc_clear(&gta02_irqc, inum);
    135137
    136138        irq_t *irq = irq_dispatch_and_lock(inum);
    … …  
    144146                    CPU->id, inum);
    145147        }
    146 
    147         /* Clear interrupt condition in the interrupt controller. */
    148         pio_write_32(&gta02_irqc->srcpnd, S3C24XX_INT_BIT(inum));
    149         pio_write_32(&gta02_irqc->intpnd, S3C24XX_INT_BIT(inum));
    150148}
    151149
    … …  
    176174        }
    177175#endif
    178         outdev_t *scons_dev;
    179 
    180         scons_dev = s3c24xx_uart_init((ioport8_t *) gta02_scons_out);
    181         if (scons_dev)
    182                 stdout_wire(scons_dev);
     176
     177        /* Initialize serial port of the debugging console. */
     178        gta02_scons_dev = s3c24xx_uart_init((ioport8_t *) gta02_scons_out,
     179                S3C24XX_INT_UART2);
     180        if (gta02_scons_dev) {
     181
     182                /* Create output device. */
     183                stdout_wire(gta02_scons_dev);
     184        }
    183185}
    184186
    185187static void gta02_input_init(void)
    186188{
     189        s3c24xx_uart_instance_t *scons_inst;
     190
     191        if (gta02_scons_dev) {
     192                /* Create input device. */
     193                scons_inst = (void *) gta02_scons_dev->data;
     194
     195                srln_instance_t *srln_instance = srln_init();
     196                if (srln_instance) {
     197                        indev_t *sink = stdin_wire();
     198                        indev_t *srln = srln_wire(srln_instance, sink);
     199                        s3c24xx_uart_input_wire(scons_inst, srln);
     200
     201                        /* Enable interrupts from UART2 */
     202                        s3c24xx_irqc_src_enable(&gta02_irqc,
     203                            S3C24XX_INT_UART2);
     204
     205                        /* Enable interrupts from UART2 RXD */
     206                        s3c24xx_irqc_subsrc_enable(&gta02_irqc,
     207                            S3C24XX_SUBINT_RXD2);
     208                }
     209        }
    187210}
    188211
    … …  
    248271
    249272        /* Enable interrupts from timer0 */
    250         pio_write_32(&gta02_irqc->intmsk, pio_read_32(&gta02_irqc->intmsk) &
    251             ~S3C24XX_INT_BIT(S3C24XX_INT_TIMER0));
     273        s3c24xx_irqc_src_enable(&gta02_irqc, S3C24XX_INT_TIMER0);
    252274
    253275        /* Load data from tcntb0/tcmpb0 into tcnt0/tcmp0. */

  • kernel/genarch/Makefile.inc

    r24697c3 rec08286  
    9090endif
    9191
     92ifeq ($(CONFIG_S3C24XX_IRQC),y)
     93        GENARCH_SOURCES += \
     94                genarch/src/drivers/s3c24xx_irqc/s3c24xx_irqc.c
     95endif
     96
    9297ifeq ($(CONFIG_S3C24XX_UART),y)
    9398        GENARCH_SOURCES += \

  • kernel/genarch/include/drivers/s3c24xx_irqc/s3c24xx_irqc.h

    r24697c3 rec08286  
    5353        ioport32_t subsrcpnd;   /**< Sub source pending */
    5454        ioport32_t intsubmsk;   /** Interrupt sub mask */
    55 } s3c24xx_irqc_t;
     55} s3c24xx_irqc_regs_t;
    5656
    5757/** S3C24xx Interrupt source numbers.
    … …  
    120120#define S3C24XX_SUBINT_BIT(subsource) (1 << (subsource))
    121121
     122typedef struct {
     123        s3c24xx_irqc_regs_t *regs;
     124} s3c24xx_irqc_t;
     125
     126extern void s3c24xx_irqc_init(s3c24xx_irqc_t *, s3c24xx_irqc_regs_t *);
     127extern unsigned s3c24xx_irqc_inum_get(s3c24xx_irqc_t *);
     128extern void s3c24xx_irqc_clear(s3c24xx_irqc_t *, unsigned);
     129extern void s3c24xx_irqc_src_enable(s3c24xx_irqc_t *, unsigned);
     130extern void s3c24xx_irqc_src_disable(s3c24xx_irqc_t *, unsigned);
     131extern void s3c24xx_irqc_subsrc_enable(s3c24xx_irqc_t *, unsigned);
     132extern void s3c24xx_irqc_subsrc_disable(s3c24xx_irqc_t *, unsigned);
     133
    122134#endif
    123135

  • kernel/genarch/include/drivers/s3c24xx_uart/s3c24xx_uart.h

    r24697c3 rec08286  
    3838#define KERN_S3C24XX_UART_H_
    3939
     40#include <ddi/irq.h>
     41#include <console/chardev.h>
    4042#include <typedefs.h>
    41 #include <console/chardev.h>
    4243
    43 extern outdev_t *s3c24xx_uart_init(ioport8_t *);
     44typedef struct {
     45        ioport8_t *base;
     46        indev_t *indev;
     47        irq_t irq;
     48} s3c24xx_uart_instance_t;
     49
     50extern outdev_t *s3c24xx_uart_init(ioport8_t *, inr_t inr);
     51extern void s3c24xx_uart_input_wire(s3c24xx_uart_instance_t *,
     52    indev_t *);
    4453
    4554#endif

  • kernel/genarch/src/drivers/s3c24xx_uart/s3c24xx_uart.c

    r24697c3 rec08286  
    4040#include <genarch/drivers/s3c24xx_uart/s3c24xx_uart.h>
    4141#include <console/chardev.h>
     42#include <console/console.h>
     43#include <ddi/device.h>
    4244#include <arch/asm.h>
    4345#include <mm/slab.h>
    44 #include <console/console.h>
    4546#include <sysinfo/sysinfo.h>
    4647#include <str.h>
    4748
    4849/** S3C24xx UART register offsets */
    49 #define S3C24XX_UTRSTAT         0x10
    50 #define S3C24XX_UTXH            0x20
     50#define S3C24XX_ULCON                   0x00
     51#define S3C24XX_UCON                    0x04
     52#define S3C24XX_UFCON                   0x08
     53#define S3C24XX_UMCON                   0x0c
     54#define S3C24XX_UTRSTAT                 0x10
     55#define S3C24XX_UERSTAT                 0x14
     56#define S3C24XX_UFSTAT                  0x18
     57#define S3C24XX_UMSTAT                  0x1c
     58#define S3C24XX_UTXH                    0x20
     59#define S3C24XX_URXH                    0x24
     60#define S3C24XX_UBRDIV                  0x28
    5161
    52 /* Bits in UTXH register */
    53 #define S3C24XX_UTXH_TX_EMPTY   0x4
    54 
    55 typedef struct {
    56         ioport8_t *base;
    57 } s3c24xx_uart_instance_t;
     62/* Bits in UTRSTAT register */
     63#define S3C24XX_UTRSTAT_TX_EMPTY        0x4
     64#define S3C24XX_UTRSTAT_RDATA           0x1
    5865
    5966static void s3c24xx_uart_sendb(outdev_t *dev, uint8_t byte)
    … …  
    6774
    6875        /* Wait for transmitter to be empty. */
    69         while ((pio_read_32(utrstat) & S3C24XX_UTXH_TX_EMPTY) == 0)
     76        while ((pio_read_32(utrstat) & S3C24XX_UTRSTAT_TX_EMPTY) == 0)
    7077                ;
    7178
    … …  
    8693}
    8794
     95static irq_ownership_t s3c24xx_uart_claim(irq_t *irq)
     96{
     97        return IRQ_ACCEPT;
     98}
     99
     100static void s3c24xx_uart_irq_handler(irq_t *irq)
     101{
     102        s3c24xx_uart_instance_t *instance = irq->instance;
     103        ioport32_t *utrstat, *urxh;
     104
     105        utrstat = (ioport32_t *) (instance->base + S3C24XX_UTRSTAT);
     106        urxh = (ioport32_t *) (instance->base + S3C24XX_URXH);
     107
     108        if ((pio_read_32(utrstat) & S3C24XX_UTRSTAT_RDATA) != 0) {
     109                uint32_t data = pio_read_32(urxh);
     110                indev_push_character(instance->indev, data & 0xff);
     111        }
     112}
     113
    88114static outdev_operations_t s3c24xx_uart_ops = {
    89115        .write = s3c24xx_uart_putchar,
    … …  
    91117};
    92118
    93 outdev_t *s3c24xx_uart_init(ioport8_t *base)
     119outdev_t *s3c24xx_uart_init(ioport8_t *base, inr_t inr)
    94120{
    95121        outdev_t *uart_dev = malloc(sizeof(outdev_t), FRAME_ATOMIC);
    … …  
    108134
    109135        instance->base = base;
     136        instance->indev = NULL;
     137
     138        /* Initialize IRQ structure. */
     139        irq_initialize(&instance->irq);
     140        instance->irq.devno = device_assign_devno();
     141        instance->irq.inr = inr;
     142        instance->irq.claim = s3c24xx_uart_claim;
     143        instance->irq.handler = s3c24xx_uart_irq_handler;
     144        instance->irq.instance = instance;
     145
     146        /* Disable FIFO */
     147        ioport32_t *ufcon;
     148        ufcon = (ioport32_t *) (instance->base + S3C24XX_UFCON);
     149        pio_write_32(ufcon, pio_read_32(ufcon) & ~0x01);
     150
     151        /* Set RX interrupt to pulse mode */
     152        ioport32_t *ucon;
     153        ucon = (ioport32_t *) (instance->base + S3C24XX_UCON);
     154        pio_write_32(ucon, pio_read_32(ucon) & ~(1 << 8));
    110155
    111156        if (!fb_exported) {
    … …  
    124169}
    125170
     171void s3c24xx_uart_input_wire(s3c24xx_uart_instance_t *instance, indev_t *indev)
     172{
     173        ASSERT(instance);
     174        ASSERT(indev);
     175
     176        instance->indev = indev;
     177        irq_register(&instance->irq);
     178}
     179
    126180/** @}
    127181 */
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