Index: uspace/drv/block/ahci/ahci_hw.h
===================================================================
--- uspace/drv/block/ahci/ahci_hw.h	(revision 18b6a8849d630cc3bca153fb21bd225eebb16f4c)
+++ uspace/drv/block/ahci/ahci_hw.h	(revision e897527842650001c9fb751fa6a1792a272858d7)
@@ -216,16 +216,16 @@
 typedef union {
 	struct {
-	/** Indicates the completion status of BIST
-	 * non-zero value indicates a failure.
-	 */
-	unsigned int cc : 4;
-	/** Reserved. */
-	unsigned int reserved : 2;
-	/** Software sets this bit to 1 to invoke BIST,
-	 * the HBA clears this bit to 0 when BIST is complete.
-	 */
-	unsigned int sb : 1;
-	/** BIST capable. */
-	unsigned int bc : 1;
+		/** Indicates the completion status of BIST
+		 * non-zero value indicates a failure.
+		 */
+		unsigned int cc : 4;
+		/** Reserved. */
+		unsigned int reserved : 2;
+		/** Software sets this bit to 1 to invoke BIST,
+		 * the HBA clears this bit to 0 when BIST is complete.
+		 */
+		unsigned int sb : 1;
+		/** BIST capable. */
+		unsigned int bc : 1;
 	};
 	uint8_t u8;
@@ -252,6 +252,5 @@
 
 /** AHCI PCI register Subsystem Identifiers. */
-typedef struct
-{
+typedef struct {
 	/** Sub system vendor identifier. */
 	uint8_t ssvid;
@@ -261,6 +260,5 @@
 
 /** AHCI PCI registers Expansion ROM Base Address. */
-typedef struct
-{
+typedef struct {
 	/** Indicates the base address of the HBA expansion ROM. */
 	uint32_t u32;
@@ -268,6 +266,5 @@
 
 /** AHCI PCI register Capabilities Pointer. */
-typedef struct
-{
+typedef struct {
 	/** Indicates the first capability pointer offset. */
 	uint8_t u8;
@@ -275,6 +272,5 @@
 
 /** AHCI PCI register Interrupt Information. */
-typedef struct
-{
+typedef struct {
 	/* Software written value to indicate which interrupt vector
 	 * the interrupt is connected to.
@@ -286,6 +282,5 @@
 
 /** AHCI PCI register Min Grant (Optional). */
-typedef struct
-{
+typedef struct {
 	/** Indicates the minimum grant time that the device
 	 * wishes grant asserted.
@@ -295,6 +290,5 @@
 
 /** AHCI PCI register Max Latency (Optional). */
-typedef struct
-{
+typedef struct {
 	/** Indicates the maximum latency that the device can withstand. */
 	uint8_t u8;
@@ -431,6 +425,5 @@
 
 /** AHCI Memory register Command completion coalescing ports. */
-typedef struct
-{
+typedef struct {
 	/** If a bit is set to 1, the corresponding port is
 	 * part of the command completion coalescing feature.
@@ -440,6 +433,5 @@
 
 /** AHCI Memory register Enclosure management location. */
-typedef struct
-{
+typedef struct {
 	/** Size of the transmit message buffer area in dwords. */
 	uint16_t sz;
@@ -525,6 +517,5 @@
 
 /** AHCI Memory register Generic Host Control. */
-typedef struct
-{
+typedef struct {
 	/** Host Capabilities */
 	uint32_t cap;
@@ -942,6 +933,5 @@
 
 /** AHCI Memory register Port. */
-typedef volatile struct
-{
+typedef volatile struct {
 	/** Port x Command List Base Address. */
 	uint32_t pxclb;
@@ -1010,5 +1000,5 @@
 	/** Physical Region Descriptor Byte Count. */
 	uint32_t bytesprocessed;
-	 /** Command Table Descriptor Base Address. */
+	/** Command Table Descriptor Base Address. */
 	uint32_t cmdtable;
 	/** Command Table Descriptor Base Address Upper 32-bits. */
Index: uspace/drv/block/ddisk/ddisk.c
===================================================================
--- uspace/drv/block/ddisk/ddisk.c	(revision 18b6a8849d630cc3bca153fb21bd225eebb16f4c)
+++ uspace/drv/block/ddisk/ddisk.c	(revision e897527842650001c9fb751fa6a1792a272858d7)
@@ -495,6 +495,6 @@
 
 	/*
- 	 * Register IRQ handler.
- 	 */
+	 * Register IRQ handler.
+	 */
 	ddisk_regs_t *res_phys = (ddisk_regs_t *) res.base;
 	ddisk_irq_pio_ranges[0].base = res.base;