Index: boot/arch/sparc64/loader/ofwarch.c
===================================================================
--- boot/arch/sparc64/loader/ofwarch.c	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ boot/arch/sparc64/loader/ofwarch.c	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -70,5 +70,5 @@
 	uint64_t current_mid;
 	
-	__asm__ volatile ("ldxa [%1] %2, %0\n" : "=r" (current_mid) : "r" (0), "i" (ASI_UPA_CONFIG));
+	asm volatile ("ldxa [%1] %2, %0\n" : "=r" (current_mid) : "r" (0), "i" (ASI_UPA_CONFIG));
 	current_mid >>= UPA_CONFIG_MID_SHIFT;
 	current_mid &= UPA_CONFIG_MID_MASK;
Index: kernel/arch/amd64/include/asm.h
===================================================================
--- kernel/arch/amd64/include/asm.h	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ kernel/arch/amd64/include/asm.h	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -53,5 +53,5 @@
 	uintptr_t v;
 	
-	__asm__ volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((uint64_t)STACK_SIZE-1)));
+	asm volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((uint64_t)STACK_SIZE-1)));
 	
 	return v;
Index: kernel/arch/amd64/include/atomic.h
===================================================================
--- kernel/arch/amd64/include/atomic.h	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ kernel/arch/amd64/include/atomic.h	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -43,7 +43,7 @@
 static inline void atomic_inc(atomic_t *val) {
 #ifdef CONFIG_SMP
-	__asm__ volatile ("lock incq %0\n" : "=m" (val->count));
+	asm volatile ("lock incq %0\n" : "=m" (val->count));
 #else
-	__asm__ volatile ("incq %0\n" : "=m" (val->count));
+	asm volatile ("incq %0\n" : "=m" (val->count));
 #endif /* CONFIG_SMP */
 }
@@ -51,7 +51,7 @@
 static inline void atomic_dec(atomic_t *val) {
 #ifdef CONFIG_SMP
-	__asm__ volatile ("lock decq %0\n" : "=m" (val->count));
+	asm volatile ("lock decq %0\n" : "=m" (val->count));
 #else
-	__asm__ volatile ("decq %0\n" : "=m" (val->count));
+	asm volatile ("decq %0\n" : "=m" (val->count));
 #endif /* CONFIG_SMP */
 }
@@ -61,5 +61,5 @@
 	long r = 1;
 
-	__asm__ volatile (
+	asm volatile (
 		"lock xaddq %1, %0\n"
 		: "=m" (val->count), "+r" (r)
@@ -73,5 +73,5 @@
 	long r = -1;
 	
-	__asm__ volatile (
+	asm volatile (
 		"lock xaddq %1, %0\n"
 		: "=m" (val->count), "+r" (r)
@@ -87,5 +87,5 @@
 	uint64_t v;
 	
-	__asm__ volatile (
+	asm volatile (
 		"movq $1, %0\n"
 		"xchgq %0, %1\n"
@@ -103,5 +103,5 @@
 
 	preemption_disable();
-	__asm__ volatile (
+	asm volatile (
 		"0:;"
 #ifdef CONFIG_HT
Index: kernel/arch/amd64/include/memstr.h
===================================================================
--- kernel/arch/amd64/include/memstr.h	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ kernel/arch/amd64/include/memstr.h	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -52,5 +52,5 @@
         unative_t d0, d1, d2;
 
-        __asm__ __volatile__(
+        asm volatile(
                 "rep movsq\n\t"
                 "movq %4, %%rcx\n\t"
@@ -83,5 +83,5 @@
 	unative_t ret;
 	
-	__asm__ (
+	asm (
 		"repe cmpsb\n\t"
 		"je 1f\n\t"
@@ -109,5 +109,5 @@
 	unative_t d0, d1;
 	
-	__asm__ __volatile__ (
+	asm volatile (
 		"rep stosw\n\t"
 		: "=&D" (d0), "=&c" (d1), "=a" (x)
@@ -131,5 +131,5 @@
 	unative_t d0, d1;
 	
-	__asm__ __volatile__ (
+	asm volatile (
 		"rep stosb\n\t"
 		: "=&D" (d0), "=&c" (d1), "=a" (x)
Index: kernel/arch/amd64/src/cpu/cpu.c
===================================================================
--- kernel/arch/amd64/src/cpu/cpu.c	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ kernel/arch/amd64/src/cpu/cpu.c	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -77,5 +77,5 @@
 void cpu_setup_fpu(void)
 {
-	__asm__ volatile (
+	asm volatile (
 		"movq %%cr0, %%rax;"
 		"btsq $1, %%rax;" /* cr0.mp */
@@ -100,5 +100,5 @@
 void fpu_disable(void)
 {
-	__asm__	volatile (
+	asm	volatile (
 		"mov %%cr0,%%rax;"
 		"bts $3,%%rax;"
@@ -112,5 +112,5 @@
 void fpu_enable(void)
 {
-	__asm__	volatile (
+	asm	volatile (
 		"mov %%cr0,%%rax;"
 		"btr $3,%%rax;"
Index: kernel/arch/amd64/src/fpu_context.c
===================================================================
--- kernel/arch/amd64/src/fpu_context.c	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ kernel/arch/amd64/src/fpu_context.c	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -41,5 +41,5 @@
 void fpu_context_save(fpu_context_t *fctx)
 {
-	__asm__ volatile (
+	asm volatile (
 		"fxsave %0"
 		: "=m"(*fctx)
@@ -50,5 +50,5 @@
 void fpu_context_restore(fpu_context_t *fctx)
 {
-	__asm__ volatile (
+	asm volatile (
 		"fxrstor %0"
 		: "=m"(*fctx)
@@ -59,5 +59,5 @@
 {
 	/* TODO: Zero all SSE, MMX etc. registers */
-	__asm__ volatile (
+	asm volatile (
 		"fninit;"
 	);
Index: kernel/arch/amd64/src/userspace.c
===================================================================
--- kernel/arch/amd64/src/userspace.c	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ kernel/arch/amd64/src/userspace.c	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -55,5 +55,5 @@
 	ipl &= ~(0xcd4);
 
-	__asm__ volatile (""
+	asm volatile (""
 			  "pushq %0\n"
 			  "pushq %1\n"
Index: kernel/arch/ia32/include/asm.h
===================================================================
--- kernel/arch/ia32/include/asm.h	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ kernel/arch/ia32/include/asm.h	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -58,11 +58,18 @@
  * Halt the current CPU until interrupt event.
  */
-static inline void cpu_halt(void) { __asm__("hlt\n"); };
-static inline void cpu_sleep(void) { __asm__("hlt\n"); };
+static inline void cpu_halt(void)
+{
+	asm("hlt\n");
+};
+
+static inline void cpu_sleep(void)
+{
+	asm("hlt\n");
+};
 
 #define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \
     { \
 	unative_t res; \
-	__asm__ volatile ("movl %%" #reg ", %0" : "=r" (res) ); \
+	asm volatile ("movl %%" #reg ", %0" : "=r" (res) ); \
 	return res; \
     }
@@ -70,5 +77,5 @@
 #define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \
     { \
-	__asm__ volatile ("movl %0, %%" #reg : : "r" (regn)); \
+	asm volatile ("movl %0, %%" #reg : : "r" (regn)); \
     }
 
@@ -99,5 +106,8 @@
  * @param val Value to write
  */
-static inline void outb(uint16_t port, uint8_t val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }
+static inline void outb(uint16_t port, uint8_t val)
+{
+	asm volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) );
+}
 
 /** Word to port
@@ -108,5 +118,8 @@
  * @param val Value to write
  */
-static inline void outw(uint16_t port, uint16_t val) { __asm__ volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); }
+static inline void outw(uint16_t port, uint16_t val)
+{
+	asm volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) );
+}
 
 /** Double word to port
@@ -117,5 +130,8 @@
  * @param val Value to write
  */
-static inline void outl(uint16_t port, uint32_t val) { __asm__ volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); }
+static inline void outl(uint16_t port, uint32_t val)
+{
+	asm volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) );
+}
 
 /** Byte from port
@@ -126,5 +142,11 @@
  * @return Value read
  */
-static inline uint8_t inb(uint16_t port) { uint8_t val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }
+static inline uint8_t inb(uint16_t port)
+{
+	uint8_t val;
+	
+	asm volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) );
+	return val;
+}
 
 /** Word from port
@@ -135,5 +157,11 @@
  * @return Value read
  */
-static inline uint16_t inw(uint16_t port) { uint16_t val; __asm__ volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; }
+static inline uint16_t inw(uint16_t port)
+{
+	uint16_t val;
+	
+	asm volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) );
+	return val;
+}
 
 /** Double word from port
@@ -144,5 +172,11 @@
  * @return Value read
  */
-static inline uint32_t inl(uint16_t port) { uint32_t val; __asm__ volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; }
+static inline uint32_t inl(uint16_t port)
+{
+	uint32_t val;
+	
+	asm volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) );
+	return val;
+}
 
 /** Enable interrupts.
@@ -156,5 +190,5 @@
 {
 	ipl_t v;
-	__asm__ volatile (
+	asm volatile (
 		"pushf\n\t"
 		"popl %0\n\t"
@@ -175,5 +209,5 @@
 {
 	ipl_t v;
-	__asm__ volatile (
+	asm volatile (
 		"pushf\n\t"
 		"popl %0\n\t"
@@ -192,5 +226,5 @@
 static inline void interrupts_restore(ipl_t ipl)
 {
-	__asm__ volatile (
+	asm volatile (
 		"pushl %0\n\t"
 		"popf\n"
@@ -206,5 +240,5 @@
 {
 	ipl_t v;
-	__asm__ volatile (
+	asm volatile (
 		"pushf\n\t"
 		"popl %0\n"
@@ -224,5 +258,5 @@
 	uintptr_t v;
 	
-	__asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1)));
+	asm volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1)));
 	
 	return v;
@@ -234,5 +268,5 @@
 	uintptr_t *ip;
 
-	__asm__ volatile (
+	asm volatile (
 		"mov %%eip, %0"
 		: "=r" (ip)
@@ -247,5 +281,5 @@
 static inline void invlpg(uintptr_t addr)
 {
-	__asm__ volatile ("invlpg %0\n" :: "m" (*(unative_t *)addr));
+	asm volatile ("invlpg %0\n" :: "m" (*(unative_t *)addr));
 }
 
@@ -256,5 +290,5 @@
 static inline void gdtr_load(ptr_16_32_t *gdtr_reg)
 {
-	__asm__ volatile ("lgdtl %0\n" : : "m" (*gdtr_reg));
+	asm volatile ("lgdtl %0\n" : : "m" (*gdtr_reg));
 }
 
@@ -265,5 +299,5 @@
 static inline void gdtr_store(ptr_16_32_t *gdtr_reg)
 {
-	__asm__ volatile ("sgdtl %0\n" : : "m" (*gdtr_reg));
+	asm volatile ("sgdtl %0\n" : : "m" (*gdtr_reg));
 }
 
@@ -274,5 +308,5 @@
 static inline void idtr_load(ptr_16_32_t *idtr_reg)
 {
-	__asm__ volatile ("lidtl %0\n" : : "m" (*idtr_reg));
+	asm volatile ("lidtl %0\n" : : "m" (*idtr_reg));
 }
 
@@ -283,5 +317,5 @@
 static inline void tr_load(uint16_t sel)
 {
-	__asm__ volatile ("ltr %0" : : "r" (sel));
+	asm volatile ("ltr %0" : : "r" (sel));
 }
 
Index: kernel/arch/ia32/include/atomic.h
===================================================================
--- kernel/arch/ia32/include/atomic.h	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ kernel/arch/ia32/include/atomic.h	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -43,7 +43,7 @@
 static inline void atomic_inc(atomic_t *val) {
 #ifdef CONFIG_SMP
-	__asm__ volatile ("lock incl %0\n" : "=m" (val->count));
+	asm volatile ("lock incl %0\n" : "=m" (val->count));
 #else
-	__asm__ volatile ("incl %0\n" : "=m" (val->count));
+	asm volatile ("incl %0\n" : "=m" (val->count));
 #endif /* CONFIG_SMP */
 }
@@ -51,7 +51,7 @@
 static inline void atomic_dec(atomic_t *val) {
 #ifdef CONFIG_SMP
-	__asm__ volatile ("lock decl %0\n" : "=m" (val->count));
+	asm volatile ("lock decl %0\n" : "=m" (val->count));
 #else
-	__asm__ volatile ("decl %0\n" : "=m" (val->count));
+	asm volatile ("decl %0\n" : "=m" (val->count));
 #endif /* CONFIG_SMP */
 }
@@ -61,5 +61,5 @@
 	long r = 1;
 
-	__asm__ volatile (
+	asm volatile (
 		"lock xaddl %1, %0\n"
 		: "=m" (val->count), "+r" (r)
@@ -73,5 +73,5 @@
 	long r = -1;
 	
-	__asm__ volatile (
+	asm volatile (
 		"lock xaddl %1, %0\n"
 		: "=m" (val->count), "+r"(r)
@@ -87,5 +87,5 @@
 	uint32_t v;
 	
-	__asm__ volatile (
+	asm volatile (
 		"movl $1, %0\n"
 		"xchgl %0, %1\n"
@@ -102,5 +102,5 @@
 
 	preemption_disable();
-	__asm__ volatile (
+	asm volatile (
 		"0:;"
 #ifdef CONFIG_HT
Index: kernel/arch/ia32/include/barrier.h
===================================================================
--- kernel/arch/ia32/include/barrier.h	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ kernel/arch/ia32/include/barrier.h	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -47,10 +47,10 @@
  */
 
-#define CS_ENTER_BARRIER()	__asm__ volatile ("" ::: "memory")
-#define CS_LEAVE_BARRIER()	__asm__ volatile ("" ::: "memory")
+#define CS_ENTER_BARRIER()	asm volatile ("" ::: "memory")
+#define CS_LEAVE_BARRIER()	asm volatile ("" ::: "memory")
 
 static inline void cpuid_serialization(void)
 {
-	__asm__ volatile (
+	asm volatile (
 		"xorl %%eax, %%eax\n"
 		"cpuid\n"
@@ -60,10 +60,10 @@
 
 #ifdef CONFIG_FENCES_P4
-#	define memory_barrier()		__asm__ volatile ("mfence\n" ::: "memory")
-#	define read_barrier()		__asm__ volatile ("lfence\n" ::: "memory")
+#	define memory_barrier()		asm volatile ("mfence\n" ::: "memory")
+#	define read_barrier()		asm volatile ("lfence\n" ::: "memory")
 #	ifdef CONFIG_WEAK_MEMORY
-#		define write_barrier()	__asm__ volatile ("sfence\n" ::: "memory")
+#		define write_barrier()	asm volatile ("sfence\n" ::: "memory")
 #	else
-#		define write_barrier()  __asm__ volatile( "" ::: "memory");
+#		define write_barrier()  asm volatile( "" ::: "memory");
 #	endif
 #elif CONFIG_FENCES_P3
@@ -71,7 +71,7 @@
 #	define read_barrier()		cpuid_serialization()
 #	ifdef CONFIG_WEAK_MEMORY
-#		define write_barrier()	__asm__ volatile ("sfence\n" ::: "memory")
+#		define write_barrier()	asm volatile ("sfence\n" ::: "memory")
 #	else
-#		define write_barrier()  __asm__ volatile( "" ::: "memory");
+#		define write_barrier()  asm volatile( "" ::: "memory");
 #	endif
 #else
@@ -81,5 +81,5 @@
 #		define write_barrier()	cpuid_serialization()
 #	else
-#		define write_barrier()  __asm__ volatile( "" ::: "memory");
+#		define write_barrier()  asm volatile( "" ::: "memory");
 #	endif
 #endif
Index: kernel/arch/ia32/include/cpuid.h
===================================================================
--- kernel/arch/ia32/include/cpuid.h	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ kernel/arch/ia32/include/cpuid.h	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -77,5 +77,5 @@
 	uint32_t val, ret;
 	
-	__asm__ volatile (
+	asm volatile (
 		"pushf\n"               /* read flags */
 		"popl %0\n"
@@ -100,5 +100,5 @@
 static inline void cpuid(uint32_t cmd, cpu_info_t *info)
 {
-	__asm__ volatile (
+	asm volatile (
 		"movl %4, %%eax\n"
 		"cpuid\n"
Index: kernel/arch/ia32/include/memstr.h
===================================================================
--- kernel/arch/ia32/include/memstr.h	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ kernel/arch/ia32/include/memstr.h	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -52,5 +52,5 @@
         unative_t d0, d1, d2;
 
-        __asm__ __volatile__(
+        asm volatile(
                 /* copy all full dwords */
                 "rep movsl\n\t"
@@ -89,5 +89,5 @@
 	int ret;
 	
-	__asm__ (
+	asm (
 		"repe cmpsb\n\t"
 		"je 1f\n\t"
@@ -115,5 +115,5 @@
 	uint32_t d0, d1;
 	
-	__asm__ __volatile__ (
+	asm volatile (
 		"rep stosw\n\t"
 		: "=&D" (d0), "=&c" (d1), "=a" (x)
@@ -137,5 +137,5 @@
 	uint32_t d0, d1;
 	
-	__asm__ __volatile__ (
+	asm volatile (
 		"rep stosb\n\t"
 		: "=&D" (d0), "=&c" (d1), "=a" (x)
Index: kernel/arch/ia32/src/cpu/cpu.c
===================================================================
--- kernel/arch/ia32/src/cpu/cpu.c	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ kernel/arch/ia32/src/cpu/cpu.c	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -72,5 +72,5 @@
 void fpu_disable(void)
 {
-	__asm__ volatile (
+	asm volatile (
 		"mov %%cr0,%%eax;"
 		"or $8,%%eax;"
@@ -84,5 +84,5 @@
 void fpu_enable(void)
 {
-	__asm__ volatile (
+	asm volatile (
 		"mov %%cr0,%%eax;"
 		"and $0xffFFffF7,%%eax;"
Index: kernel/arch/ia32/src/fpu_context.c
===================================================================
--- kernel/arch/ia32/src/fpu_context.c	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ kernel/arch/ia32/src/fpu_context.c	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -44,5 +44,5 @@
 static void fpu_context_f_save(fpu_context_t *fctx)
 {
-	__asm__ volatile (
+	asm volatile (
 		"fnsave %0"
 		: "=m"(*fctx)
@@ -52,5 +52,5 @@
 static void fpu_context_f_restore(fpu_context_t *fctx)
 {
-	__asm__ volatile (
+	asm volatile (
 		"frstor %0"
 		: "=m"(*fctx)
@@ -60,5 +60,5 @@
 static void fpu_context_fx_save(fpu_context_t *fctx)
 {
-	__asm__ volatile (
+	asm volatile (
 		"fxsave %0"
 		: "=m"(*fctx)
@@ -68,5 +68,5 @@
 static void fpu_context_fx_restore(fpu_context_t *fctx)
 {
-	__asm__ volatile (
+	asm volatile (
 		"fxrstor %0"
 		: "=m"(*fctx)
@@ -104,5 +104,5 @@
 {
 	uint32_t help0 = 0, help1 = 0;
-	__asm__ volatile (
+	asm volatile (
 		"fninit;\n"
 		"stmxcsr %0\n"
Index: kernel/arch/ia32/src/pm.c
===================================================================
--- kernel/arch/ia32/src/pm.c	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ kernel/arch/ia32/src/pm.c	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -148,5 +148,5 @@
 static void clean_IOPL_NT_flags(void)
 {
-	__asm__ volatile (
+	asm volatile (
 		"pushfl\n"
 		"pop %%eax\n"
@@ -161,5 +161,5 @@
 static void clean_AM_flag(void)
 {
-	__asm__ volatile (
+	asm volatile (
 		"mov %%cr0, %%eax\n"
 		"and $0xfffbffff, %%eax\n"
Index: kernel/arch/ia32/src/userspace.c
===================================================================
--- kernel/arch/ia32/src/userspace.c	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ kernel/arch/ia32/src/userspace.c	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -52,5 +52,5 @@
 	ipl = interrupts_disable();
 
-	__asm__ volatile (
+	asm volatile (
 		/*
 		 * Clear nested task flag.
Index: kernel/arch/ia32xen/include/asm.h
===================================================================
--- kernel/arch/ia32xen/include/asm.h	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ kernel/arch/ia32xen/include/asm.h	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -60,5 +60,5 @@
     { \
 	unative_t res; \
-	__asm__ volatile ("movl %%" #reg ", %0" : "=r" (res) ); \
+	asm volatile ("movl %%" #reg ", %0" : "=r" (res) ); \
 	return res; \
     }
@@ -66,5 +66,5 @@
 #define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \
     { \
-	__asm__ volatile ("movl %0, %%" #reg : : "r" (regn)); \
+	asm volatile ("movl %0, %%" #reg : : "r" (regn)); \
     }
 
@@ -93,5 +93,5 @@
  * @param val Value to write
  */
-static inline void outb(uint16_t port, uint8_t val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }
+static inline void outb(uint16_t port, uint8_t val) { asm volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }
 
 /** Word to port
@@ -102,5 +102,5 @@
  * @param val Value to write
  */
-static inline void outw(uint16_t port, uint16_t val) { __asm__ volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); }
+static inline void outw(uint16_t port, uint16_t val) { asm volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); }
 
 /** Double word to port
@@ -111,5 +111,5 @@
  * @param val Value to write
  */
-static inline void outl(uint16_t port, uint32_t val) { __asm__ volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); }
+static inline void outl(uint16_t port, uint32_t val) { asm volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); }
 
 /** Byte from port
@@ -120,5 +120,5 @@
  * @return Value read
  */
-static inline uint8_t inb(uint16_t port) { uint8_t val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }
+static inline uint8_t inb(uint16_t port) { uint8_t val; asm volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }
 
 /** Word from port
@@ -129,5 +129,5 @@
  * @return Value read
  */
-static inline uint16_t inw(uint16_t port) { uint16_t val; __asm__ volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; }
+static inline uint16_t inw(uint16_t port) { uint16_t val; asm volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; }
 
 /** Double word from port
@@ -138,5 +138,5 @@
  * @return Value read
  */
-static inline uint32_t inl(uint16_t port) { uint32_t val; __asm__ volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; }
+static inline uint32_t inl(uint16_t port) { uint32_t val; asm volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; }
 
 /** Enable interrupts.
@@ -214,5 +214,5 @@
 	uintptr_t v;
 	
-	__asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1)));
+	asm volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1)));
 	
 	return v;
@@ -224,5 +224,5 @@
 	uintptr_t *ip;
 
-	__asm__ volatile (
+	asm volatile (
 		"mov %%eip, %0"
 		: "=r" (ip)
@@ -237,5 +237,5 @@
 static inline void invlpg(uintptr_t addr)
 {
-	__asm__ volatile ("invlpg %0\n" :: "m" (*(unative_t *)addr));
+	asm volatile ("invlpg %0\n" :: "m" (*(unative_t *)addr));
 }
 
@@ -246,5 +246,5 @@
 static inline void gdtr_load(ptr_16_32_t *gdtr_reg)
 {
-	__asm__ volatile ("lgdtl %0\n" : : "m" (*gdtr_reg));
+	asm volatile ("lgdtl %0\n" : : "m" (*gdtr_reg));
 }
 
@@ -255,5 +255,5 @@
 static inline void gdtr_store(ptr_16_32_t *gdtr_reg)
 {
-	__asm__ volatile ("sgdtl %0\n" : : "m" (*gdtr_reg));
+	asm volatile ("sgdtl %0\n" : : "m" (*gdtr_reg));
 }
 
@@ -264,5 +264,5 @@
 static inline void tr_load(uint16_t sel)
 {
-	__asm__ volatile ("ltr %0" : : "r" (sel));
+	asm volatile ("ltr %0" : : "r" (sel));
 }
 
Index: kernel/arch/ia32xen/src/pm.c
===================================================================
--- kernel/arch/ia32xen/src/pm.c	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ kernel/arch/ia32xen/src/pm.c	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -133,5 +133,5 @@
 static void clean_IOPL_NT_flags(void)
 {
-//	__asm__ volatile (
+//	asm volatile (
 //		"pushfl\n"
 //		"pop %%eax\n"
@@ -146,5 +146,5 @@
 static void clean_AM_flag(void)
 {
-//	__asm__ volatile (
+//	asm volatile (
 //		"mov %%cr0, %%eax\n"
 //		"and $0xfffbffff, %%eax\n"
Index: kernel/arch/ia64/include/asm.h
===================================================================
--- kernel/arch/ia64/include/asm.h	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ kernel/arch/ia64/include/asm.h	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -50,5 +50,5 @@
 	uint64_t v;
 
-	__asm__ volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1)));
+	asm volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1)));
 	
 	return v;
@@ -63,5 +63,5 @@
 	uint64_t v;
 	
-	__asm__ volatile ("mov %0 = psr\n" : "=r" (v));
+	asm volatile ("mov %0 = psr\n" : "=r" (v));
 	
 	return v;
@@ -76,5 +76,5 @@
 	uint64_t v;
 	
-	__asm__ volatile ("mov %0 = cr.iva\n" : "=r" (v));
+	asm volatile ("mov %0 = cr.iva\n" : "=r" (v));
 	
 	return v;
@@ -87,5 +87,5 @@
 static inline void iva_write(uint64_t v)
 {
-	__asm__ volatile ("mov cr.iva = %0\n" : : "r" (v));
+	asm volatile ("mov cr.iva = %0\n" : : "r" (v));
 }
 
@@ -99,5 +99,5 @@
 	uint64_t v;
 	
-	__asm__ volatile ("mov %0 = cr.ivr\n" : "=r" (v));
+	asm volatile ("mov %0 = cr.ivr\n" : "=r" (v));
 	
 	return v;
@@ -110,5 +110,5 @@
 static inline void itc_write(uint64_t v)
 {
-	__asm__ volatile ("mov ar.itc = %0\n" : : "r" (v));
+	asm volatile ("mov ar.itc = %0\n" : : "r" (v));
 }
 
@@ -121,5 +121,5 @@
 	uint64_t v;
 	
-	__asm__ volatile ("mov %0 = ar.itc\n" : "=r" (v));
+	asm volatile ("mov %0 = ar.itc\n" : "=r" (v));
 	
 	return v;
@@ -132,5 +132,5 @@
 static inline void itm_write(uint64_t v)
 {
-	__asm__ volatile ("mov cr.itm = %0\n" : : "r" (v));
+	asm volatile ("mov cr.itm = %0\n" : : "r" (v));
 }
 
@@ -143,5 +143,5 @@
 	uint64_t v;
 	
-	__asm__ volatile ("mov %0 = cr.itm\n" : "=r" (v));
+	asm volatile ("mov %0 = cr.itm\n" : "=r" (v));
 	
 	return v;
@@ -156,5 +156,5 @@
 	uint64_t v;
 	
-	__asm__ volatile ("mov %0 = cr.itv\n" : "=r" (v));
+	asm volatile ("mov %0 = cr.itv\n" : "=r" (v));
 	
 	return v;
@@ -167,5 +167,5 @@
 static inline void itv_write(uint64_t v)
 {
-	__asm__ volatile ("mov cr.itv = %0\n" : : "r" (v));
+	asm volatile ("mov cr.itv = %0\n" : : "r" (v));
 }
 
@@ -176,5 +176,5 @@
 static inline void eoi_write(uint64_t v)
 {
-	__asm__ volatile ("mov cr.eoi = %0\n" : : "r" (v));
+	asm volatile ("mov cr.eoi = %0\n" : : "r" (v));
 }
 
@@ -187,5 +187,5 @@
 	uint64_t v;
 
-	__asm__ volatile ("mov %0 = cr.tpr\n"  : "=r" (v));
+	asm volatile ("mov %0 = cr.tpr\n"  : "=r" (v));
 	
 	return v;
@@ -198,5 +198,5 @@
 static inline void tpr_write(uint64_t v)
 {
-	__asm__ volatile ("mov cr.tpr = %0\n" : : "r" (v));
+	asm volatile ("mov cr.tpr = %0\n" : : "r" (v));
 }
 
@@ -212,5 +212,5 @@
 	uint64_t v;
 	
-	__asm__ volatile (
+	asm volatile (
 		"mov %0 = psr\n"
 		"rsm %1\n"
@@ -233,5 +233,5 @@
 	uint64_t v;
 	
-	__asm__ volatile (
+	asm volatile (
 		"mov %0 = psr\n"
 		"ssm %1\n"
@@ -271,5 +271,5 @@
 static inline void pk_disable(void)
 {
-	__asm__ volatile ("rsm %0\n" : : "i" (PSR_PK_MASK));
+	asm volatile ("rsm %0\n" : : "i" (PSR_PK_MASK));
 }
 
Index: kernel/arch/ia64/include/atomic.h
===================================================================
--- kernel/arch/ia64/include/atomic.h	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ kernel/arch/ia64/include/atomic.h	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -47,5 +47,5 @@
 	long v;
 
- 	__asm__ volatile ("fetchadd8.rel %0 = %1, %2\n" : "=r" (v), "+m" (val->count) : "i" (imm));
+ 	asm volatile ("fetchadd8.rel %0 = %1, %2\n" : "=r" (v), "+m" (val->count) : "i" (imm));
  
 	return v;
Index: kernel/arch/ia64/include/barrier.h
===================================================================
--- kernel/arch/ia64/include/barrier.h	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ kernel/arch/ia64/include/barrier.h	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -42,10 +42,10 @@
 #define CS_LEAVE_BARRIER()	memory_barrier()
 
-#define memory_barrier()	__asm__ volatile ("mf\n" ::: "memory")
+#define memory_barrier()	asm volatile ("mf\n" ::: "memory")
 #define read_barrier()		memory_barrier()
 #define write_barrier()		memory_barrier()
 
-#define srlz_i()		__asm__ volatile (";; srlz.i ;;\n" ::: "memory")
-#define srlz_d()		__asm__ volatile (";; srlz.d\n" ::: "memory")
+#define srlz_i()		asm volatile (";; srlz.i ;;\n" ::: "memory")
+#define srlz_d()		asm volatile (";; srlz.d\n" ::: "memory")
 
 #endif
Index: kernel/arch/ia64/include/cpu.h
===================================================================
--- kernel/arch/ia64/include/cpu.h	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ kernel/arch/ia64/include/cpu.h	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -59,5 +59,5 @@
 	uint64_t v;
 	
-	__asm__ volatile ("mov %0 = cpuid[%1]\n" : "=r" (v) : "r" (n));
+	asm volatile ("mov %0 = cpuid[%1]\n" : "=r" (v) : "r" (n));
 	
 	return v;
Index: kernel/arch/ia64/include/mm/page.h
===================================================================
--- kernel/arch/ia64/include/mm/page.h	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ kernel/arch/ia64/include/mm/page.h	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -195,5 +195,5 @@
 	uint64_t ret;
 
-	__asm__ volatile ("thash %0 = %1\n" : "=r" (ret) : "r" (va));
+	asm volatile ("thash %0 = %1\n" : "=r" (ret) : "r" (va));
 
 	return ret;
@@ -213,5 +213,5 @@
 	uint64_t ret;
 
-	__asm__ volatile ("ttag %0 = %1\n" : "=r" (ret) : "r" (va));
+	asm volatile ("ttag %0 = %1\n" : "=r" (ret) : "r" (va));
 
 	return ret;
@@ -228,5 +228,5 @@
 	uint64_t ret;
 	ASSERT(i < REGION_REGISTERS);
-	__asm__ volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i << VRN_SHIFT));
+	asm volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i << VRN_SHIFT));
 	return ret;
 }
@@ -240,5 +240,5 @@
 {
 	ASSERT(i < REGION_REGISTERS);
-	__asm__ volatile (
+	asm volatile (
 		"mov rr[%0] = %1\n" 
 		: 
@@ -255,5 +255,5 @@
 	uint64_t ret;
 	
-	__asm__ volatile ("mov %0 = cr.pta\n" : "=r" (ret));
+	asm volatile ("mov %0 = cr.pta\n" : "=r" (ret));
 	
 	return ret;
@@ -266,5 +266,5 @@
 static inline void pta_write(uint64_t v)
 {
-	__asm__ volatile ("mov cr.pta = %0\n" : : "r" (v));
+	asm volatile ("mov cr.pta = %0\n" : : "r" (v));
 }
 
Index: kernel/arch/ia64/src/ia64.c
===================================================================
--- kernel/arch/ia64/src/ia64.c	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ kernel/arch/ia64/src/ia64.c	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -134,5 +134,5 @@
 	psr.bn = 1;				/* start in bank 0 */
 
-	__asm__ volatile ("mov %0 = ar.rsc\n" : "=r" (rsc.value));
+	asm volatile ("mov %0 = ar.rsc\n" : "=r" (rsc.value));
 	rsc.loadrs = 0;
 	rsc.be = false;
Index: kernel/arch/ia64/src/mm/tlb.c
===================================================================
--- kernel/arch/ia64/src/mm/tlb.c	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ kernel/arch/ia64/src/mm/tlb.c	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -73,5 +73,5 @@
 	for(i = 0; i < count1; i++) {
 		for(j = 0; j < count2; j++) {
-			__asm__ volatile (
+			asm volatile (
 				"ptc.e %0 ;;"
 				:
@@ -180,5 +180,5 @@
 	/*cnt+=(page!=va);*/
 	for(; va<(page+cnt*(PAGE_SIZE)); va += (1<<ps))	{
-		__asm__ volatile (
+		asm volatile (
 			"ptc.l %0,%1;;"
 			:
@@ -245,5 +245,5 @@
 	}
 	
-	__asm__ volatile (
+	asm volatile (
 		"mov r8=psr;;\n"
 		"rsm %0;;\n"   			/* PSR_IC_MASK */
@@ -321,5 +321,5 @@
 	}
 
-	__asm__ volatile (
+	asm volatile (
 		"mov r8=psr;;\n"
 		"rsm %0;;\n"			/* PSR_IC_MASK */
@@ -383,5 +383,5 @@
 void dtr_purge(uintptr_t page, count_t width)
 {
-	__asm__ volatile ("ptr.d %0, %1\n" : : "r" (page), "r" (width<<2));
+	asm volatile ("ptr.d %0, %1\n" : : "r" (page), "r" (width<<2));
 }
 
Index: kernel/arch/ia64/src/proc/scheduler.c
===================================================================
--- kernel/arch/ia64/src/proc/scheduler.c	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ kernel/arch/ia64/src/proc/scheduler.c	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -74,5 +74,5 @@
 	 * These values will be found there after switch from userspace.
 	 */
-	__asm__ volatile (
+	asm volatile (
 		"bsw.0\n"
 		"mov r22 = %0\n"
Index: kernel/arch/ia64/src/ski/ski.c
===================================================================
--- kernel/arch/ia64/src/ski/ski.c	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ kernel/arch/ia64/src/ski/ski.c	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -70,5 +70,5 @@
 void ski_putchar(chardev_t *d, const char ch)
 {
-	__asm__ volatile (
+	asm volatile (
 		"mov r15 = %0\n"
 		"mov r32 = %1\n"	/* r32 is in0 */
@@ -96,5 +96,5 @@
 	uint64_t ch;
 	
-	__asm__ volatile (
+	asm volatile (
 		"mov r15 = %1\n"
 		"break 0x80000;;\n"	/* modifies r8 */
@@ -205,5 +205,5 @@
 void ski_init_console(void)
 {
-	__asm__ volatile (
+	asm volatile (
 		"mov r15 = %0\n"
 		"break 0x80000\n"
Index: kernel/arch/mips32/include/asm.h
===================================================================
--- kernel/arch/mips32/include/asm.h	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ kernel/arch/mips32/include/asm.h	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -44,5 +44,5 @@
 {
 	/* Most of the simulators do not support */
-/*	__asm__ volatile ("wait"); */
+/*	asm volatile ("wait"); */
 }
 
@@ -57,5 +57,5 @@
 	uintptr_t v;
 	
-	__asm__ volatile ("and %0, $29, %1\n" : "=r" (v) : "r" (~(STACK_SIZE-1)));
+	asm volatile ("and %0, $29, %1\n" : "=r" (v) : "r" (~(STACK_SIZE-1)));
 	
 	return v;
Index: kernel/arch/mips32/include/atomic.h
===================================================================
--- kernel/arch/mips32/include/atomic.h	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ kernel/arch/mips32/include/atomic.h	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -56,5 +56,5 @@
 	long tmp, v;
 
-	__asm__ volatile (
+	asm volatile (
 		"1:\n"
 		"	ll %0, %1\n"
Index: kernel/arch/mips32/include/barrier.h
===================================================================
--- kernel/arch/mips32/include/barrier.h	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ kernel/arch/mips32/include/barrier.h	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -39,10 +39,10 @@
  * TODO: implement true MIPS memory barriers for macros below.
  */
-#define CS_ENTER_BARRIER()	__asm__ volatile ("" ::: "memory")
-#define CS_LEAVE_BARRIER()	__asm__ volatile ("" ::: "memory")
+#define CS_ENTER_BARRIER()	asm volatile ("" ::: "memory")
+#define CS_LEAVE_BARRIER()	asm volatile ("" ::: "memory")
 
-#define memory_barrier()        __asm__ volatile ("" ::: "memory")
-#define read_barrier()          __asm__ volatile ("" ::: "memory")
-#define write_barrier()         __asm__ volatile ("" ::: "memory")
+#define memory_barrier()        asm volatile ("" ::: "memory")
+#define read_barrier()          asm volatile ("" ::: "memory")
+#define write_barrier()         asm volatile ("" ::: "memory")
 
 #endif
Index: kernel/arch/mips32/include/mm/tlb.h
===================================================================
--- kernel/arch/mips32/include/mm/tlb.h	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ kernel/arch/mips32/include/mm/tlb.h	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -143,5 +143,5 @@
 static inline void tlbp(void)
 {
-	__asm__ volatile ("tlbp\n\t");
+	asm volatile ("tlbp\n\t");
 }
 
@@ -153,5 +153,5 @@
 static inline void tlbr(void)
 {
-	__asm__ volatile ("tlbr\n\t");
+	asm volatile ("tlbr\n\t");
 }
 
@@ -162,5 +162,5 @@
 static inline void tlbwi(void)
 {
-	__asm__ volatile ("tlbwi\n\t");
+	asm volatile ("tlbwi\n\t");
 }
 
@@ -171,5 +171,5 @@
 static inline void tlbwr(void)
 {
-	__asm__ volatile ("tlbwr\n\t");
+	asm volatile ("tlbwr\n\t");
 }
 
Index: kernel/arch/sparc64/include/asm.h
===================================================================
--- kernel/arch/sparc64/include/asm.h	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ kernel/arch/sparc64/include/asm.h	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -52,5 +52,5 @@
 	uint64_t v;
 	
-	__asm__ volatile ("rdpr %%pstate, %0\n" : "=r" (v));
+	asm volatile ("rdpr %%pstate, %0\n" : "=r" (v));
 	
 	return v;
@@ -63,5 +63,5 @@
 static inline void pstate_write(uint64_t v)
 {
-	__asm__ volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));
+	asm volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));
 }
 
@@ -74,5 +74,5 @@
 	uint64_t v;
 	
-	__asm__ volatile ("rd %%tick_cmpr, %0\n" : "=r" (v));
+	asm volatile ("rd %%tick_cmpr, %0\n" : "=r" (v));
 	
 	return v;
@@ -85,5 +85,5 @@
 static inline void tick_compare_write(uint64_t v)
 {
-	__asm__ volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));
+	asm volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));
 }
 
@@ -96,5 +96,5 @@
 	uint64_t v;
 	
-	__asm__ volatile ("rdpr %%tick, %0\n" : "=r" (v));
+	asm volatile ("rdpr %%tick, %0\n" : "=r" (v));
 	
 	return v;
@@ -107,5 +107,5 @@
 static inline void tick_write(uint64_t v)
 {
-	__asm__ volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0));
+	asm volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0));
 }
 
@@ -118,5 +118,5 @@
 	uint64_t v;
 	
-	__asm__ volatile ("rd %%fprs, %0\n" : "=r" (v));
+	asm volatile ("rd %%fprs, %0\n" : "=r" (v));
 	
 	return v;
@@ -129,5 +129,5 @@
 static inline void fprs_write(uint64_t v)
 {
-	__asm__ volatile ("wr %0, %1, %%fprs\n" : : "r" (v), "i" (0));
+	asm volatile ("wr %0, %1, %%fprs\n" : : "r" (v), "i" (0));
 }
 
@@ -140,5 +140,5 @@
 	uint64_t v;
 
-	__asm__ volatile ("rd %%softint, %0\n" : "=r" (v));
+	asm volatile ("rd %%softint, %0\n" : "=r" (v));
 
 	return v;
@@ -151,5 +151,5 @@
 static inline void softint_write(uint64_t v)
 {
-	__asm__ volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0));
+	asm volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0));
 }
 
@@ -162,5 +162,5 @@
 static inline void clear_softint_write(uint64_t v)
 {
-	__asm__ volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0));
+	asm volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0));
 }
 
@@ -173,5 +173,5 @@
 static inline void set_softint_write(uint64_t v)
 {
-	__asm__ volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0));
+	asm volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0));
 }
 
@@ -248,5 +248,5 @@
 	uintptr_t unbiased_sp;
 	
-	__asm__ volatile ("add %%sp, %1, %0\n" : "=r" (unbiased_sp) : "i" (STACK_BIAS));
+	asm volatile ("add %%sp, %1, %0\n" : "=r" (unbiased_sp) : "i" (STACK_BIAS));
 	
 	return ALIGN_DOWN(unbiased_sp, STACK_SIZE);
@@ -261,5 +261,5 @@
 	uint64_t v;
 	
-	__asm__ volatile ("rdpr %%ver, %0\n" : "=r" (v));
+	asm volatile ("rdpr %%ver, %0\n" : "=r" (v));
 	
 	return v;
@@ -274,5 +274,5 @@
 	uint64_t v;
 	
-	__asm__ volatile ("rdpr %%tpc, %0\n" : "=r" (v));
+	asm volatile ("rdpr %%tpc, %0\n" : "=r" (v));
 	
 	return v;
@@ -287,5 +287,5 @@
 	uint64_t v;
 	
-	__asm__ volatile ("rdpr %%tl, %0\n" : "=r" (v));
+	asm volatile ("rdpr %%tl, %0\n" : "=r" (v));
 	
 	return v;
@@ -300,5 +300,5 @@
 	uint64_t v;
 	
-	__asm__ volatile ("rdpr %%tba, %0\n" : "=r" (v));
+	asm volatile ("rdpr %%tba, %0\n" : "=r" (v));
 	
 	return v;
@@ -311,5 +311,5 @@
 static inline void tba_write(uint64_t v)
 {
-	__asm__ volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));
+	asm volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));
 }
 
@@ -325,5 +325,5 @@
 	uint64_t v;
 	
-	__asm__ volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" ((unsigned) asi));
+	asm volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" ((unsigned) asi));
 	
 	return v;
@@ -338,5 +338,5 @@
 static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v)
 {
-	__asm__ volatile ("stxa %0, [%1] %2\n" : :  "r" (v), "r" (va), "i" ((unsigned) asi) : "memory");
+	asm volatile ("stxa %0, [%1] %2\n" : :  "r" (v), "r" (va), "i" ((unsigned) asi) : "memory");
 }
 
@@ -344,5 +344,5 @@
 static inline void flushw(void)
 {
-	__asm__ volatile ("flushw\n");
+	asm volatile ("flushw\n");
 }
 
@@ -350,5 +350,5 @@
 static inline void nucleus_enter(void)
 {
-	__asm__ volatile ("wrpr %g0, 1, %tl\n");
+	asm volatile ("wrpr %g0, 1, %tl\n");
 }
 
@@ -356,5 +356,5 @@
 static inline void nucleus_leave(void)
 {
-	__asm__ volatile ("wrpr %g0, %g0, %tl\n");
+	asm volatile ("wrpr %g0, %g0, %tl\n");
 }
 
Index: kernel/arch/sparc64/include/atomic.h
===================================================================
--- kernel/arch/sparc64/include/atomic.h	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ kernel/arch/sparc64/include/atomic.h	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -58,5 +58,5 @@
 		a = *((uint64_t *) x);
 		b = a + i;
-		__asm__ volatile ("casx %0, %2, %1\n" : "+m" (*((uint64_t *)x)), "+r" (b) : "r" (a));
+		asm volatile ("casx %0, %2, %1\n" : "+m" (*((uint64_t *)x)), "+r" (b) : "r" (a));
 	} while (a != b);
 
@@ -99,5 +99,5 @@
 	volatile uintptr_t x = (uint64_t) &val->count;
 
-	__asm__ volatile ("casx %0, %2, %1\n" : "+m" (*((uint64_t *) x)), "+r" (v) : "r" (0));
+	asm volatile ("casx %0, %2, %1\n" : "+m" (*((uint64_t *) x)), "+r" (v) : "r" (0));
 
 	return v;
@@ -111,5 +111,5 @@
 	volatile uintptr_t x = (uint64_t) &val->count;
 
-	__asm__ volatile (
+	asm volatile (
 	"0:\n"
 		"casx %0, %3, %1\n"
Index: kernel/arch/sparc64/include/barrier.h
===================================================================
--- kernel/arch/sparc64/include/barrier.h	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ kernel/arch/sparc64/include/barrier.h	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -40,10 +40,10 @@
  */
 #define CS_ENTER_BARRIER() 				\
-	__asm__ volatile (				\
+	asm volatile (				\
 		"membar #LoadLoad | #LoadStore\n"	\
 		::: "memory"				\
 	)
 #define CS_LEAVE_BARRIER()				\
-	__asm__ volatile ( 				\
+	asm volatile ( 				\
 		"membar #StoreStore\n"			\
 		"membar #LoadStore\n"			\
@@ -52,9 +52,9 @@
 
 #define memory_barrier()	\
-	__asm__ volatile ("membar #LoadLoad | #StoreStore\n" ::: "memory")
+	asm volatile ("membar #LoadLoad | #StoreStore\n" ::: "memory")
 #define read_barrier()		\
-	__asm__ volatile ("membar #LoadLoad\n" ::: "memory")
+	asm volatile ("membar #LoadLoad\n" ::: "memory")
 #define write_barrier()		\
-	__asm__ volatile ("membar #StoreStore\n" ::: "memory")
+	asm volatile ("membar #StoreStore\n" ::: "memory")
 
 /** Flush Instruction Memory instruction. */
@@ -71,5 +71,5 @@
 	 */
 	 
-        __asm__ volatile ("flush %o7\n");
+        asm volatile ("flush %o7\n");
 }
 
@@ -77,5 +77,5 @@
 static inline void membar(void)
 {
-	__asm__ volatile ("membar #Sync\n");
+	asm volatile ("membar #Sync\n");
 }
 
Index: kernel/arch/sparc64/src/fpu_context.c
===================================================================
--- kernel/arch/sparc64/src/fpu_context.c	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ kernel/arch/sparc64/src/fpu_context.c	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -40,5 +40,5 @@
 void fpu_context_save(fpu_context_t *fctx)
 {
-	__asm__ volatile (
+	asm volatile (
 		"std %%f0, %0\n"
 		"std %%f2, %1\n"
@@ -68,5 +68,5 @@
 	 */
 	
-	__asm__ volatile (
+	asm volatile (
 		"std %%f32, %0\n"
 		"std %%f34, %1\n"
@@ -91,10 +91,10 @@
 	);
 	
-	__asm__ volatile ("stx %%fsr, %0\n" : "=m" (fctx->fsr));
+	asm volatile ("stx %%fsr, %0\n" : "=m" (fctx->fsr));
 }
 
 void fpu_context_restore(fpu_context_t *fctx)
 {
-	__asm__ volatile (
+	asm volatile (
 		"ldd %0, %%f0\n"
 		"ldd %1, %%f2\n"
@@ -125,5 +125,5 @@
 	 */
 	
-	__asm__ volatile (
+	asm volatile (
 		"ldd %0, %%f32\n"
 		"ldd %1, %%f34\n"
@@ -149,5 +149,5 @@
 	);
 	
-	__asm__ volatile ("ldx %0, %%fsr\n" : : "m" (fctx->fsr));
+	asm volatile ("ldx %0, %%fsr\n" : : "m" (fctx->fsr));
 }
 
Index: uspace/libc/arch/amd64/include/atomic.h
===================================================================
--- uspace/libc/arch/amd64/include/atomic.h	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ uspace/libc/arch/amd64/include/atomic.h	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -39,9 +39,9 @@
 
 static inline void atomic_inc(atomic_t *val) {
-	__asm__ volatile ("lock incq %0\n" : "=m" (val->count));
+	asm volatile ("lock incq %0\n" : "=m" (val->count));
 }
 
 static inline void atomic_dec(atomic_t *val) {
-	__asm__ volatile ("lock decq %0\n" : "=m" (val->count));
+	asm volatile ("lock decq %0\n" : "=m" (val->count));
 }
 
@@ -50,5 +50,5 @@
 	long r;
 
-	__asm__ volatile (
+	asm volatile (
 		"movq $1, %0\n"
 		"lock xaddq %0, %1\n"
@@ -63,5 +63,5 @@
 	long r;
 	
-	__asm__ volatile (
+	asm volatile (
 		"movq $-1, %0\n"
 		"lock xaddq %0, %1\n"
Index: uspace/libc/arch/amd64/include/thread.h
===================================================================
--- uspace/libc/arch/amd64/include/thread.h	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ uspace/libc/arch/amd64/include/thread.h	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -52,5 +52,5 @@
 	void * retval;
 
-	__asm__ ("movq %%fs:0, %0" : "=r"(retval));
+	asm ("movq %%fs:0, %0" : "=r"(retval));
 	return retval;
 }
Index: uspace/libc/arch/ia32/include/atomic.h
===================================================================
--- uspace/libc/arch/ia32/include/atomic.h	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ uspace/libc/arch/ia32/include/atomic.h	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -37,9 +37,9 @@
 
 static inline void atomic_inc(atomic_t *val) {
-	__asm__ volatile ("lock incl %0\n" : "=m" (val->count));
+	asm volatile ("lock incl %0\n" : "=m" (val->count));
 }
 
 static inline void atomic_dec(atomic_t *val) {
-	__asm__ volatile ("lock decl %0\n" : "=m" (val->count));
+	asm volatile ("lock decl %0\n" : "=m" (val->count));
 }
 
@@ -48,5 +48,5 @@
 	long r;
 
-	__asm__ volatile (
+	asm volatile (
 		"movl $1, %0\n"
 		"lock xaddl %0, %1\n"
@@ -61,5 +61,5 @@
 	long r;
 	
-	__asm__ volatile (
+	asm volatile (
 		"movl $-1, %0\n"
 		"lock xaddl %0, %1\n"
Index: uspace/libc/arch/ia32/include/thread.h
===================================================================
--- uspace/libc/arch/ia32/include/thread.h	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ uspace/libc/arch/ia32/include/thread.h	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -52,5 +52,5 @@
 	void * retval;
 
-	__asm__ ("movl %%gs:0, %0" : "=r"(retval));
+	asm ("movl %%gs:0, %0" : "=r"(retval));
 	return retval;
 }
Index: uspace/libc/arch/ia64/include/atomic.h
===================================================================
--- uspace/libc/arch/ia64/include/atomic.h	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ uspace/libc/arch/ia64/include/atomic.h	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -47,5 +47,5 @@
 	long v;
 
- 	__asm__ volatile ("fetchadd8.rel %0 = %1, %2\n" : "=r" (v), "+m" (val->count) : "i" (imm));
+ 	asm volatile ("fetchadd8.rel %0 = %1, %2\n" : "=r" (v), "+m" (val->count) : "i" (imm));
  
 	return v;
Index: uspace/libc/arch/ia64/include/thread.h
===================================================================
--- uspace/libc/arch/ia64/include/thread.h	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ uspace/libc/arch/ia64/include/thread.h	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -46,5 +46,5 @@
 static inline void __tcb_set(tcb_t *tcb)
 {
-	__asm__ volatile ("mov r13 = %0\n" : : "r" (tcb) : "r13");
+	asm volatile ("mov r13 = %0\n" : : "r" (tcb) : "r13");
 }
 
@@ -53,5 +53,5 @@
 	void *retval;
 
-	__asm__ volatile ("mov %0 = r13\n" : "=r" (retval));
+	asm volatile ("mov %0 = r13\n" : "=r" (retval));
 
 	return retval;
Index: uspace/libc/arch/mips32/include/atomic.h
===================================================================
--- uspace/libc/arch/mips32/include/atomic.h	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ uspace/libc/arch/mips32/include/atomic.h	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -57,5 +57,5 @@
 	long tmp, v;
 
-	__asm__ volatile (
+	asm volatile (
 		"1:\n"
 		"	ll %0, %1\n"
Index: uspace/libc/arch/mips32/include/thread.h
===================================================================
--- uspace/libc/arch/mips32/include/thread.h	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ uspace/libc/arch/mips32/include/thread.h	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -62,5 +62,5 @@
 	tp += MIPS_TP_OFFSET + sizeof(tcb_t);
 
-	__asm__ volatile ("add $27, %0, $0" : : "r"(tp)); /* Move tls to K1 */
+	asm volatile ("add $27, %0, $0" : : "r"(tp)); /* Move tls to K1 */
 }
 
@@ -69,5 +69,5 @@
 	void * retval;
 
-	__asm__ volatile("add %0, $27, $0" : "=r"(retval));
+	asm volatile("add %0, $27, $0" : "=r"(retval));
 
 	return (tcb_t *)(retval - MIPS_TP_OFFSET - sizeof(tcb_t));
Index: uspace/libc/arch/ppc32/include/atomic.h
===================================================================
--- uspace/libc/arch/ppc32/include/atomic.h	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ uspace/libc/arch/ppc32/include/atomic.h	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -40,5 +40,5 @@
 	long tmp;
 
-	asm __volatile__ (
+	asm volatile (
 		"1:\n"
 		"lwarx %0, 0, %2\n"
@@ -55,5 +55,5 @@
 	long tmp;
 
-	asm __volatile__(
+	asm volatile (
 		"1:\n"
 		"lwarx %0, 0, %2\n"
Index: uspace/libc/arch/ppc64/include/atomic.h
===================================================================
--- uspace/libc/arch/ppc64/include/atomic.h	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ uspace/libc/arch/ppc64/include/atomic.h	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -40,5 +40,5 @@
 	long tmp;
 
-	asm __volatile__ (
+	asm volatile (
 		"1:\n"
 		"lwarx %0, 0, %2\n"
@@ -55,5 +55,5 @@
 	long tmp;
 
-	asm __volatile__(
+	asm volatile (
 		"1:\n"
 		"lwarx %0, 0, %2\n"
Index: uspace/libc/arch/sparc64/include/atomic.h
===================================================================
--- uspace/libc/arch/sparc64/include/atomic.h	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ uspace/libc/arch/sparc64/include/atomic.h	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -54,5 +54,5 @@
 		a = val->count;
 		b = a + i;
-		__asm__ volatile ("casx %0, %2, %1\n" : "+m" (*val), "+r" (b) : "r" (a));
+		asm volatile ("casx %0, %2, %1\n" : "+m" (*val), "+r" (b) : "r" (a));
 	} while (a != b);
 
Index: uspace/libc/arch/sparc64/include/syscall.h
===================================================================
--- uspace/libc/arch/sparc64/include/syscall.h	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ uspace/libc/arch/sparc64/include/syscall.h	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -47,5 +47,5 @@
 	register uint64_t a4 asm("o3") = p4;
 
-	__asm__ volatile (
+	asm volatile (
 		"ta %5\n"
 		: "=r" (a1)
Index: uspace/libc/arch/sparc64/include/thread.h
===================================================================
--- uspace/libc/arch/sparc64/include/thread.h	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ uspace/libc/arch/sparc64/include/thread.h	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -46,5 +46,5 @@
 static inline void __tcb_set(tcb_t *tcb)
 {
-	__asm__ volatile ("mov %0, %%g7\n" : : "r" (tcb) : "g7");
+	asm volatile ("mov %0, %%g7\n" : : "r" (tcb) : "g7");
 }
 
@@ -53,5 +53,5 @@
 	void *retval;
 
-	__asm__ volatile ("mov %%g7, %0\n" : "=r" (retval));
+	asm volatile ("mov %%g7, %0\n" : "=r" (retval));
 
 	return retval;
Index: uspace/libc/malloc/malloc.c
===================================================================
--- uspace/libc/malloc/malloc.c	(revision 62c63fc1e28ff7b487c370d09617342a5d5ecb43)
+++ uspace/libc/malloc/malloc.c	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -1570,5 +1570,5 @@
   else {\
     unsigned int K;\
-    __asm__("bsrl %1,%0\n\t" : "=r" (K) : "rm"  (X));\
+    asm("bsrl %1,%0\n\t" : "=r" (K) : "rm"  (X));\
     I =  (bindex_t)((K << 1) + ((S >> (K + (TREEBIN_SHIFT-1)) & 1)));\
   }\
@@ -1629,5 +1629,5 @@
 {\
   unsigned int J;\
-  __asm__("bsfl %1,%0\n\t" : "=r" (J) : "rm" (X));\
+  asm("bsfl %1,%0\n\t" : "=r" (J) : "rm" (X));\
   I = (bindex_t)J;\
 }