Index: kernel/arch/ia64/include/asm.h =================================================================== --- kernel/arch/ia64/include/asm.h (revision f429331b6108df4294a421a92f3e9aaa64d95732) +++ kernel/arch/ia64/include/asm.h (revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89) @@ -50,5 +50,5 @@ uint64_t v; - __asm__ volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1))); + asm volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1))); return v; @@ -63,5 +63,5 @@ uint64_t v; - __asm__ volatile ("mov %0 = psr\n" : "=r" (v)); + asm volatile ("mov %0 = psr\n" : "=r" (v)); return v; @@ -76,5 +76,5 @@ uint64_t v; - __asm__ volatile ("mov %0 = cr.iva\n" : "=r" (v)); + asm volatile ("mov %0 = cr.iva\n" : "=r" (v)); return v; @@ -87,5 +87,5 @@ static inline void iva_write(uint64_t v) { - __asm__ volatile ("mov cr.iva = %0\n" : : "r" (v)); + asm volatile ("mov cr.iva = %0\n" : : "r" (v)); } @@ -99,5 +99,5 @@ uint64_t v; - __asm__ volatile ("mov %0 = cr.ivr\n" : "=r" (v)); + asm volatile ("mov %0 = cr.ivr\n" : "=r" (v)); return v; @@ -110,5 +110,5 @@ static inline void itc_write(uint64_t v) { - __asm__ volatile ("mov ar.itc = %0\n" : : "r" (v)); + asm volatile ("mov ar.itc = %0\n" : : "r" (v)); } @@ -121,5 +121,5 @@ uint64_t v; - __asm__ volatile ("mov %0 = ar.itc\n" : "=r" (v)); + asm volatile ("mov %0 = ar.itc\n" : "=r" (v)); return v; @@ -132,5 +132,5 @@ static inline void itm_write(uint64_t v) { - __asm__ volatile ("mov cr.itm = %0\n" : : "r" (v)); + asm volatile ("mov cr.itm = %0\n" : : "r" (v)); } @@ -143,5 +143,5 @@ uint64_t v; - __asm__ volatile ("mov %0 = cr.itm\n" : "=r" (v)); + asm volatile ("mov %0 = cr.itm\n" : "=r" (v)); return v; @@ -156,5 +156,5 @@ uint64_t v; - __asm__ volatile ("mov %0 = cr.itv\n" : "=r" (v)); + asm volatile ("mov %0 = cr.itv\n" : "=r" (v)); return v; @@ -167,5 +167,5 @@ static inline void itv_write(uint64_t v) { - __asm__ volatile ("mov cr.itv = %0\n" : : "r" (v)); + asm volatile ("mov cr.itv = %0\n" : : "r" (v)); } @@ -176,5 +176,5 @@ static inline void eoi_write(uint64_t v) { - __asm__ volatile ("mov cr.eoi = %0\n" : : "r" (v)); + asm volatile ("mov cr.eoi = %0\n" : : "r" (v)); } @@ -187,5 +187,5 @@ uint64_t v; - __asm__ volatile ("mov %0 = cr.tpr\n" : "=r" (v)); + asm volatile ("mov %0 = cr.tpr\n" : "=r" (v)); return v; @@ -198,5 +198,5 @@ static inline void tpr_write(uint64_t v) { - __asm__ volatile ("mov cr.tpr = %0\n" : : "r" (v)); + asm volatile ("mov cr.tpr = %0\n" : : "r" (v)); } @@ -212,5 +212,5 @@ uint64_t v; - __asm__ volatile ( + asm volatile ( "mov %0 = psr\n" "rsm %1\n" @@ -233,5 +233,5 @@ uint64_t v; - __asm__ volatile ( + asm volatile ( "mov %0 = psr\n" "ssm %1\n" @@ -271,5 +271,5 @@ static inline void pk_disable(void) { - __asm__ volatile ("rsm %0\n" : : "i" (PSR_PK_MASK)); + asm volatile ("rsm %0\n" : : "i" (PSR_PK_MASK)); } Index: kernel/arch/ia64/include/atomic.h =================================================================== --- kernel/arch/ia64/include/atomic.h (revision f429331b6108df4294a421a92f3e9aaa64d95732) +++ kernel/arch/ia64/include/atomic.h (revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89) @@ -47,5 +47,5 @@ long v; - __asm__ volatile ("fetchadd8.rel %0 = %1, %2\n" : "=r" (v), "+m" (val->count) : "i" (imm)); + asm volatile ("fetchadd8.rel %0 = %1, %2\n" : "=r" (v), "+m" (val->count) : "i" (imm)); return v; Index: kernel/arch/ia64/include/barrier.h =================================================================== --- kernel/arch/ia64/include/barrier.h (revision f429331b6108df4294a421a92f3e9aaa64d95732) +++ kernel/arch/ia64/include/barrier.h (revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89) @@ -42,10 +42,10 @@ #define CS_LEAVE_BARRIER() memory_barrier() -#define memory_barrier() __asm__ volatile ("mf\n" ::: "memory") +#define memory_barrier() asm volatile ("mf\n" ::: "memory") #define read_barrier() memory_barrier() #define write_barrier() memory_barrier() -#define srlz_i() __asm__ volatile (";; srlz.i ;;\n" ::: "memory") -#define srlz_d() __asm__ volatile (";; srlz.d\n" ::: "memory") +#define srlz_i() asm volatile (";; srlz.i ;;\n" ::: "memory") +#define srlz_d() asm volatile (";; srlz.d\n" ::: "memory") #endif Index: kernel/arch/ia64/include/cpu.h =================================================================== --- kernel/arch/ia64/include/cpu.h (revision f429331b6108df4294a421a92f3e9aaa64d95732) +++ kernel/arch/ia64/include/cpu.h (revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89) @@ -59,5 +59,5 @@ uint64_t v; - __asm__ volatile ("mov %0 = cpuid[%1]\n" : "=r" (v) : "r" (n)); + asm volatile ("mov %0 = cpuid[%1]\n" : "=r" (v) : "r" (n)); return v; Index: kernel/arch/ia64/include/mm/page.h =================================================================== --- kernel/arch/ia64/include/mm/page.h (revision f429331b6108df4294a421a92f3e9aaa64d95732) +++ kernel/arch/ia64/include/mm/page.h (revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89) @@ -195,5 +195,5 @@ uint64_t ret; - __asm__ volatile ("thash %0 = %1\n" : "=r" (ret) : "r" (va)); + asm volatile ("thash %0 = %1\n" : "=r" (ret) : "r" (va)); return ret; @@ -213,5 +213,5 @@ uint64_t ret; - __asm__ volatile ("ttag %0 = %1\n" : "=r" (ret) : "r" (va)); + asm volatile ("ttag %0 = %1\n" : "=r" (ret) : "r" (va)); return ret; @@ -228,5 +228,5 @@ uint64_t ret; ASSERT(i < REGION_REGISTERS); - __asm__ volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i << VRN_SHIFT)); + asm volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i << VRN_SHIFT)); return ret; } @@ -240,5 +240,5 @@ { ASSERT(i < REGION_REGISTERS); - __asm__ volatile ( + asm volatile ( "mov rr[%0] = %1\n" : @@ -255,5 +255,5 @@ uint64_t ret; - __asm__ volatile ("mov %0 = cr.pta\n" : "=r" (ret)); + asm volatile ("mov %0 = cr.pta\n" : "=r" (ret)); return ret; @@ -266,5 +266,5 @@ static inline void pta_write(uint64_t v) { - __asm__ volatile ("mov cr.pta = %0\n" : : "r" (v)); + asm volatile ("mov cr.pta = %0\n" : : "r" (v)); } Index: kernel/arch/ia64/src/ia64.c =================================================================== --- kernel/arch/ia64/src/ia64.c (revision f429331b6108df4294a421a92f3e9aaa64d95732) +++ kernel/arch/ia64/src/ia64.c (revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89) @@ -134,5 +134,5 @@ psr.bn = 1; /* start in bank 0 */ - __asm__ volatile ("mov %0 = ar.rsc\n" : "=r" (rsc.value)); + asm volatile ("mov %0 = ar.rsc\n" : "=r" (rsc.value)); rsc.loadrs = 0; rsc.be = false; Index: kernel/arch/ia64/src/mm/tlb.c =================================================================== --- kernel/arch/ia64/src/mm/tlb.c (revision f429331b6108df4294a421a92f3e9aaa64d95732) +++ kernel/arch/ia64/src/mm/tlb.c (revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89) @@ -73,5 +73,5 @@ for(i = 0; i < count1; i++) { for(j = 0; j < count2; j++) { - __asm__ volatile ( + asm volatile ( "ptc.e %0 ;;" : @@ -180,5 +180,5 @@ /*cnt+=(page!=va);*/ for(; va<(page+cnt*(PAGE_SIZE)); va += (1<