Index: kernel/arch/ia32/include/asm.h
===================================================================
--- kernel/arch/ia32/include/asm.h	(revision f429331b6108df4294a421a92f3e9aaa64d95732)
+++ kernel/arch/ia32/include/asm.h	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -58,11 +58,18 @@
  * Halt the current CPU until interrupt event.
  */
-static inline void cpu_halt(void) { __asm__("hlt\n"); };
-static inline void cpu_sleep(void) { __asm__("hlt\n"); };
+static inline void cpu_halt(void)
+{
+	asm("hlt\n");
+};
+
+static inline void cpu_sleep(void)
+{
+	asm("hlt\n");
+};
 
 #define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \
     { \
 	unative_t res; \
-	__asm__ volatile ("movl %%" #reg ", %0" : "=r" (res) ); \
+	asm volatile ("movl %%" #reg ", %0" : "=r" (res) ); \
 	return res; \
     }
@@ -70,5 +77,5 @@
 #define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \
     { \
-	__asm__ volatile ("movl %0, %%" #reg : : "r" (regn)); \
+	asm volatile ("movl %0, %%" #reg : : "r" (regn)); \
     }
 
@@ -99,5 +106,8 @@
  * @param val Value to write
  */
-static inline void outb(uint16_t port, uint8_t val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }
+static inline void outb(uint16_t port, uint8_t val)
+{
+	asm volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) );
+}
 
 /** Word to port
@@ -108,5 +118,8 @@
  * @param val Value to write
  */
-static inline void outw(uint16_t port, uint16_t val) { __asm__ volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); }
+static inline void outw(uint16_t port, uint16_t val)
+{
+	asm volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) );
+}
 
 /** Double word to port
@@ -117,5 +130,8 @@
  * @param val Value to write
  */
-static inline void outl(uint16_t port, uint32_t val) { __asm__ volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); }
+static inline void outl(uint16_t port, uint32_t val)
+{
+	asm volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) );
+}
 
 /** Byte from port
@@ -126,5 +142,11 @@
  * @return Value read
  */
-static inline uint8_t inb(uint16_t port) { uint8_t val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }
+static inline uint8_t inb(uint16_t port)
+{
+	uint8_t val;
+	
+	asm volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) );
+	return val;
+}
 
 /** Word from port
@@ -135,5 +157,11 @@
  * @return Value read
  */
-static inline uint16_t inw(uint16_t port) { uint16_t val; __asm__ volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; }
+static inline uint16_t inw(uint16_t port)
+{
+	uint16_t val;
+	
+	asm volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) );
+	return val;
+}
 
 /** Double word from port
@@ -144,5 +172,11 @@
  * @return Value read
  */
-static inline uint32_t inl(uint16_t port) { uint32_t val; __asm__ volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; }
+static inline uint32_t inl(uint16_t port)
+{
+	uint32_t val;
+	
+	asm volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) );
+	return val;
+}
 
 /** Enable interrupts.
@@ -156,5 +190,5 @@
 {
 	ipl_t v;
-	__asm__ volatile (
+	asm volatile (
 		"pushf\n\t"
 		"popl %0\n\t"
@@ -175,5 +209,5 @@
 {
 	ipl_t v;
-	__asm__ volatile (
+	asm volatile (
 		"pushf\n\t"
 		"popl %0\n\t"
@@ -192,5 +226,5 @@
 static inline void interrupts_restore(ipl_t ipl)
 {
-	__asm__ volatile (
+	asm volatile (
 		"pushl %0\n\t"
 		"popf\n"
@@ -206,5 +240,5 @@
 {
 	ipl_t v;
-	__asm__ volatile (
+	asm volatile (
 		"pushf\n\t"
 		"popl %0\n"
@@ -224,5 +258,5 @@
 	uintptr_t v;
 	
-	__asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1)));
+	asm volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1)));
 	
 	return v;
@@ -234,5 +268,5 @@
 	uintptr_t *ip;
 
-	__asm__ volatile (
+	asm volatile (
 		"mov %%eip, %0"
 		: "=r" (ip)
@@ -247,5 +281,5 @@
 static inline void invlpg(uintptr_t addr)
 {
-	__asm__ volatile ("invlpg %0\n" :: "m" (*(unative_t *)addr));
+	asm volatile ("invlpg %0\n" :: "m" (*(unative_t *)addr));
 }
 
@@ -256,5 +290,5 @@
 static inline void gdtr_load(ptr_16_32_t *gdtr_reg)
 {
-	__asm__ volatile ("lgdtl %0\n" : : "m" (*gdtr_reg));
+	asm volatile ("lgdtl %0\n" : : "m" (*gdtr_reg));
 }
 
@@ -265,5 +299,5 @@
 static inline void gdtr_store(ptr_16_32_t *gdtr_reg)
 {
-	__asm__ volatile ("sgdtl %0\n" : : "m" (*gdtr_reg));
+	asm volatile ("sgdtl %0\n" : : "m" (*gdtr_reg));
 }
 
@@ -274,5 +308,5 @@
 static inline void idtr_load(ptr_16_32_t *idtr_reg)
 {
-	__asm__ volatile ("lidtl %0\n" : : "m" (*idtr_reg));
+	asm volatile ("lidtl %0\n" : : "m" (*idtr_reg));
 }
 
@@ -283,5 +317,5 @@
 static inline void tr_load(uint16_t sel)
 {
-	__asm__ volatile ("ltr %0" : : "r" (sel));
+	asm volatile ("ltr %0" : : "r" (sel));
 }
 
Index: kernel/arch/ia32/include/atomic.h
===================================================================
--- kernel/arch/ia32/include/atomic.h	(revision f429331b6108df4294a421a92f3e9aaa64d95732)
+++ kernel/arch/ia32/include/atomic.h	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -43,7 +43,7 @@
 static inline void atomic_inc(atomic_t *val) {
 #ifdef CONFIG_SMP
-	__asm__ volatile ("lock incl %0\n" : "=m" (val->count));
+	asm volatile ("lock incl %0\n" : "=m" (val->count));
 #else
-	__asm__ volatile ("incl %0\n" : "=m" (val->count));
+	asm volatile ("incl %0\n" : "=m" (val->count));
 #endif /* CONFIG_SMP */
 }
@@ -51,7 +51,7 @@
 static inline void atomic_dec(atomic_t *val) {
 #ifdef CONFIG_SMP
-	__asm__ volatile ("lock decl %0\n" : "=m" (val->count));
+	asm volatile ("lock decl %0\n" : "=m" (val->count));
 #else
-	__asm__ volatile ("decl %0\n" : "=m" (val->count));
+	asm volatile ("decl %0\n" : "=m" (val->count));
 #endif /* CONFIG_SMP */
 }
@@ -61,5 +61,5 @@
 	long r = 1;
 
-	__asm__ volatile (
+	asm volatile (
 		"lock xaddl %1, %0\n"
 		: "=m" (val->count), "+r" (r)
@@ -73,5 +73,5 @@
 	long r = -1;
 	
-	__asm__ volatile (
+	asm volatile (
 		"lock xaddl %1, %0\n"
 		: "=m" (val->count), "+r"(r)
@@ -87,5 +87,5 @@
 	uint32_t v;
 	
-	__asm__ volatile (
+	asm volatile (
 		"movl $1, %0\n"
 		"xchgl %0, %1\n"
@@ -102,5 +102,5 @@
 
 	preemption_disable();
-	__asm__ volatile (
+	asm volatile (
 		"0:;"
 #ifdef CONFIG_HT
Index: kernel/arch/ia32/include/barrier.h
===================================================================
--- kernel/arch/ia32/include/barrier.h	(revision f429331b6108df4294a421a92f3e9aaa64d95732)
+++ kernel/arch/ia32/include/barrier.h	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -47,10 +47,10 @@
  */
 
-#define CS_ENTER_BARRIER()	__asm__ volatile ("" ::: "memory")
-#define CS_LEAVE_BARRIER()	__asm__ volatile ("" ::: "memory")
+#define CS_ENTER_BARRIER()	asm volatile ("" ::: "memory")
+#define CS_LEAVE_BARRIER()	asm volatile ("" ::: "memory")
 
 static inline void cpuid_serialization(void)
 {
-	__asm__ volatile (
+	asm volatile (
 		"xorl %%eax, %%eax\n"
 		"cpuid\n"
@@ -60,10 +60,10 @@
 
 #ifdef CONFIG_FENCES_P4
-#	define memory_barrier()		__asm__ volatile ("mfence\n" ::: "memory")
-#	define read_barrier()		__asm__ volatile ("lfence\n" ::: "memory")
+#	define memory_barrier()		asm volatile ("mfence\n" ::: "memory")
+#	define read_barrier()		asm volatile ("lfence\n" ::: "memory")
 #	ifdef CONFIG_WEAK_MEMORY
-#		define write_barrier()	__asm__ volatile ("sfence\n" ::: "memory")
+#		define write_barrier()	asm volatile ("sfence\n" ::: "memory")
 #	else
-#		define write_barrier()  __asm__ volatile( "" ::: "memory");
+#		define write_barrier()  asm volatile( "" ::: "memory");
 #	endif
 #elif CONFIG_FENCES_P3
@@ -71,7 +71,7 @@
 #	define read_barrier()		cpuid_serialization()
 #	ifdef CONFIG_WEAK_MEMORY
-#		define write_barrier()	__asm__ volatile ("sfence\n" ::: "memory")
+#		define write_barrier()	asm volatile ("sfence\n" ::: "memory")
 #	else
-#		define write_barrier()  __asm__ volatile( "" ::: "memory");
+#		define write_barrier()  asm volatile( "" ::: "memory");
 #	endif
 #else
@@ -81,5 +81,5 @@
 #		define write_barrier()	cpuid_serialization()
 #	else
-#		define write_barrier()  __asm__ volatile( "" ::: "memory");
+#		define write_barrier()  asm volatile( "" ::: "memory");
 #	endif
 #endif
Index: kernel/arch/ia32/include/cpuid.h
===================================================================
--- kernel/arch/ia32/include/cpuid.h	(revision f429331b6108df4294a421a92f3e9aaa64d95732)
+++ kernel/arch/ia32/include/cpuid.h	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -77,5 +77,5 @@
 	uint32_t val, ret;
 	
-	__asm__ volatile (
+	asm volatile (
 		"pushf\n"               /* read flags */
 		"popl %0\n"
@@ -100,5 +100,5 @@
 static inline void cpuid(uint32_t cmd, cpu_info_t *info)
 {
-	__asm__ volatile (
+	asm volatile (
 		"movl %4, %%eax\n"
 		"cpuid\n"
Index: kernel/arch/ia32/include/memstr.h
===================================================================
--- kernel/arch/ia32/include/memstr.h	(revision f429331b6108df4294a421a92f3e9aaa64d95732)
+++ kernel/arch/ia32/include/memstr.h	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -52,5 +52,5 @@
         unative_t d0, d1, d2;
 
-        __asm__ __volatile__(
+        asm volatile(
                 /* copy all full dwords */
                 "rep movsl\n\t"
@@ -89,5 +89,5 @@
 	int ret;
 	
-	__asm__ (
+	asm (
 		"repe cmpsb\n\t"
 		"je 1f\n\t"
@@ -115,5 +115,5 @@
 	uint32_t d0, d1;
 	
-	__asm__ __volatile__ (
+	asm volatile (
 		"rep stosw\n\t"
 		: "=&D" (d0), "=&c" (d1), "=a" (x)
@@ -137,5 +137,5 @@
 	uint32_t d0, d1;
 	
-	__asm__ __volatile__ (
+	asm volatile (
 		"rep stosb\n\t"
 		: "=&D" (d0), "=&c" (d1), "=a" (x)
Index: kernel/arch/ia32/src/cpu/cpu.c
===================================================================
--- kernel/arch/ia32/src/cpu/cpu.c	(revision f429331b6108df4294a421a92f3e9aaa64d95732)
+++ kernel/arch/ia32/src/cpu/cpu.c	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -72,5 +72,5 @@
 void fpu_disable(void)
 {
-	__asm__ volatile (
+	asm volatile (
 		"mov %%cr0,%%eax;"
 		"or $8,%%eax;"
@@ -84,5 +84,5 @@
 void fpu_enable(void)
 {
-	__asm__ volatile (
+	asm volatile (
 		"mov %%cr0,%%eax;"
 		"and $0xffFFffF7,%%eax;"
Index: kernel/arch/ia32/src/fpu_context.c
===================================================================
--- kernel/arch/ia32/src/fpu_context.c	(revision f429331b6108df4294a421a92f3e9aaa64d95732)
+++ kernel/arch/ia32/src/fpu_context.c	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -44,5 +44,5 @@
 static void fpu_context_f_save(fpu_context_t *fctx)
 {
-	__asm__ volatile (
+	asm volatile (
 		"fnsave %0"
 		: "=m"(*fctx)
@@ -52,5 +52,5 @@
 static void fpu_context_f_restore(fpu_context_t *fctx)
 {
-	__asm__ volatile (
+	asm volatile (
 		"frstor %0"
 		: "=m"(*fctx)
@@ -60,5 +60,5 @@
 static void fpu_context_fx_save(fpu_context_t *fctx)
 {
-	__asm__ volatile (
+	asm volatile (
 		"fxsave %0"
 		: "=m"(*fctx)
@@ -68,5 +68,5 @@
 static void fpu_context_fx_restore(fpu_context_t *fctx)
 {
-	__asm__ volatile (
+	asm volatile (
 		"fxrstor %0"
 		: "=m"(*fctx)
@@ -104,5 +104,5 @@
 {
 	uint32_t help0 = 0, help1 = 0;
-	__asm__ volatile (
+	asm volatile (
 		"fninit;\n"
 		"stmxcsr %0\n"
Index: kernel/arch/ia32/src/pm.c
===================================================================
--- kernel/arch/ia32/src/pm.c	(revision f429331b6108df4294a421a92f3e9aaa64d95732)
+++ kernel/arch/ia32/src/pm.c	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -148,5 +148,5 @@
 static void clean_IOPL_NT_flags(void)
 {
-	__asm__ volatile (
+	asm volatile (
 		"pushfl\n"
 		"pop %%eax\n"
@@ -161,5 +161,5 @@
 static void clean_AM_flag(void)
 {
-	__asm__ volatile (
+	asm volatile (
 		"mov %%cr0, %%eax\n"
 		"and $0xfffbffff, %%eax\n"
Index: kernel/arch/ia32/src/userspace.c
===================================================================
--- kernel/arch/ia32/src/userspace.c	(revision f429331b6108df4294a421a92f3e9aaa64d95732)
+++ kernel/arch/ia32/src/userspace.c	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -52,5 +52,5 @@
 	ipl = interrupts_disable();
 
-	__asm__ volatile (
+	asm volatile (
 		/*
 		 * Clear nested task flag.