Index: kernel/arch/amd64/include/asm.h
===================================================================
--- kernel/arch/amd64/include/asm.h	(revision f429331b6108df4294a421a92f3e9aaa64d95732)
+++ kernel/arch/amd64/include/asm.h	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -53,5 +53,5 @@
 	uintptr_t v;
 	
-	__asm__ volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((uint64_t)STACK_SIZE-1)));
+	asm volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((uint64_t)STACK_SIZE-1)));
 	
 	return v;
Index: kernel/arch/amd64/include/atomic.h
===================================================================
--- kernel/arch/amd64/include/atomic.h	(revision f429331b6108df4294a421a92f3e9aaa64d95732)
+++ kernel/arch/amd64/include/atomic.h	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -43,7 +43,7 @@
 static inline void atomic_inc(atomic_t *val) {
 #ifdef CONFIG_SMP
-	__asm__ volatile ("lock incq %0\n" : "=m" (val->count));
+	asm volatile ("lock incq %0\n" : "=m" (val->count));
 #else
-	__asm__ volatile ("incq %0\n" : "=m" (val->count));
+	asm volatile ("incq %0\n" : "=m" (val->count));
 #endif /* CONFIG_SMP */
 }
@@ -51,7 +51,7 @@
 static inline void atomic_dec(atomic_t *val) {
 #ifdef CONFIG_SMP
-	__asm__ volatile ("lock decq %0\n" : "=m" (val->count));
+	asm volatile ("lock decq %0\n" : "=m" (val->count));
 #else
-	__asm__ volatile ("decq %0\n" : "=m" (val->count));
+	asm volatile ("decq %0\n" : "=m" (val->count));
 #endif /* CONFIG_SMP */
 }
@@ -61,5 +61,5 @@
 	long r = 1;
 
-	__asm__ volatile (
+	asm volatile (
 		"lock xaddq %1, %0\n"
 		: "=m" (val->count), "+r" (r)
@@ -73,5 +73,5 @@
 	long r = -1;
 	
-	__asm__ volatile (
+	asm volatile (
 		"lock xaddq %1, %0\n"
 		: "=m" (val->count), "+r" (r)
@@ -87,5 +87,5 @@
 	uint64_t v;
 	
-	__asm__ volatile (
+	asm volatile (
 		"movq $1, %0\n"
 		"xchgq %0, %1\n"
@@ -103,5 +103,5 @@
 
 	preemption_disable();
-	__asm__ volatile (
+	asm volatile (
 		"0:;"
 #ifdef CONFIG_HT
Index: kernel/arch/amd64/include/memstr.h
===================================================================
--- kernel/arch/amd64/include/memstr.h	(revision f429331b6108df4294a421a92f3e9aaa64d95732)
+++ kernel/arch/amd64/include/memstr.h	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -52,5 +52,5 @@
         unative_t d0, d1, d2;
 
-        __asm__ __volatile__(
+        asm volatile(
                 "rep movsq\n\t"
                 "movq %4, %%rcx\n\t"
@@ -83,5 +83,5 @@
 	unative_t ret;
 	
-	__asm__ (
+	asm (
 		"repe cmpsb\n\t"
 		"je 1f\n\t"
@@ -109,5 +109,5 @@
 	unative_t d0, d1;
 	
-	__asm__ __volatile__ (
+	asm volatile (
 		"rep stosw\n\t"
 		: "=&D" (d0), "=&c" (d1), "=a" (x)
@@ -131,5 +131,5 @@
 	unative_t d0, d1;
 	
-	__asm__ __volatile__ (
+	asm volatile (
 		"rep stosb\n\t"
 		: "=&D" (d0), "=&c" (d1), "=a" (x)
Index: kernel/arch/amd64/src/cpu/cpu.c
===================================================================
--- kernel/arch/amd64/src/cpu/cpu.c	(revision f429331b6108df4294a421a92f3e9aaa64d95732)
+++ kernel/arch/amd64/src/cpu/cpu.c	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -77,5 +77,5 @@
 void cpu_setup_fpu(void)
 {
-	__asm__ volatile (
+	asm volatile (
 		"movq %%cr0, %%rax;"
 		"btsq $1, %%rax;" /* cr0.mp */
@@ -100,5 +100,5 @@
 void fpu_disable(void)
 {
-	__asm__	volatile (
+	asm	volatile (
 		"mov %%cr0,%%rax;"
 		"bts $3,%%rax;"
@@ -112,5 +112,5 @@
 void fpu_enable(void)
 {
-	__asm__	volatile (
+	asm	volatile (
 		"mov %%cr0,%%rax;"
 		"btr $3,%%rax;"
Index: kernel/arch/amd64/src/fpu_context.c
===================================================================
--- kernel/arch/amd64/src/fpu_context.c	(revision f429331b6108df4294a421a92f3e9aaa64d95732)
+++ kernel/arch/amd64/src/fpu_context.c	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -41,5 +41,5 @@
 void fpu_context_save(fpu_context_t *fctx)
 {
-	__asm__ volatile (
+	asm volatile (
 		"fxsave %0"
 		: "=m"(*fctx)
@@ -50,5 +50,5 @@
 void fpu_context_restore(fpu_context_t *fctx)
 {
-	__asm__ volatile (
+	asm volatile (
 		"fxrstor %0"
 		: "=m"(*fctx)
@@ -59,5 +59,5 @@
 {
 	/* TODO: Zero all SSE, MMX etc. registers */
-	__asm__ volatile (
+	asm volatile (
 		"fninit;"
 	);
Index: kernel/arch/amd64/src/userspace.c
===================================================================
--- kernel/arch/amd64/src/userspace.c	(revision f429331b6108df4294a421a92f3e9aaa64d95732)
+++ kernel/arch/amd64/src/userspace.c	(revision e7b7be3ff072782e570cb6ee64b50b1625a3fd89)
@@ -55,5 +55,5 @@
 	ipl &= ~(0xcd4);
 
-	__asm__ volatile (""
+	asm volatile (""
 			  "pushq %0\n"
 			  "pushq %1\n"