Index: kernel/arch/amd64/include/asm.h =================================================================== --- kernel/arch/amd64/include/asm.h (revision 9688513053f7f16516b100b89f79fae37a7695b5) +++ kernel/arch/amd64/include/asm.h (revision e762b4375e99a4a33536330659ad95ea048dbf84) @@ -27,5 +27,5 @@ */ -/** @addtogroup amd64 +/** @addtogroup amd64 * @{ */ @@ -46,4 +46,5 @@ * The stack is assumed to be STACK_SIZE bytes long. * The stack must start on page boundary. + * */ static inline uintptr_t get_stack_base(void) @@ -51,5 +52,9 @@ uintptr_t v; - asm volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((uint64_t)STACK_SIZE-1))); + asm volatile ( + "andq %%rsp, %[v]\n" + : [v] "=r" (v) + : "0" (~((uint64_t) STACK_SIZE-1)) + ); return v; @@ -73,10 +78,16 @@ * @param port Port to read from * @return Value read + * */ static inline uint8_t pio_read_8(ioport8_t *port) { uint8_t val; - - asm volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port)); + + asm volatile ( + "inb %w[port], %b[val]\n" + : [val] "=a" (val) + : [port] "d" (port) + ); + return val; } @@ -88,4 +99,5 @@ * @param port Port to read from * @return Value read + * */ static inline uint16_t pio_read_16(ioport16_t *port) @@ -93,5 +105,10 @@ uint16_t val; - asm volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port)); + asm volatile ( + "inw %w[port], %w[val]\n" + : [val] "=a" (val) + : [port] "d" (port) + ); + return val; } @@ -103,4 +120,5 @@ * @param port Port to read from * @return Value read + * */ static inline uint32_t pio_read_32(ioport32_t *port) @@ -108,5 +126,10 @@ uint32_t val; - asm volatile ("inl %w1, %0 \n" : "=a" (val) : "d" (port)); + asm volatile ( + "inl %w[port], %[val]\n" + : [val] "=a" (val) + : [port] "d" (port) + ); + return val; } @@ -118,8 +141,12 @@ * @param port Port to write to * @param val Value to write + * */ static inline void pio_write_8(ioport8_t *port, uint8_t val) { - asm volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port)); + asm volatile ( + "outb %b[val], %w[port]\n" + :: [val] "a" (val), [port] "d" (port) + ); } @@ -130,8 +157,12 @@ * @param port Port to write to * @param val Value to write + * */ static inline void pio_write_16(ioport16_t *port, uint16_t val) { - asm volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port)); + asm volatile ( + "outw %w[val], %w[port]\n" + :: [val] "a" (val), [port] "d" (port) + ); } @@ -142,8 +173,12 @@ * @param port Port to write to * @param val Value to write + * */ static inline void pio_write_32(ioport32_t *port, uint32_t val) { - asm volatile ("outl %0, %w1\n" : : "a" (val), "d" (port)); + asm volatile ( + "outl %[val], %w[port]\n" + :: [val] "a" (val), [port] "d" (port) + ); } @@ -160,13 +195,16 @@ * * @return Old interrupt priority level. + * */ static inline ipl_t interrupts_enable(void) { ipl_t v; - __asm__ volatile ( + + asm volatile ( "pushfq\n" - "popq %0\n" + "popq %[v]\n" "sti\n" - : "=r" (v) - ); + : [v] "=r" (v) + ); + return v; } @@ -178,13 +216,16 @@ * * @return Old interrupt priority level. + * */ static inline ipl_t interrupts_disable(void) { ipl_t v; - __asm__ volatile ( + + asm volatile ( "pushfq\n" - "popq %0\n" + "popq %[v]\n" "cli\n" - : "=r" (v) - ); + : [v] "=r" (v) + ); + return v; } @@ -195,11 +236,12 @@ * * @param ipl Saved interrupt priority level. + * */ static inline void interrupts_restore(ipl_t ipl) { - __asm__ volatile ( - "pushq %0\n" + asm volatile ( + "pushq %[ipl]\n" "popfq\n" - : : "r" (ipl) - ); + :: [ipl] "r" (ipl) + ); } @@ -209,12 +251,15 @@ * * @return Current interrupt priority level. + * */ static inline ipl_t interrupts_read(void) { ipl_t v; - __asm__ volatile ( + + asm volatile ( "pushfq\n" - "popq %0\n" - : "=r" (v) - ); + "popq %[v]\n" + : [v] "=r" (v) + ); + return v; } @@ -223,9 +268,10 @@ static inline void write_msr(uint32_t msr, uint64_t value) { - __asm__ volatile ( - "wrmsr;" : : "c" (msr), - "a" ((uint32_t)(value)), - "d" ((uint32_t)(value >> 32)) - ); + asm volatile ( + "wrmsr\n" + :: "c" (msr), + "a" ((uint32_t) (value)), + "d" ((uint32_t) (value >> 32)) + ); } @@ -233,9 +279,12 @@ { uint32_t ax, dx; - - __asm__ volatile ( - "rdmsr;" : "=a"(ax), "=d"(dx) : "c" (msr) - ); - return ((uint64_t)dx << 32) | ax; + + asm volatile ( + "rdmsr\n" + : "=a" (ax), "=d" (dx) + : "c" (msr) + ); + + return ((uint64_t) dx << 32) | ax; } @@ -244,17 +293,16 @@ * * Enable local APIC in MSR. + * */ static inline void enable_l_apic_in_msr() { - __asm__ volatile ( + asm volatile ( "movl $0x1b, %%ecx\n" "rdmsr\n" - "orl $(1<<11),%%eax\n" + "orl $(1 << 11),%%eax\n" "orl $(0xfee00000),%%eax\n" "wrmsr\n" - : - : - :"%eax","%ecx","%edx" - ); + ::: "%eax","%ecx","%edx" + ); } @@ -262,9 +310,10 @@ { uintptr_t *ip; - - __asm__ volatile ( - "mov %%rip, %0" - : "=r" (ip) - ); + + asm volatile ( + "mov %%rip, %[ip]" + : [ip] "=r" (ip) + ); + return ip; } @@ -273,8 +322,12 @@ * * @param addr Address on a page whose TLB entry is to be invalidated. + * */ static inline void invlpg(uintptr_t addr) { - __asm__ volatile ("invlpg %0\n" :: "m" (*((unative_t *)addr))); + asm volatile ( + "invlpg %[addr]\n" + :: [addr] "m" (*((unative_t *) addr)) + ); } @@ -282,8 +335,12 @@ * * @param gdtr_reg Address of memory from where to load GDTR. + * */ static inline void gdtr_load(struct ptr_16_64 *gdtr_reg) { - __asm__ volatile ("lgdtq %0\n" : : "m" (*gdtr_reg)); + asm volatile ( + "lgdtq %[gdtr_reg]\n" + :: [gdtr_reg] "m" (*gdtr_reg) + ); } @@ -291,8 +348,12 @@ * * @param gdtr_reg Address of memory to where to load GDTR. + * */ static inline void gdtr_store(struct ptr_16_64 *gdtr_reg) { - __asm__ volatile ("sgdtq %0\n" : : "m" (*gdtr_reg)); + asm volatile ( + "sgdtq %[gdtr_reg]\n" + :: [gdtr_reg] "m" (*gdtr_reg) + ); } @@ -300,8 +361,11 @@ * * @param idtr_reg Address of memory from where to load IDTR. + * */ static inline void idtr_load(struct ptr_16_64 *idtr_reg) { - __asm__ volatile ("lidtq %0\n" : : "m" (*idtr_reg)); + asm volatile ( + "lidtq %[idtr_reg]\n" + :: [idtr_reg] "m" (*idtr_reg)); } @@ -309,21 +373,31 @@ * * @param sel Selector specifying descriptor of TSS segment. + * */ static inline void tr_load(uint16_t sel) { - __asm__ volatile ("ltr %0" : : "r" (sel)); + asm volatile ( + "ltr %[sel]" + :: [sel] "r" (sel) + ); } #define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \ - { \ - unative_t res; \ - __asm__ volatile ("movq %%" #reg ", %0" : "=r" (res) ); \ - return res; \ - } + { \ + unative_t res; \ + asm volatile ( \ + "movq %%" #reg ", %[res]" \ + : [res] "=r" (res) \ + ); \ + return res; \ + } #define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \ - { \ - __asm__ volatile ("movq %0, %%" #reg : : "r" (regn)); \ - } + { \ + asm volatile ( \ + "movq %[regn], %%" #reg \ + :: [regn] "r" (regn) \ + ); \ + } GEN_READ_REG(cr0)