Index: kernel/arch/sparc64/include/trap/mmu.h
===================================================================
--- kernel/arch/sparc64/include/trap/mmu.h	(revision b254b3b9cf2ab6ddfb7a668c8739854bc5da0efb)
+++ kernel/arch/sparc64/include/trap/mmu.h	(revision e5ecc02b4e8dc0f4c95588b0f1601d1986173b13)
@@ -86,5 +86,5 @@
 	bz 0f						! page address is zero
 
-	or %g3, (TTE_CP|TTE_P|TTE_W), %g2		! 8K pages are the default (encoded as 0)
+	or %g3, (TTE_CV|TTE_CP|TTE_P|TTE_W), %g2	! 8K pages are the default (encoded as 0)
 	mov 1, %g3
 	sllx %g3, TTE_V_SHIFT, %g3
Index: kernel/arch/sparc64/src/start.S
===================================================================
--- kernel/arch/sparc64/src/start.S	(revision b254b3b9cf2ab6ddfb7a668c8739854bc5da0efb)
+++ kernel/arch/sparc64/src/start.S	(revision e5ecc02b4e8dc0f4c95588b0f1601d1986173b13)
@@ -115,5 +115,5 @@
 
 #define SET_TLB_DATA(r1, r2, imm) \
-	set TTE_L | TTE_CP | TTE_P | TTE_W | LMA | imm, %r1; \
+	set TTE_CV | TTE_CP | TTE_P | LMA | imm, %r1; \
 	set PAGESIZE_4M, %r2; \
 	sllx %r2, TTE_SIZE_SHIFT, %r2; \
@@ -124,5 +124,5 @@
 	
 	! write DTLB data and install the kernel mapping
-	SET_TLB_DATA(g1, g2, 0)			! use non-global mapping
+	SET_TLB_DATA(g1, g2, TTE_L | TTE_W)	! use non-global mapping
 	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG		
 	membar #Sync
@@ -141,5 +141,5 @@
 
 	! write DTLB data and install the kernel mapping in context 1
-	SET_TLB_DATA(g1, g2, 0)			! use non-global mapping
+	SET_TLB_DATA(g1, g2, TTE_W)			! use non-global mapping
 	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG		
 	membar #Sync
@@ -197,5 +197,5 @@
 
 	! write ITLB data and install the permanent kernel mapping in context 0
-	SET_TLB_DATA(g1, g2, 0)			! use non-global mapping
+	SET_TLB_DATA(g1, g2, TTE_L)		! use non-global mapping
 	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG		
 	flush %g5