Index: kernel/arch/arm32/include/barrier.h =================================================================== --- kernel/arch/arm32/include/barrier.h (revision 80dabb8d5cd8827e3f43939b3ce35fcce1382a99) +++ kernel/arch/arm32/include/barrier.h (revision e25eca8008c4df6f190fbd28a399c5e01406f863) @@ -47,4 +47,6 @@ #define write_barrier() asm volatile ("" ::: "memory") +#define smc_coherence(a) + #endif Index: kernel/arch/ia32/include/barrier.h =================================================================== --- kernel/arch/ia32/include/barrier.h (revision 80dabb8d5cd8827e3f43939b3ce35fcce1382a99) +++ kernel/arch/ia32/include/barrier.h (revision e25eca8008c4df6f190fbd28a399c5e01406f863) @@ -85,4 +85,12 @@ #endif +/* + * On ia32, the hardware takes care about instruction and data cache coherence, + * even on SMP systems. We issue a write barrier to be sure that writes + * queueing in the store buffer drain to the memory (even though it would be + * sufficient for them to drain to the D-cache). + */ +#define smc_coherence(a) write_barrier() + #endif Index: kernel/arch/ia64/include/barrier.h =================================================================== --- kernel/arch/ia64/include/barrier.h (revision 80dabb8d5cd8827e3f43939b3ce35fcce1382a99) +++ kernel/arch/ia64/include/barrier.h (revision e25eca8008c4df6f190fbd28a399c5e01406f863) @@ -46,6 +46,20 @@ #define write_barrier() memory_barrier() -#define srlz_i() asm volatile (";; srlz.i ;;\n" ::: "memory") -#define srlz_d() asm volatile (";; srlz.d\n" ::: "memory") +#define srlz_i() \ + asm volatile (";; srlz.i ;;\n" ::: "memory") +#define srlz_d() \ + asm volatile (";; srlz.d\n" ::: "memory") + +#define fc_i(a) \ + asm volatile ("fc.i %0\n" : "r" ((a)) :: "memory") +#define sync_i() \ + asm volatile (";; sync.i\n" ::: "memory") + +#define smc_coherence(a) \ +{ \ + fc_i((a)); \ + sync_i(); \ + srlz_i(); \ +} #endif Index: kernel/arch/mips32/include/barrier.h =================================================================== --- kernel/arch/mips32/include/barrier.h (revision 80dabb8d5cd8827e3f43939b3ce35fcce1382a99) +++ kernel/arch/mips32/include/barrier.h (revision e25eca8008c4df6f190fbd28a399c5e01406f863) @@ -46,4 +46,6 @@ #define write_barrier() asm volatile ("" ::: "memory") +#define smc_coherence(a) + #endif Index: kernel/arch/ppc32/include/barrier.h =================================================================== --- kernel/arch/ppc32/include/barrier.h (revision 80dabb8d5cd8827e3f43939b3ce35fcce1382a99) +++ kernel/arch/ppc32/include/barrier.h (revision e25eca8008c4df6f190fbd28a399c5e01406f863) @@ -43,4 +43,6 @@ #define write_barrier() asm volatile ("eieio" ::: "memory") +#define smc_coherence(a) + #endif Index: kernel/arch/ppc64/include/barrier.h =================================================================== --- kernel/arch/ppc64/include/barrier.h (revision 80dabb8d5cd8827e3f43939b3ce35fcce1382a99) +++ kernel/arch/ppc64/include/barrier.h (revision e25eca8008c4df6f190fbd28a399c5e01406f863) @@ -39,7 +39,9 @@ #define CS_LEAVE_BARRIER() asm volatile ("" ::: "memory") -#define memory_barrier() asm volatile ("sync" ::: "memory") -#define read_barrier() asm volatile ("sync" ::: "memory") -#define write_barrier() asm volatile ("eieio" ::: "memory") +#define memory_barrier() asm volatile ("sync" ::: "memory") +#define read_barrier() asm volatile ("sync" ::: "memory") +#define write_barrier() asm volatile ("eieio" ::: "memory") + +#define smc_coherence(a) #endif Index: kernel/arch/sparc64/include/barrier.h =================================================================== --- kernel/arch/sparc64/include/barrier.h (revision 80dabb8d5cd8827e3f43939b3ce35fcce1382a99) +++ kernel/arch/sparc64/include/barrier.h (revision e25eca8008c4df6f190fbd28a399c5e01406f863) @@ -58,6 +58,11 @@ asm volatile ("membar #StoreStore\n" ::: "memory") +static inline void flush(uintptr_t addr) +{ + asm volatile ("flush %0\n" :: "r" (addr) : "memory"); +} + /** Flush Instruction Memory instruction. */ -static inline void flush(void) +static inline void flush_blind(void) { /* @@ -80,4 +85,10 @@ } +#define smc_coherence(a) \ +{ \ + write_barrier(); \ + flush((a)); \ +} + #endif Index: kernel/arch/sparc64/include/mm/cache_spec.h =================================================================== --- kernel/arch/sparc64/include/mm/cache_spec.h (revision e25eca8008c4df6f190fbd28a399c5e01406f863) +++ kernel/arch/sparc64/include/mm/cache_spec.h (revision e25eca8008c4df6f190fbd28a399c5e01406f863) @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2008 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_CACHE_SPEC_H_ +#define KERN_sparc64_CACHE_SPEC_H_ + +/* + * The following macros are valid for the following processors: + * + * UltraSPARC, UltraSPARC II, UltraSPARC IIi + * + * Should we support other UltraSPARC processors, we need to make sure that + * the macros are defined correctly for them. + */ + +#define DCACHE_SIZE (16 * 1024) +#define DCACHE_LINE_SIZE 32 + +#define ICACHE_SIZE (16 * 1024) +#define ICACHE_WAYS 2 +#define ICACHE_LINE_SIZE 32 + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/mm/tlb.h =================================================================== --- kernel/arch/sparc64/include/mm/tlb.h (revision 80dabb8d5cd8827e3f43939b3ce35fcce1382a99) +++ kernel/arch/sparc64/include/mm/tlb.h (revision e25eca8008c4df6f190fbd28a399c5e01406f863) @@ -161,5 +161,5 @@ { asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v); - flush(); + flush_blind(); } @@ -180,5 +180,5 @@ { asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v); - flush(); + flush_blind(); } @@ -210,5 +210,5 @@ reg.tlb_entry = entry; asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); - flush(); + flush_blind(); } @@ -280,5 +280,5 @@ { asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v); - flush(); + flush_blind(); } @@ -319,5 +319,5 @@ { asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v); - flush(); + flush_blind(); } @@ -348,5 +348,5 @@ { asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v); - flush(); + flush_blind(); } @@ -401,5 +401,5 @@ * address within the * ASI */ - flush(); + flush_blind(); } Index: kernel/arch/sparc64/src/mm/cache.S =================================================================== --- kernel/arch/sparc64/src/mm/cache.S (revision 80dabb8d5cd8827e3f43939b3ce35fcce1382a99) +++ kernel/arch/sparc64/src/mm/cache.S (revision e25eca8008c4df6f190fbd28a399c5e01406f863) @@ -28,7 +28,5 @@ #include - -#define DCACHE_SIZE (16 * 1024) -#define DCACHE_LINE_SIZE 32 +#include #define DCACHE_TAG_SHIFT 2