Changeset e25eca80 in mainline for kernel/arch/ia32/include/barrier.h


Ignore:
Timestamp:
2008-06-13T20:36:38Z (17 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
d5087aa
Parents:
80dabb8d
Message:

Add smc_coherence() macro to all architectures.
So far, only amd64, ia32, ia64 and sparc64 are implemented.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • kernel/arch/ia32/include/barrier.h

    r80dabb8d re25eca80  
    8585#endif
    8686
     87/*
     88 * On ia32, the hardware takes care about instruction and data cache coherence,
     89 * even on SMP systems.  We issue a write barrier to be sure that writes
     90 * queueing in the store buffer drain to the memory (even though it would be
     91 * sufficient for them to drain to the D-cache).
     92 */
     93#define smc_coherence(a)                write_barrier()
     94
    8795#endif
    8896
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