Changeset e25eca80 in mainline for kernel/arch/ia32/include/barrier.h
- Timestamp:
- 2008-06-13T20:36:38Z (17 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- d5087aa
- Parents:
- 80dabb8d
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/ia32/include/barrier.h
r80dabb8d re25eca80 85 85 #endif 86 86 87 /* 88 * On ia32, the hardware takes care about instruction and data cache coherence, 89 * even on SMP systems. We issue a write barrier to be sure that writes 90 * queueing in the store buffer drain to the memory (even though it would be 91 * sufficient for them to drain to the D-cache). 92 */ 93 #define smc_coherence(a) write_barrier() 94 87 95 #endif 88 96
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