Changeset e2172284 in mainline
- Timestamp:
- 2018-03-27T06:34:31Z (7 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- bf2042f9
- Parents:
- eb748a0
- git-author:
- Jiri Svoboda <jiri@…> (2018-03-26 22:14:11)
- git-committer:
- Jiri Svoboda <jiri@…> (2018-03-27 06:34:31)
- Location:
- uspace/drv/bus/usb/xhci
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
uspace/drv/bus/usb/xhci/commands.h
reb748a0 re2172284 144 144 extern errno_t xhci_cmd_async_fini(xhci_hc_t *, xhci_cmd_t *); 145 145 146 static inline errno_t xhci_cmd_sync_inline_wrapper(xhci_hc_t *hc, xhci_cmd_t cmd)147 {148 /* Poor man's xhci_cmd_init (everything else is zeroed) */149 link_initialize(&cmd._header.link);150 fibril_mutex_initialize(&cmd._header.completed_mtx);151 fibril_condvar_initialize(&cmd._header.completed_cv);152 153 /* Issue the command */154 const errno_t err = xhci_cmd_sync(hc, &cmd);155 xhci_cmd_fini(&cmd);156 157 return err;158 }159 160 /** The inline macro expects:161 * - hc - HC to schedule command on (xhci_hc_t *).162 * - command - Member of `xhci_cmd_type_t` without the "XHCI_CMD_" prefix.163 * - VA_ARGS - (optional) Command arguments in struct initialization notation.164 *165 * The return code and semantics matches those of `xhci_cmd_sync_fini`.166 *167 * Example:168 * errno_t err = xhci_cmd_sync_inline(hc, DISABLE_SLOT, .slot_id = 42);169 */170 171 #define xhci_cmd_sync_inline(hc, command, ...) \172 xhci_cmd_sync_inline_wrapper(hc, \173 (xhci_cmd_t) { ._header.cmd = XHCI_CMD_##command, ##__VA_ARGS__ })174 175 146 #endif 176 147 -
uspace/drv/bus/usb/xhci/hc.c
reb748a0 re2172284 822 822 errno_t err; 823 823 xhci_hc_t * const hc = bus_to_hc(dev->base.bus); 824 825 if ((err = xhci_cmd_sync_inline(hc, DISABLE_SLOT, .slot_id = dev->slot_id))) { 824 xhci_cmd_t cmd; 825 826 xhci_cmd_init(&cmd, XHCI_CMD_DISABLE_SLOT); 827 cmd.slot_id = dev->slot_id; 828 err = xhci_cmd_sync(hc, &cmd); 829 xhci_cmd_fini(&cmd); 830 if (err != EOK) 826 831 return err; 827 }828 832 829 833 /* Free the device context. */ … … 893 897 894 898 /* Issue Address Device command. */ 895 if ((err = xhci_cmd_sync_inline(hc, ADDRESS_DEVICE, 896 .slot_id = dev->slot_id, 897 .input_ctx = ictx_dma_buf 898 ))) 899 xhci_cmd_t cmd; 900 xhci_cmd_init(&cmd, XHCI_CMD_ADDRESS_DEVICE); 901 cmd.slot_id = dev->slot_id; 902 cmd.input_ctx = ictx_dma_buf; 903 err = xhci_cmd_sync(hc, &cmd); 904 xhci_cmd_fini(&cmd); 905 if (err != EOK) 899 906 return err; 900 907 … … 914 921 { 915 922 xhci_hc_t * const hc = bus_to_hc(dev->base.bus); 923 xhci_cmd_t cmd; 916 924 917 925 /* Issue configure endpoint command (sec 4.3.5). */ 918 926 dma_buffer_t ictx_dma_buf; 919 consterrno_t err = create_configure_ep_input_ctx(dev, &ictx_dma_buf);920 if (err )927 errno_t err = create_configure_ep_input_ctx(dev, &ictx_dma_buf); 928 if (err != EOK) 921 929 return err; 922 930 923 return xhci_cmd_sync_inline(hc, CONFIGURE_ENDPOINT, 924 .slot_id = dev->slot_id, 925 .input_ctx = ictx_dma_buf 926 ); 931 xhci_cmd_init(&cmd, XHCI_CMD_CONFIGURE_ENDPOINT); 932 cmd.slot_id = dev->slot_id; 933 cmd.input_ctx = ictx_dma_buf; 934 err = xhci_cmd_sync(hc, &cmd); 935 xhci_cmd_fini(&cmd); 936 937 return err; 927 938 } 928 939 … … 935 946 { 936 947 xhci_hc_t * const hc = bus_to_hc(dev->base.bus); 948 xhci_cmd_t cmd; 949 errno_t err; 937 950 938 951 if (hc_is_broken(hc)) … … 940 953 941 954 /* Issue configure endpoint command (sec 4.3.5) with the DC flag. */ 942 return xhci_cmd_sync_inline(hc, CONFIGURE_ENDPOINT, 943 .slot_id = dev->slot_id, 944 .deconfigure = true 945 ); 955 xhci_cmd_init(&cmd, XHCI_CMD_CONFIGURE_ENDPOINT); 956 cmd.slot_id = dev->slot_id; 957 cmd.deconfigure = true; 958 959 err = xhci_cmd_sync(hc, &cmd); 960 xhci_cmd_fini(&cmd); 961 962 return err; 946 963 } 947 964 … … 957 974 xhci_device_t * const dev = xhci_ep_to_dev(ep); 958 975 const unsigned dci = endpoint_dci(ep); 976 xhci_cmd_t cmd; 959 977 960 978 /* Issue configure endpoint command (sec 4.3.5). */ 961 979 dma_buffer_t ictx_dma_buf; 962 consterrno_t err = create_configure_ep_input_ctx(dev, &ictx_dma_buf);963 if (err )980 errno_t err = create_configure_ep_input_ctx(dev, &ictx_dma_buf); 981 if (err != EOK) 964 982 return err; 965 983 … … 972 990 xhci_setup_endpoint_context(ep, ep_ctx); 973 991 974 return xhci_cmd_sync_inline(hc, CONFIGURE_ENDPOINT, 975 .slot_id = dev->slot_id, 976 .input_ctx = ictx_dma_buf 977 ); 992 xhci_cmd_init(&cmd, XHCI_CMD_CONFIGURE_ENDPOINT); 993 cmd.slot_id = dev->slot_id; 994 cmd.input_ctx = ictx_dma_buf; 995 err = xhci_cmd_sync(hc, &cmd); 996 xhci_cmd_fini(&cmd); 997 998 return err; 978 999 } 979 1000 … … 989 1010 xhci_hc_t * const hc = bus_to_hc(dev->base.bus); 990 1011 const unsigned dci = endpoint_dci(ep); 1012 xhci_cmd_t cmd; 991 1013 992 1014 if (hc_is_broken(hc)) … … 995 1017 /* Issue configure endpoint command (sec 4.3.5). */ 996 1018 dma_buffer_t ictx_dma_buf; 997 consterrno_t err = create_configure_ep_input_ctx(dev, &ictx_dma_buf);998 if (err )1019 errno_t err = create_configure_ep_input_ctx(dev, &ictx_dma_buf); 1020 if (err != EOK) 999 1021 return err; 1000 1022 … … 1002 1024 XHCI_INPUT_CTRL_CTX_DROP_SET(*XHCI_GET_CTRL_CTX(ictx, hc), dci); 1003 1025 1004 return xhci_cmd_sync_inline(hc, CONFIGURE_ENDPOINT, 1005 .slot_id = dev->slot_id, 1006 .input_ctx = ictx_dma_buf 1007 ); 1026 xhci_cmd_init(&cmd, XHCI_CMD_CONFIGURE_ENDPOINT); 1027 cmd.slot_id = dev->slot_id; 1028 cmd.input_ctx = ictx_dma_buf; 1029 err = xhci_cmd_sync(hc, &cmd); 1030 xhci_cmd_fini(&cmd); 1031 1032 return err; 1008 1033 } 1009 1034 … … 1020 1045 xhci_device_t * const dev = xhci_ep_to_dev(ep); 1021 1046 const unsigned dci = endpoint_dci(ep); 1047 xhci_cmd_t cmd; 1022 1048 1023 1049 dma_buffer_t ictx_dma_buf; 1024 1050 xhci_hc_t * const hc = bus_to_hc(dev->base.bus); 1025 1051 1026 consterrno_t err = dma_buffer_alloc(&ictx_dma_buf, XHCI_INPUT_CTX_SIZE(hc));1027 if (err )1052 errno_t err = dma_buffer_alloc(&ictx_dma_buf, XHCI_INPUT_CTX_SIZE(hc)); 1053 if (err != EOK) 1028 1054 return err; 1029 1055 … … 1035 1061 xhci_setup_endpoint_context(ep, ep_ctx); 1036 1062 1037 return xhci_cmd_sync_inline(hc, EVALUATE_CONTEXT, 1038 .slot_id = dev->slot_id, 1039 .input_ctx = ictx_dma_buf 1040 ); 1063 xhci_cmd_init(&cmd, XHCI_CMD_EVALUATE_CONTEXT); 1064 cmd.slot_id = dev->slot_id; 1065 cmd.input_ctx = ictx_dma_buf; 1066 err = xhci_cmd_sync(hc, &cmd); 1067 xhci_cmd_fini(&cmd); 1068 1069 return err; 1041 1070 } 1042 1071 … … 1052 1081 const unsigned dci = endpoint_dci(ep); 1053 1082 xhci_hc_t * const hc = bus_to_hc(dev->base.bus); 1083 xhci_cmd_t cmd; 1084 errno_t err; 1054 1085 1055 1086 if (hc_is_broken(hc)) 1056 1087 return EOK; 1057 1088 1058 return xhci_cmd_sync_inline(hc, STOP_ENDPOINT, 1059 .slot_id = dev->slot_id, 1060 .endpoint_id = dci 1061 ); 1089 xhci_cmd_init(&cmd, XHCI_CMD_STOP_ENDPOINT); 1090 cmd.slot_id = dev->slot_id; 1091 cmd.endpoint_id = dci; 1092 err = xhci_cmd_sync(hc, &cmd); 1093 xhci_cmd_fini(&cmd); 1094 1095 return err; 1062 1096 } 1063 1097 … … 1073 1107 const unsigned dci = endpoint_dci(ep); 1074 1108 xhci_hc_t * const hc = bus_to_hc(dev->base.bus); 1075 return xhci_cmd_sync_inline(hc, RESET_ENDPOINT, 1076 .slot_id = dev->slot_id, 1077 .endpoint_id = dci 1078 ); 1109 xhci_cmd_t cmd; 1110 errno_t err; 1111 1112 xhci_cmd_init(&cmd, XHCI_CMD_RESET_ENDPOINT); 1113 cmd.slot_id = dev->slot_id; 1114 cmd.endpoint_id = dci; 1115 err = xhci_cmd_sync(hc, &cmd); 1116 xhci_cmd_fini(&cmd); 1117 1118 return err; 1079 1119 } 1080 1120 … … 1089 1129 const unsigned dci = endpoint_dci(ep); 1090 1130 uintptr_t addr; 1131 xhci_cmd_t cmd; 1132 errno_t err; 1091 1133 1092 1134 xhci_trb_ring_t *ring = xhci_endpoint_get_ring(ep, stream_id); … … 1094 1136 1095 1137 xhci_hc_t * const hc = bus_to_hc(endpoint_get_bus(&ep->base)); 1096 return xhci_cmd_sync_inline(hc, SET_TR_DEQUEUE_POINTER, 1097 .slot_id = dev->slot_id, 1098 .endpoint_id = dci, 1099 .stream_id = stream_id, 1100 .dequeue_ptr = addr, 1101 ); 1138 1139 xhci_cmd_init(&cmd, XHCI_CMD_SET_TR_DEQUEUE_POINTER); 1140 cmd.slot_id = dev->slot_id; 1141 cmd.endpoint_id = dci; 1142 cmd.stream_id = stream_id; 1143 cmd.dequeue_ptr = addr; 1144 err = xhci_cmd_sync(hc, &cmd); 1145 xhci_cmd_fini(&cmd); 1146 1147 return err; 1102 1148 } 1103 1149
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