Index: HelenOS.config =================================================================== --- HelenOS.config (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ HelenOS.config (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -65,4 +65,5 @@ @ "testarm" GXEmul Testarm @ "integratorcp" Integratorcp +@ "beagleboardxm" BeogleBoard-xM ! [PLATFORM=arm32] MACHINE (choice) @@ -86,4 +87,17 @@ ! [PLATFORM=sparc64&MACHINE=generic] PROCESSOR (choice) +% CPU type +@ "armv4" ARMv4 +! [PLATFORM=arm32&(MACHINE=gta02|MACHINE=testarm)] PROCESSOR (choice) + +% CPU type +@ "armv5" ARMv5 +! [PLATFORM=arm32&MACHINE=integratorcp] PROCESSOR (choice) + +% CPU type +@ "armv7_a" ARMv7-A +! [PLATFORM=arm32&MACHINE=beagleboardxm] PROCESSOR (choice) + + % RAM disk format @ "tmpfs" TMPFS image @@ -406,5 +420,5 @@ % Output device class @ "generic" Monitor or serial line -! [PLATFORM=arm32&(MACHINE=gta02|MACHINE=integratorcp)] CONFIG_HID_OUT (choice) +! [PLATFORM=arm32&(MACHINE=gta02|MACHINE=integratorcp|MACHINE=beagleboardxm)] CONFIG_HID_OUT (choice) % Output device class @@ -466,4 +480,7 @@ ! [PLATFORM=arm32&MACHINE=gta02] CONFIG_S3C24XX_IRQC (y) +% Support for TI AMDM37X on-chip UART +! [(CONFIG_HID_OUT=generic|CONFIG_HID_OUT=serial)&PLATFORM=arm32&MACHINE=beagleboardxm] CONFIG_AMDM37X_UART (y/n) + % Support for i8042 controller ! [CONFIG_PC_KBD=y] CONFIG_I8042 (y) @@ -485,5 +502,5 @@ % Serial line input module -! [CONFIG_DSRLNIN=y|(PLATFORM=arm32&MACHINE=gta02)|(PLATFORM=arm32&MACHINE=integratorcp&CONFIG_ARM926_UART=y)|(PLATFORM=ia64&MACHINE=i460GX&CONFIG_NS16550=y)|(PLATFORM=ia64&MACHINE=ski)|(PLATFORM=sparc64&PROCESSOR=sun4v)] CONFIG_SRLN (y) +! [CONFIG_DSRLNIN=y|(PLATFORM=arm32&MACHINE=gta02)|(PLATFORM=arm32&MACHINE=integratorcp&CONFIG_ARM926_UART=y)|(PLATFORM=arm32&MACHINE=beagleboardxm&CONFIG_AMDM37X_UART=y)|(PLATFORM=ia64&MACHINE=i460GX&CONFIG_NS16550=y)|(PLATFORM=ia64&MACHINE=ski)|(PLATFORM=sparc64&PROCESSOR=sun4v)] CONFIG_SRLN (y) % EGA support @@ -521,5 +538,5 @@ @ "1920x1080" @ "1920x1200" -! [(PLATFORM=ia32|PLATFORM=amd64)&CONFIG_HID_OUT!=none&CONFIG_FB=y] CONFIG_BFB_MODE (choice) +! [(PLATFORM=ia32|PLATFORM=amd64|MACHINE=beagleboardxm)&CONFIG_HID_OUT!=none&CONFIG_FB=y] CONFIG_BFB_MODE (choice) % Default framebuffer depth @@ -527,5 +544,5 @@ @ "16" @ "24" -! [(PLATFORM=ia32|PLATFORM=amd64)&CONFIG_HID_OUT!=none&CONFIG_FB=y] CONFIG_BFB_BPP (choice) +! [(PLATFORM=ia32|PLATFORM=amd64|MACHINE=beagleboardxm)&CONFIG_HID_OUT!=none&CONFIG_FB=y] CONFIG_BFB_BPP (choice) % Start AP processors by the loader @@ -595,2 +612,10 @@ @ "efi" GRUB for UEFI ! [PLATFORM=ia32|PLATFORM=amd64] GRUB_ARCH (choice) + +% uImage OS type +@ "2" NetBSD stage 2 boot loader +! [PLATFORM=arm32&MACHINE=beagleboardxm] UIMAGE_OS (choice) + +% uImage OS type +@ "5" Linux kernel +! [PLATFORM=arm32&MACHINE!=beagleboardxm] UIMAGE_OS (choice) Index: abi/include/mm/as.h =================================================================== --- abi/include/mm/as.h (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ abi/include/mm/as.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -37,9 +37,10 @@ /** Address space area flags. */ -#define AS_AREA_READ 0x01 -#define AS_AREA_WRITE 0x02 -#define AS_AREA_EXEC 0x04 -#define AS_AREA_CACHEABLE 0x08 -#define AS_AREA_GUARD 0x10 +#define AS_AREA_READ 0x01 +#define AS_AREA_WRITE 0x02 +#define AS_AREA_EXEC 0x04 +#define AS_AREA_CACHEABLE 0x08 +#define AS_AREA_GUARD 0x10 +#define AS_AREA_LATE_RESERVE 0x20 /** Address space area info exported to uspace. */ Index: boot/Makefile.uboot =================================================================== --- boot/Makefile.uboot (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ boot/Makefile.uboot (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -40,5 +40,5 @@ $(POST_OUTPUT): $(BIN_OUTPUT) - $(MKUIMAGE) -name "$(IMAGE_NAME)" -laddr 0x30008000 -saddr 0x30008000 $< $@ + $(MKUIMAGE) -name "$(IMAGE_NAME)" -laddr $(LADDR) -saddr $(SADDR) -ostype $(UIMAGE_OS) $< $@ clean: Index: boot/arch/arm32/Makefile.inc =================================================================== --- boot/arch/arm32/Makefile.inc (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ boot/arch/arm32/Makefile.inc (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -30,4 +30,14 @@ BOOT_OUTPUT = image.boot POST_OUTPUT = $(ROOT_PATH)/uImage.bin + LADDR = 0x30008000 + SADDR = 0x30008000 + POSTBUILD = Makefile.uboot +endif + +ifeq ($(MACHINE), beagleboardxm) + BOOT_OUTPUT = image.boot + POST_OUTPUT = $(ROOT_PATH)/uImage.bin + LADDR = 0x80000000 + SADDR = 0x80000000 POSTBUILD = Makefile.uboot endif @@ -39,12 +49,26 @@ BITS = 32 ENDIANESS = LE -EXTRA_CFLAGS = -march=armv4 +EXTRA_CFLAGS = -march=$(subst _,-,$(PROCESSOR)) -mno-unaligned-access +ifeq ($(MACHINE), gta02) RD_SRVS_ESSENTIAL += \ $(USPACE_PATH)/srv/hid/s3c24xx_ts/s3c24xx_ts \ $(USPACE_PATH)/srv/hw/char/s3c24xx_uart/s3c24xx_uart +endif +ifeq ($(MACHINE), gxemul) RD_SRVS_NON_ESSENTIAL += \ $(USPACE_PATH)/srv/bd/gxe_bd/gxe_bd +endif + +RD_DRVS += \ + infrastructure/rootamdm37x \ + bus/usb/ehci \ + bus/usb/ohci \ + bus/usb/usbflbk \ + bus/usb/usbhub \ + bus/usb/usbhid \ + bus/usb/usbmast \ + bus/usb/usbmid SOURCES = \ Index: boot/arch/arm32/include/arch.h =================================================================== --- boot/arch/arm32/include/arch.h (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ boot/arch/arm32/include/arch.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -42,4 +42,6 @@ #ifdef MACHINE_gta02 #define BOOT_BASE 0x30008000 +#elif defined MACHINE_beagleboardxm +#define BOOT_BASE 0x80000000 #else #define BOOT_BASE 0x00000000 @@ -48,9 +50,16 @@ #define BOOT_OFFSET (BOOT_BASE + 0xa00000) +#ifdef MACHINE_beagleboardxm + #define PA_OFFSET 0 +#else + #define PA_OFFSET 0x80000000 +#endif + #ifndef __ASM__ - #define PA2KA(addr) (((uintptr_t) (addr)) + 0x80000000) + #define PA2KA(addr) (((uintptr_t) (addr)) + PA_OFFSET) #else - #define PA2KA(addr) ((addr) + 0x80000000) + #define PA2KA(addr) ((addr) + PA_OFFSET) #endif + #endif Index: boot/arch/arm32/include/main.h =================================================================== --- boot/arch/arm32/include/main.h (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ boot/arch/arm32/include/main.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -40,4 +40,16 @@ /** Address where characters to be printed are expected. */ + +/** BeagleBoard-xM UART register address + * + * This is UART3 of AM/DM37x CPU + */ +#define BBXM_SCONS_THR 0x49020000 +#define BBXM_SCONS_SSR 0x49020044 + +/* Check this bit before writing (tx fifo full) */ +#define BBXM_THR_FULL 0x00000001 + + /** GTA02 serial console UART register addresses. * Index: boot/arch/arm32/include/mm.h =================================================================== --- boot/arch/arm32/include/mm.h (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ boot/arch/arm32/include/mm.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -58,9 +58,13 @@ unsigned int bufferable : 1; unsigned int cacheable : 1; - unsigned int impl_specific : 1; + unsigned int xn : 1; unsigned int domain : 4; unsigned int should_be_zero_1 : 1; - unsigned int access_permission : 2; - unsigned int should_be_zero_2 : 8; + unsigned int access_permission_0 : 2; + unsigned int tex : 3; + unsigned int access_permission_1 : 2; + unsigned int non_global : 1; + unsigned int should_be_zero_2 : 1; + unsigned int non_secure : 1; unsigned int section_base_addr : 12; } __attribute__((packed)) pte_level0_section_t; Index: boot/arch/arm32/src/mm.c =================================================================== --- boot/arch/arm32/src/mm.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ boot/arch/arm32/src/mm.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -54,11 +54,15 @@ { pte->descriptor_type = PTE_DESCRIPTOR_SECTION; - pte->bufferable = 0; + pte->bufferable = 1; pte->cacheable = 0; - pte->impl_specific = 0; + pte->xn = 0; pte->domain = 0; pte->should_be_zero_1 = 0; - pte->access_permission = PTE_AP_USER_NO_KERNEL_RW; + pte->access_permission_0 = PTE_AP_USER_NO_KERNEL_RW; + pte->tex = 0; + pte->access_permission_1 = 0; + pte->non_global = 0; pte->should_be_zero_2 = 0; + pte->non_secure = 0; pte->section_base_addr = frame; } @@ -67,6 +71,5 @@ static void init_boot_pt(void) { - pfn_t split_page = 0x800; - + const pfn_t split_page = PTL0_ENTRIES; /* Create 1:1 virtual-physical mapping (in lower 2 GB). */ pfn_t page; @@ -78,6 +81,13 @@ * (upper 2 GB), physical addresses start from 0. */ + /* BeagleBoard-xM (DM37x) memory starts at 2GB border, + * thus mapping only lower 2GB is not not enough. + * Map entire AS 1:1 instead and hope it works. */ for (page = split_page; page < PTL0_ENTRIES; page++) +#ifndef MACHINE_beagleboardxm init_ptl0_section(&boot_pt[page], page - split_page); +#else + init_ptl0_section(&boot_pt[page], page); +#endif asm volatile ( @@ -95,11 +105,25 @@ /* Behave as a client of domains */ "ldr r0, =0x55555555\n" - "mcr p15, 0, r0, c3, c0, 0\n" + "mcr p15, 0, r0, c3, c0, 0\n" +#ifdef PROCESSOR_armv7_a + /* Read Auxiliary control register */ + "mrc p15, 0, r0, c1, c0, 1\n" + /* Mask to enable L2 cache */ + "ldr r1, =0x00000002\n" + "orr r0, r0, r1\n" + /* Store Auxiliary control register */ + "mrc p15, 0, r0, c1, c0, 1\n" +#endif /* Current settings */ "mrc p15, 0, r0, c1, c0, 0\n" +#ifdef PROCESSOR_armv7_a + /* Mask to enable paging, caching */ + "ldr r1, =0x00000005\n" +#else /* Mask to enable paging */ "ldr r1, =0x00000001\n" +#endif "orr r0, r0, r1\n" Index: boot/arch/arm32/src/putchar.c =================================================================== --- boot/arch/arm32/src/putchar.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ boot/arch/arm32/src/putchar.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -40,4 +40,26 @@ #include #include + +#ifdef MACHINE_beagleboardxm + +/** Send a byte to the amdm37x serial console. + * + * @param byte Byte to send. + */ +static void scons_sendb_bbxm(uint8_t byte) +{ + volatile uint32_t *thr = + (volatile uint32_t *)BBXM_SCONS_THR; + volatile uint32_t *ssr = + (volatile uint32_t *)BBXM_SCONS_SSR; + + /* Wait until transmitter is empty. */ + while ((*ssr & BBXM_THR_FULL) == 1) ; + + /* Transmit byte. */ + *thr = (uint32_t) byte; +} + +#endif #ifdef MACHINE_gta02 @@ -97,4 +119,7 @@ static void scons_sendb(uint8_t byte) { +#ifdef MACHINE_beagleboardxm + scons_sendb_bbxm(byte); +#endif #ifdef MACHINE_gta02 scons_sendb_gta02(byte); Index: boot/arch/ia64/src/main.c =================================================================== --- boot/arch/ia64/src/main.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ boot/arch/ia64/src/main.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -48,5 +48,5 @@ #define DEFAULT_MEMORY_BASE 0x4000000ULL -#define DEFAULT_MEMORY_SIZE 0x4000000ULL +#define DEFAULT_MEMORY_SIZE (256 * 1024 * 1024) #define DEFAULT_LEGACY_IO_BASE 0x00000FFFFC000000ULL #define DEFAULT_LEGACY_IO_SIZE 0x4000000ULL Index: contrib/conf/ski.conf =================================================================== --- contrib/conf/ski.conf (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ contrib/conf/ski.conf (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -1,1 +1,1 @@ -load HelenOS/image.boot +load image.boot Index: defaults/arm32/beagleboardxm/Makefile.config =================================================================== --- defaults/arm32/beagleboardxm/Makefile.config (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) +++ defaults/arm32/beagleboardxm/Makefile.config (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -0,0 +1,11 @@ +# Machine type +MACHINE = beagleboardxm + +# RAM disk format +RDFMT = fat + +#framebuffer +CONFIG_FB = y + +CONFIG_BFB_MODE = 1024x768 +CONFIG_BFB_BPP = 24 Index: defaults/arm32/gta02/Makefile.config =================================================================== --- defaults/arm32/gta02/Makefile.config (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ defaults/arm32/gta02/Makefile.config (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -3,3 +3,3 @@ # RAM disk format -RDFMT = tmpfs +RDFMT = fat Index: kernel/arch/amd64/src/mm/page.c =================================================================== --- kernel/arch/amd64/src/mm/page.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ kernel/arch/amd64/src/mm/page.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -92,8 +92,5 @@ access = PF_ACCESS_READ; - if (as_page_fault(page, access, istate) == AS_PF_FAULT) { - fault_if_from_uspace(istate, "Page fault: %p.", (void *) page); - panic_memtrap(istate, access, page, NULL); - } + as_page_fault(page, access, istate); } Index: kernel/arch/arm32/Makefile.inc =================================================================== --- kernel/arch/arm32/Makefile.inc (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ kernel/arch/arm32/Makefile.inc (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -33,5 +33,5 @@ ATSIGN = % -GCC_CFLAGS += -march=armv4 -fno-omit-frame-pointer -mapcs-frame +GCC_CFLAGS += -fno-omit-frame-pointer -mapcs-frame -march=$(subst _,-,$(PROCESSOR)) -mno-unaligned-access BITS = 32 @@ -74,4 +74,8 @@ endif +ifeq ($(MACHINE),beagleboardxm) + ARCH_SOURCES += arch/$(KARCH)/src/mach/beagleboardxm/beagleboardxm.c +endif + ifeq ($(CONFIG_PL050),y) ARCH_SOURCES += genarch/src/drivers/pl050/pl050.c Index: kernel/arch/arm32/_link.ld.in =================================================================== --- kernel/arch/arm32/_link.ld.in (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ kernel/arch/arm32/_link.ld.in (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -9,4 +9,6 @@ #ifdef MACHINE_gta02 #define KERNEL_LOAD_ADDRESS 0xb0a08000 +#elif defined MACHINE_beagleboardxm +#define KERNEL_LOAD_ADDRESS 0x80a00000 #else #define KERNEL_LOAD_ADDRESS 0x80a00000 Index: kernel/arch/arm32/include/asm.h =================================================================== --- kernel/arch/arm32/include/asm.h (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ kernel/arch/arm32/include/asm.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -43,7 +43,17 @@ #include -/** No such instruction on ARM to sleep CPU. */ +/** No such instruction on old ARM to sleep CPU. + * + * ARMv7 introduced wait for event and wait for interrupt (wfe/wfi). + * ARM920T has custom coprocessor action to do the same. See ARM920T Technical + * Reference Manual ch 4.9 p. 4-23 (103 in the PDF) + */ NO_TRACE static inline void cpu_sleep(void) { +#ifdef PROCESSOR_armv7_a + asm volatile ( "wfe" :: ); +#elif defined(MACHINE_gta02) + asm volatile ( "mcr p15,0,R0,c7,c0,4" :: ); +#endif } Index: kernel/arch/arm32/include/barrier.h =================================================================== --- kernel/arch/arm32/include/barrier.h (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ kernel/arch/arm32/include/barrier.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -47,6 +47,24 @@ #define write_barrier() asm volatile ("" ::: "memory") -#define smc_coherence(a) -#define smc_coherence_block(a, l) +/* + * There are multiple ways ICache can be implemented on ARM machines. Namely + * PIPT, VIPT, and ASID and VMID tagged VIVT (see ARM Architecture Reference + * Manual B3.11.2 (p. 1383). However, CortexA8 Manual states: "For maximum + * compatibility across processors, ARM recommends that operating systems target + * the ARMv7 base architecture that uses ASID-tagged VIVT instruction caches, + * and do not assume the presence of the IVIPT extension. Software that relies + * on the IVIPT extension might fail in an unpredictable way on an ARMv7 + * implementation that does not include the IVIPT extension." (7.2.6 p. 245). + * Only PIPT invalidates cache for all VA aliases if one block is invalidated. + * + * @note: Supporting ASID and VMID tagged VIVT may need to add ICache + * maintenance to other places than just smc. + */ + +/* Available on both all supported arms, + * invalidates entire ICache so the written value does not matter. */ +#define smc_coherence(a) asm volatile ( "mcr p15, 0, r0, c7, c5, 0") +#define smc_coherence_block(a, l) smc_coherence(a) + #endif Index: kernel/arch/arm32/include/cpu.h =================================================================== --- kernel/arch/arm32/include/cpu.h (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ kernel/arch/arm32/include/cpu.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -41,5 +41,5 @@ -/** Struct representing ARM CPU identifiaction. */ +/** Struct representing ARM CPU identification. */ typedef struct { /** Implementator (vendor) number. */ Index: kernel/arch/arm32/include/mach/beagleboardxm/beagleboardxm.h =================================================================== --- kernel/arch/arm32/include/mach/beagleboardxm/beagleboardxm.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) +++ kernel/arch/arm32/include/mach/beagleboardxm/beagleboardxm.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** @addtogroup arm32beagleboardxm beagleboardxm + * @brief BeagleBoard-xM platform. + * @ingroup arm32 + * @{ + */ +/** @file + * @brief BeagleBoard platform driver. + */ + +#ifndef KERN_arm32_beagleboardxm_H_ +#define KERN_arm32_beagleboardxm_H_ + +#include + +extern struct arm_machine_ops bbxm_machine_ops; + +#endif + +/** @} + */ + Index: kernel/arch/arm32/include/machine_func.h =================================================================== --- kernel/arch/arm32/include/machine_func.h (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ kernel/arch/arm32/include/machine_func.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -108,4 +108,6 @@ extern size_t machine_get_irq_count(void); +extern const char * machine_get_platform_name(void); + #endif Index: kernel/arch/arm32/include/mm/frame.h =================================================================== --- kernel/arch/arm32/include/mm/frame.h (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ kernel/arch/arm32/include/mm/frame.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -48,4 +48,6 @@ #ifdef MACHINE_gta02 #define BOOT_PAGE_TABLE_ADDRESS 0x30010000 +#elif defined MACHINE_beagleboardxm +#define BOOT_PAGE_TABLE_ADDRESS 0x80008000 #else #define BOOT_PAGE_TABLE_ADDRESS 0x00008000 @@ -57,4 +59,6 @@ #ifdef MACHINE_gta02 #define PHYSMEM_START_ADDR 0x30008000 +#elif defined MACHINE_beagleboardxm +#define PHYSMEM_START_ADDR 0x80000000 #else #define PHYSMEM_START_ADDR 0x00000000 Index: kernel/arch/arm32/include/mm/page.h =================================================================== --- kernel/arch/arm32/include/mm/page.h (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ kernel/arch/arm32/include/mm/page.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -46,4 +46,13 @@ #define PAGE_SIZE FRAME_SIZE +#ifdef MACHINE_beagleboardxm +#ifndef __ASM__ +# define KA2PA(x) ((uintptr_t) (x)) +# define PA2KA(x) ((uintptr_t) (x)) +#else +# define KA2PA(x) (x) +# define PA2KA(x) (x) +#endif +#else #ifndef __ASM__ # define KA2PA(x) (((uintptr_t) (x)) - 0x80000000) @@ -53,57 +62,58 @@ # define PA2KA(x) ((x) + 0x80000000) #endif +#endif /* Number of entries in each level. */ -#define PTL0_ENTRIES_ARCH (1 << 12) /* 4096 */ -#define PTL1_ENTRIES_ARCH 0 -#define PTL2_ENTRIES_ARCH 0 +#define PTL0_ENTRIES_ARCH (1 << 12) /* 4096 */ +#define PTL1_ENTRIES_ARCH 0 +#define PTL2_ENTRIES_ARCH 0 /* coarse page tables used (256 * 4 = 1KB per page) */ -#define PTL3_ENTRIES_ARCH (1 << 8) /* 256 */ +#define PTL3_ENTRIES_ARCH (1 << 8) /* 256 */ /* Page table sizes for each level. */ -#define PTL0_SIZE_ARCH FOUR_FRAMES -#define PTL1_SIZE_ARCH 0 -#define PTL2_SIZE_ARCH 0 -#define PTL3_SIZE_ARCH ONE_FRAME +#define PTL0_SIZE_ARCH FOUR_FRAMES +#define PTL1_SIZE_ARCH 0 +#define PTL2_SIZE_ARCH 0 +#define PTL3_SIZE_ARCH ONE_FRAME /* Macros calculating indices into page tables for each level. */ -#define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 20) & 0xfff) -#define PTL1_INDEX_ARCH(vaddr) 0 -#define PTL2_INDEX_ARCH(vaddr) 0 -#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x0ff) +#define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 20) & 0xfff) +#define PTL1_INDEX_ARCH(vaddr) 0 +#define PTL2_INDEX_ARCH(vaddr) 0 +#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x0ff) /* Get PTE address accessors for each level. */ #define GET_PTL1_ADDRESS_ARCH(ptl0, i) \ - ((pte_t *) ((((pte_t *)(ptl0))[(i)].l0).coarse_table_addr << 10)) + ((pte_t *) ((((pte_t *)(ptl0))[(i)].l0).coarse_table_addr << 10)) #define GET_PTL2_ADDRESS_ARCH(ptl1, i) \ - (ptl1) + (ptl1) #define GET_PTL3_ADDRESS_ARCH(ptl2, i) \ - (ptl2) + (ptl2) #define GET_FRAME_ADDRESS_ARCH(ptl3, i) \ - ((uintptr_t) ((((pte_t *)(ptl3))[(i)].l1).frame_base_addr << 12)) + ((uintptr_t) ((((pte_t *)(ptl3))[(i)].l1).frame_base_addr << 12)) /* Set PTE address accessors for each level. */ #define SET_PTL0_ADDRESS_ARCH(ptl0) \ - (set_ptl0_addr((pte_t *) (ptl0))) + (set_ptl0_addr((pte_t *) (ptl0))) #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \ - (((pte_t *) (ptl0))[(i)].l0.coarse_table_addr = (a) >> 10) + (((pte_t *) (ptl0))[(i)].l0.coarse_table_addr = (a) >> 10) #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \ - (((pte_t *) (ptl3))[(i)].l1.frame_base_addr = (a) >> 12) + (((pte_t *) (ptl3))[(i)].l1.frame_base_addr = (a) >> 12) /* Get PTE flags accessors for each level. */ #define GET_PTL1_FLAGS_ARCH(ptl0, i) \ - get_pt_level0_flags((pte_t *) (ptl0), (size_t) (i)) + get_pt_level0_flags((pte_t *) (ptl0), (size_t) (i)) #define GET_PTL2_FLAGS_ARCH(ptl1, i) \ - PAGE_PRESENT + PAGE_PRESENT #define GET_PTL3_FLAGS_ARCH(ptl2, i) \ - PAGE_PRESENT + PAGE_PRESENT #define GET_FRAME_FLAGS_ARCH(ptl3, i) \ - get_pt_level1_flags((pte_t *) (ptl3), (size_t) (i)) + get_pt_level1_flags((pte_t *) (ptl3), (size_t) (i)) /* Set PTE flags accessors for each level. */ #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \ - set_pt_level0_flags((pte_t *) (ptl0), (size_t) (i), (x)) + set_pt_level0_flags((pte_t *) (ptl0), (size_t) (i), (x)) #define SET_PTL2_FLAGS_ARCH(ptl1, i, x) #define SET_PTL3_FLAGS_ARCH(ptl2, i, x) @@ -119,221 +129,11 @@ set_pt_level1_present((pte_t *) (ptl3), (size_t) (i)) -/* Macros for querying the last-level PTE entries. */ -#define PTE_VALID_ARCH(pte) \ - (*((uint32_t *) (pte)) != 0) -#define PTE_PRESENT_ARCH(pte) \ - (((pte_t *) (pte))->l0.descriptor_type != 0) -#define PTE_GET_FRAME_ARCH(pte) \ - (((pte_t *) (pte))->l1.frame_base_addr << FRAME_WIDTH) -#define PTE_WRITABLE_ARCH(pte) \ - (((pte_t *) (pte))->l1.access_permission_0 == PTE_AP_USER_RW_KERNEL_RW) -#define PTE_EXECUTABLE_ARCH(pte) \ - 1 - -#ifndef __ASM__ - -/** Level 0 page table entry. */ -typedef struct { - /* 0b01 for coarse tables, see below for details */ - unsigned descriptor_type : 2; - unsigned impl_specific : 3; - unsigned domain : 4; - unsigned should_be_zero : 1; - - /* Pointer to the coarse 2nd level page table (holding entries for small - * (4KB) or large (64KB) pages. ARM also supports fine 2nd level page - * tables that may hold even tiny pages (1KB) but they are bigger (4KB - * per table in comparison with 1KB per the coarse table) - */ - unsigned coarse_table_addr : 22; -} ATTRIBUTE_PACKED pte_level0_t; - -/** Level 1 page table entry (small (4KB) pages used). */ -typedef struct { - - /* 0b10 for small pages */ - unsigned descriptor_type : 2; - unsigned bufferable : 1; - unsigned cacheable : 1; - - /* access permissions for each of 4 subparts of a page - * (for each 1KB when small pages used */ - unsigned access_permission_0 : 2; - unsigned access_permission_1 : 2; - unsigned access_permission_2 : 2; - unsigned access_permission_3 : 2; - unsigned frame_base_addr : 20; -} ATTRIBUTE_PACKED pte_level1_t; - -typedef union { - pte_level0_t l0; - pte_level1_t l1; -} pte_t; - -/* Level 1 page tables access permissions */ - -/** User mode: no access, privileged mode: no access. */ -#define PTE_AP_USER_NO_KERNEL_NO 0 - -/** User mode: no access, privileged mode: read/write. */ -#define PTE_AP_USER_NO_KERNEL_RW 1 - -/** User mode: read only, privileged mode: read/write. */ -#define PTE_AP_USER_RO_KERNEL_RW 2 - -/** User mode: read/write, privileged mode: read/write. */ -#define PTE_AP_USER_RW_KERNEL_RW 3 - - -/* pte_level0_t and pte_level1_t descriptor_type flags */ - -/** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type). */ -#define PTE_DESCRIPTOR_NOT_PRESENT 0 - -/** pte_level0_t coarse page table flag (used in descriptor_type). */ -#define PTE_DESCRIPTOR_COARSE_TABLE 1 - -/** pte_level1_t small page table flag (used in descriptor type). */ -#define PTE_DESCRIPTOR_SMALL_PAGE 2 - - -/** Sets the address of level 0 page table. - * - * @param pt Pointer to the page table to set. - * - */ -NO_TRACE static inline void set_ptl0_addr(pte_t *pt) -{ - asm volatile ( - "mcr p15, 0, %[pt], c2, c0, 0\n" - :: [pt] "r" (pt) - ); -} - - -/** Returns level 0 page table entry flags. - * - * @param pt Level 0 page table. - * @param i Index of the entry to return. - * - */ -NO_TRACE static inline int get_pt_level0_flags(pte_t *pt, size_t i) -{ - pte_level0_t *p = &pt[i].l0; - int np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT); - - return (np << PAGE_PRESENT_SHIFT) | (1 << PAGE_USER_SHIFT) | - (1 << PAGE_READ_SHIFT) | (1 << PAGE_WRITE_SHIFT) | - (1 << PAGE_EXEC_SHIFT) | (1 << PAGE_CACHEABLE_SHIFT); -} - -/** Returns level 1 page table entry flags. - * - * @param pt Level 1 page table. - * @param i Index of the entry to return. - * - */ -NO_TRACE static inline int get_pt_level1_flags(pte_t *pt, size_t i) -{ - pte_level1_t *p = &pt[i].l1; - - int dt = p->descriptor_type; - int ap = p->access_permission_0; - - return ((dt == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) | - ((ap == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT) | - ((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_READ_SHIFT) | - ((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_WRITE_SHIFT) | - ((ap != PTE_AP_USER_NO_KERNEL_RW) << PAGE_USER_SHIFT) | - ((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_READ_SHIFT) | - ((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_WRITE_SHIFT) | - (1 << PAGE_EXEC_SHIFT) | - (p->bufferable << PAGE_CACHEABLE); -} - -/** Sets flags of level 0 page table entry. - * - * @param pt level 0 page table - * @param i index of the entry to be changed - * @param flags new flags - * - */ -NO_TRACE static inline void set_pt_level0_flags(pte_t *pt, size_t i, int flags) -{ - pte_level0_t *p = &pt[i].l0; - - if (flags & PAGE_NOT_PRESENT) { - p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; - /* - * Ensures that the entry will be recognized as valid when - * PTE_VALID_ARCH applied. - */ - p->should_be_zero = 1; - } else { - p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE; - p->should_be_zero = 0; - } -} - -NO_TRACE static inline void set_pt_level0_present(pte_t *pt, size_t i) -{ - pte_level0_t *p = &pt[i].l0; - - p->should_be_zero = 0; - write_barrier(); - p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE; -} - -/** Sets flags of level 1 page table entry. - * - * We use same access rights for the whole page. When page - * is not preset we store 1 in acess_rigts_3 so that at least - * one bit is 1 (to mark correct page entry, see #PAGE_VALID_ARCH). - * - * @param pt Level 1 page table. - * @param i Index of the entry to be changed. - * @param flags New flags. - * - */ -NO_TRACE static inline void set_pt_level1_flags(pte_t *pt, size_t i, int flags) -{ - pte_level1_t *p = &pt[i].l1; - - if (flags & PAGE_NOT_PRESENT) - p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; - else - p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE; - - p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0; - - /* default access permission */ - p->access_permission_0 = p->access_permission_1 = - p->access_permission_2 = p->access_permission_3 = - PTE_AP_USER_NO_KERNEL_RW; - - if (flags & PAGE_USER) { - if (flags & PAGE_READ) { - p->access_permission_0 = p->access_permission_1 = - p->access_permission_2 = p->access_permission_3 = - PTE_AP_USER_RO_KERNEL_RW; - } - if (flags & PAGE_WRITE) { - p->access_permission_0 = p->access_permission_1 = - p->access_permission_2 = p->access_permission_3 = - PTE_AP_USER_RW_KERNEL_RW; - } - } -} - -NO_TRACE static inline void set_pt_level1_present(pte_t *pt, size_t i) -{ - pte_level1_t *p = &pt[i].l1; - - p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE; -} - -extern void page_arch_init(void); - -#endif /* __ASM__ */ +#if defined(PROCESSOR_armv6) | defined(PROCESSOR_armv7_a) +#include "page_armv6.h" +#elif defined(PROCESSOR_armv4) | defined(PROCESSOR_armv5) +#include "page_armv4.h" +#else +#error "Unsupported architecture" +#endif #endif Index: kernel/arch/arm32/include/mm/page_armv4.h =================================================================== --- kernel/arch/arm32/include/mm/page_armv4.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) +++ kernel/arch/arm32/include/mm/page_armv4.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -0,0 +1,269 @@ +/* + * Copyright (c) 2007 Pavel Jancik, Michal Kebrt + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup arm32mm + * @{ + */ +/** @file + * @brief Paging related declarations. + */ + +#ifndef KERN_arm32_PAGE_armv4_H_ +#define KERN_arm32_PAGE_armv4_H_ + +#ifndef KERN_arm32_PAGE_H_ +#error "Do not include arch specific page.h directly use generic page.h instead" +#endif + +/* Macros for querying the last-level PTE entries. */ +#define PTE_VALID_ARCH(pte) \ + (*((uint32_t *) (pte)) != 0) +#define PTE_PRESENT_ARCH(pte) \ + (((pte_t *) (pte))->l0.descriptor_type != 0) +#define PTE_GET_FRAME_ARCH(pte) \ + (((pte_t *) (pte))->l1.frame_base_addr << FRAME_WIDTH) +#define PTE_WRITABLE_ARCH(pte) \ + (((pte_t *) (pte))->l1.access_permission_0 == PTE_AP_USER_RW_KERNEL_RW) +#define PTE_EXECUTABLE_ARCH(pte) \ + 1 + +#ifndef __ASM__ + +/** Level 0 page table entry. */ +typedef struct { + /* 0b01 for coarse tables, see below for details */ + unsigned descriptor_type : 2; + unsigned impl_specific : 3; + unsigned domain : 4; + unsigned should_be_zero : 1; + + /* Pointer to the coarse 2nd level page table (holding entries for small + * (4KB) or large (64KB) pages. ARM also supports fine 2nd level page + * tables that may hold even tiny pages (1KB) but they are bigger (4KB + * per table in comparison with 1KB per the coarse table) + */ + unsigned coarse_table_addr : 22; +} ATTRIBUTE_PACKED pte_level0_t; + +/** Level 1 page table entry (small (4KB) pages used). */ +typedef struct { + + /* 0b10 for small pages */ + unsigned descriptor_type : 2; + unsigned bufferable : 1; + unsigned cacheable : 1; + + /* access permissions for each of 4 subparts of a page + * (for each 1KB when small pages used */ + unsigned access_permission_0 : 2; + unsigned access_permission_1 : 2; + unsigned access_permission_2 : 2; + unsigned access_permission_3 : 2; + unsigned frame_base_addr : 20; +} ATTRIBUTE_PACKED pte_level1_t; + +typedef union { + pte_level0_t l0; + pte_level1_t l1; +} pte_t; + +/* Level 1 page tables access permissions */ + +/** User mode: no access, privileged mode: no access. */ +#define PTE_AP_USER_NO_KERNEL_NO 0 + +/** User mode: no access, privileged mode: read/write. */ +#define PTE_AP_USER_NO_KERNEL_RW 1 + +/** User mode: read only, privileged mode: read/write. */ +#define PTE_AP_USER_RO_KERNEL_RW 2 + +/** User mode: read/write, privileged mode: read/write. */ +#define PTE_AP_USER_RW_KERNEL_RW 3 + + +/* pte_level0_t and pte_level1_t descriptor_type flags */ + +/** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type). */ +#define PTE_DESCRIPTOR_NOT_PRESENT 0 + +/** pte_level0_t coarse page table flag (used in descriptor_type). */ +#define PTE_DESCRIPTOR_COARSE_TABLE 1 + +/** pte_level1_t small page table flag (used in descriptor type). */ +#define PTE_DESCRIPTOR_SMALL_PAGE 2 + + +/** Sets the address of level 0 page table. + * + * @param pt Pointer to the page table to set. + * + */ +NO_TRACE static inline void set_ptl0_addr(pte_t *pt) +{ + asm volatile ( + "mcr p15, 0, %[pt], c2, c0, 0\n" + :: [pt] "r" (pt) + ); +} + + +/** Returns level 0 page table entry flags. + * + * @param pt Level 0 page table. + * @param i Index of the entry to return. + * + */ +NO_TRACE static inline int get_pt_level0_flags(pte_t *pt, size_t i) +{ + pte_level0_t *p = &pt[i].l0; + int np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT); + + return (np << PAGE_PRESENT_SHIFT) | (1 << PAGE_USER_SHIFT) | + (1 << PAGE_READ_SHIFT) | (1 << PAGE_WRITE_SHIFT) | + (1 << PAGE_EXEC_SHIFT) | (1 << PAGE_CACHEABLE_SHIFT); +} + +/** Returns level 1 page table entry flags. + * + * @param pt Level 1 page table. + * @param i Index of the entry to return. + * + */ +NO_TRACE static inline int get_pt_level1_flags(pte_t *pt, size_t i) +{ + pte_level1_t *p = &pt[i].l1; + + int dt = p->descriptor_type; + int ap = p->access_permission_0; + + return ((dt == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) | + ((ap == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT) | + ((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_READ_SHIFT) | + ((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_WRITE_SHIFT) | + ((ap != PTE_AP_USER_NO_KERNEL_RW) << PAGE_USER_SHIFT) | + ((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_READ_SHIFT) | + ((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_WRITE_SHIFT) | + (1 << PAGE_EXEC_SHIFT) | + (p->bufferable << PAGE_CACHEABLE); +} + +/** Sets flags of level 0 page table entry. + * + * @param pt level 0 page table + * @param i index of the entry to be changed + * @param flags new flags + * + */ +NO_TRACE static inline void set_pt_level0_flags(pte_t *pt, size_t i, int flags) +{ + pte_level0_t *p = &pt[i].l0; + + if (flags & PAGE_NOT_PRESENT) { + p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; + /* + * Ensures that the entry will be recognized as valid when + * PTE_VALID_ARCH applied. + */ + p->should_be_zero = 1; + } else { + p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE; + p->should_be_zero = 0; + } +} + + +/** Sets flags of level 1 page table entry. + * + * We use same access rights for the whole page. When page + * is not preset we store 1 in acess_rigts_3 so that at least + * one bit is 1 (to mark correct page entry, see #PAGE_VALID_ARCH). + * + * @param pt Level 1 page table. + * @param i Index of the entry to be changed. + * @param flags New flags. + * + */ +NO_TRACE static inline void set_pt_level1_flags(pte_t *pt, size_t i, int flags) +{ + pte_level1_t *p = &pt[i].l1; + + if (flags & PAGE_NOT_PRESENT) + p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; + else + p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE; + + p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0; + + /* default access permission */ + p->access_permission_0 = p->access_permission_1 = + p->access_permission_2 = p->access_permission_3 = + PTE_AP_USER_NO_KERNEL_RW; + + if (flags & PAGE_USER) { + if (flags & PAGE_READ) { + p->access_permission_0 = p->access_permission_1 = + p->access_permission_2 = p->access_permission_3 = + PTE_AP_USER_RO_KERNEL_RW; + } + if (flags & PAGE_WRITE) { + p->access_permission_0 = p->access_permission_1 = + p->access_permission_2 = p->access_permission_3 = + PTE_AP_USER_RW_KERNEL_RW; + } + } +} + +NO_TRACE static inline void set_pt_level0_present(pte_t *pt, size_t i) +{ + pte_level0_t *p = &pt[i].l0; + + p->should_be_zero = 0; + write_barrier(); + p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE; +} + + +NO_TRACE static inline void set_pt_level1_present(pte_t *pt, size_t i) +{ + pte_level1_t *p = &pt[i].l1; + + p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE; +} + + +extern void page_arch_init(void); + + +#endif /* __ASM__ */ + +#endif + +/** @} + */ Index: kernel/arch/arm32/include/mm/page_armv6.h =================================================================== --- kernel/arch/arm32/include/mm/page_armv6.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) +++ kernel/arch/arm32/include/mm/page_armv6.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -0,0 +1,285 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup arm32mm + * @{ + */ +/** @file + * @brief Paging related declarations. + */ + +#ifndef KERN_arm32_PAGE_armv7_H_ +#define KERN_arm32_PAGE_armv7_H_ + +#ifndef KERN_arm32_PAGE_H_ +#error "Do not include arch specific page.h directly use generic page.h instead" +#endif + +/* Macros for querying the last-level PTE entries. */ +#define PTE_VALID_ARCH(pte) \ + (*((uint32_t *) (pte)) != 0) +#define PTE_PRESENT_ARCH(pte) \ + (((pte_t *) (pte))->l0.descriptor_type != 0) +#define PTE_GET_FRAME_ARCH(pte) \ + (((pte_t *) (pte))->l1.frame_base_addr << FRAME_WIDTH) +#define PTE_WRITABLE_ARCH(pte) \ + (((pte_t *) (pte))->l1.access_permission_1 != PTE_AP1_RO) +#define PTE_EXECUTABLE_ARCH(pte) \ + (((pte_t *) (pte))->l1.descriptor_type != PTE_DESCRIPTOR_SMALL_PAGE_NX) + +#ifndef __ASM__ + +/** Level 0 page table entry. */ +typedef struct { + /* 0b01 for coarse tables, see below for details */ + unsigned descriptor_type : 2; + unsigned pxn : 1; + unsigned ns : 1; + unsigned should_be_zero_0 : 1; + unsigned domain : 4; + unsigned should_be_zero_1 : 1; + + /* Pointer to the coarse 2nd level page table (holding entries for small + * (4KB) or large (64KB) pages. ARM also supports fine 2nd level page + * tables that may hold even tiny pages (1KB) but they are bigger (4KB + * per table in comparison with 1KB per the coarse table) + */ + unsigned coarse_table_addr : 22; +} ATTRIBUTE_PACKED pte_level0_t; + +/** Level 1 page table entry (small (4KB) pages used). */ +typedef struct { + + /* 0b10 for small pages, 0b11 for NX small pages */ + unsigned descriptor_type : 2; + unsigned bufferable : 1; + unsigned cacheable : 1; + unsigned access_permission_0 : 2; + unsigned tex : 3; + unsigned access_permission_1 : 1; + unsigned shareable : 1; + unsigned non_global : 1; + unsigned frame_base_addr : 20; +} ATTRIBUTE_PACKED pte_level1_t; + +typedef union { + pte_level0_t l0; + pte_level1_t l1; +} pte_t; + +/* Level 1 page tables access permissions */ + +/** User mode: no access, privileged mode: no access. */ +#define PTE_AP0_USER_NO_KERNEL_NO 0 + +/** User mode: no access, privileged mode: read/write. */ +#define PTE_AP0_USER_NO_KERNEL_FULL 1 + +/** User mode: read only, privileged mode: read/write. */ +#define PTE_AP0_USER_LIMITED_KERNEL_FULL 2 + +/** User mode: read/write, privileged mode: read/write. */ +#define PTE_AP0_USER_FULL_KERNEL_FULL 3 + +/** Allow writes */ +#define PTE_AP1_RO 1 + + +/* pte_level0_t and pte_level1_t descriptor_type flags */ + +/** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type). */ +#define PTE_DESCRIPTOR_NOT_PRESENT 0 + +/** pte_level0_t coarse page table flag (used in descriptor_type). */ +#define PTE_DESCRIPTOR_COARSE_TABLE 1 + +/** pte_level1_t small page table flag (used in descriptor type). */ +#define PTE_DESCRIPTOR_SMALL_PAGE 2 + +/** pte_level1_t small page table flag with NX (used in descriptor type). */ +#define PTE_DESCRIPTOR_SMALL_PAGE_NX 3 + +/** Sets the address of level 0 page table. + * + * @param pt Pointer to the page table to set. + * + */ +NO_TRACE static inline void set_ptl0_addr(pte_t *pt) +{ + asm volatile ( + "mcr p15, 0, %[pt], c2, c0, 0\n" + :: [pt] "r" (pt) + ); +} + + +/** Returns level 0 page table entry flags. + * + * @param pt Level 0 page table. + * @param i Index of the entry to return. + * + */ +NO_TRACE static inline int get_pt_level0_flags(pte_t *pt, size_t i) +{ + const pte_level0_t *p = &pt[i].l0; + const unsigned np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT); + + return (np << PAGE_PRESENT_SHIFT) | (1 << PAGE_USER_SHIFT) | + (1 << PAGE_READ_SHIFT) | (1 << PAGE_WRITE_SHIFT) | + (1 << PAGE_EXEC_SHIFT) | (1 << PAGE_CACHEABLE_SHIFT); +} + +/** Returns level 1 page table entry flags. + * + * @param pt Level 1 page table. + * @param i Index of the entry to return. + * + */ +NO_TRACE static inline int get_pt_level1_flags(pte_t *pt, size_t i) +{ + const pte_level1_t *p = &pt[i].l1; + + const unsigned dt = p->descriptor_type; + const unsigned ap0 = p->access_permission_0; + const unsigned ap1 = p->access_permission_1; + + return ((dt == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) | + ((dt != PTE_DESCRIPTOR_SMALL_PAGE_NX) << PAGE_EXEC_SHIFT) | + ((ap0 == PTE_AP0_USER_LIMITED_KERNEL_FULL) << PAGE_READ_SHIFT) | + ((ap0 == PTE_AP0_USER_FULL_KERNEL_FULL) << PAGE_READ_SHIFT) | + ((ap0 == PTE_AP0_USER_NO_KERNEL_FULL) << PAGE_READ_SHIFT) | + ((ap0 != PTE_AP0_USER_NO_KERNEL_FULL) << PAGE_USER_SHIFT) | + (((ap1 != PTE_AP1_RO) && (ap0 == PTE_AP0_USER_FULL_KERNEL_FULL)) << PAGE_WRITE_SHIFT) | + (((ap1 != PTE_AP1_RO) && (ap0 == PTE_AP0_USER_NO_KERNEL_FULL)) << PAGE_WRITE_SHIFT) | + (p->bufferable << PAGE_CACHEABLE); +} + +/** Sets flags of level 0 page table entry. + * + * @param pt level 0 page table + * @param i index of the entry to be changed + * @param flags new flags + * + */ +NO_TRACE static inline void set_pt_level0_flags(pte_t *pt, size_t i, int flags) +{ + pte_level0_t *p = &pt[i].l0; + + if (flags & PAGE_NOT_PRESENT) { + p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; + /* + * Ensures that the entry will be recognized as valid when + * PTE_VALID_ARCH applied. + */ + p->should_be_zero_0 = 1; + p->should_be_zero_1 = 1; + } else { + p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE; + p->should_be_zero_0 = 0; + p->should_be_zero_1 = 0; + p->domain = 0; + p->ns = 0; + } +} + + +/** Sets flags of level 1 page table entry. + * + * We use same access rights for the whole page. When page + * is not preset we store 1 in acess_rigts_3 so that at least + * one bit is 1 (to mark correct page entry, see #PAGE_VALID_ARCH). + * + * @param pt Level 1 page table. + * @param i Index of the entry to be changed. + * @param flags New flags. + * + */ +NO_TRACE static inline void set_pt_level1_flags(pte_t *pt, size_t i, int flags) +{ + pte_level1_t *p = &pt[i].l1; + + if (flags & PAGE_NOT_PRESENT) { + p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; + } else { + if (flags & PAGE_EXEC) + p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE; + else + p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE_NX; + } + + /* tex=0 buf=1 and cache=1 => normal memory + * tex=0 buf=1 and cache=0 => shareable device mmio + */ + p->cacheable = (flags & PAGE_CACHEABLE); + p->bufferable = 1; + p->tex = 0; + + /* Shareable is ignored for devices (non-cacheable), + * turn it on for normal memory. */ + p->shareable = 1; + + p->non_global = !(flags & PAGE_GLOBAL); + + /* default access permission: kernel only*/ + p->access_permission_0 = PTE_AP0_USER_NO_KERNEL_FULL; + + if (flags & PAGE_USER) { + p->access_permission_0 = PTE_AP0_USER_FULL_KERNEL_FULL; + // TODO Fix kernel to use PAGE_WRITE flag properly and + // apply this for kernel pages as well. + if (!(flags & PAGE_WRITE)) + p->access_permission_1 = PTE_AP1_RO; + } +} + +NO_TRACE static inline void set_pt_level0_present(pte_t *pt, size_t i) +{ + pte_level0_t *p = &pt[i].l0; + + p->should_be_zero_0 = 0; + p->should_be_zero_1 = 0; + write_barrier(); + p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE; +} + +NO_TRACE static inline void set_pt_level1_present(pte_t *pt, size_t i) +{ + pte_level1_t *p = &pt[i].l1; + + p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE; +} + + +extern void page_arch_init(void); + +#endif /* __ASM__ */ + +#endif + +/** @} + */ Index: kernel/arch/arm32/include/mm/page_fault.h =================================================================== --- kernel/arch/arm32/include/mm/page_fault.h (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ kernel/arch/arm32/include/mm/page_fault.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -40,18 +40,28 @@ -/** Decribes CP15 "fault status register" (FSR). */ -typedef struct { - unsigned status : 3; - unsigned domain : 4; - unsigned zero : 1; - unsigned should_be_zero : 24; -} ATTRIBUTE_PACKED fault_status_t; - - -/** Help union used for casting integer value into #fault_status_t. */ +/** Decribes CP15 "fault status register" (FSR). + * + * See ARM Architecture Reference Manual ch. B4.9.6 (pdf p.743). + */ typedef union { - fault_status_t fs; - uint32_t dummy; -} fault_status_union_t; + struct { + unsigned status : 4; + unsigned domain : 4; + unsigned zero : 1; + unsigned lpae : 1; /**< Needs LPAE support implemented */ + unsigned fs : 1; /**< armv6+ mandated, earlier IPLM. DEFINED */ + unsigned wr : 1; /**< armv6+ only */ + unsigned ext : 1 ; /**< external abort */ + unsigned cm : 1; /**< Cache maintenance, needs LPAE support */ + unsigned should_be_zero : 18; + } data; + struct { + unsigned status : 4; + unsigned sbz0 : 6; + unsigned fs : 1; + unsigned should_be_zero : 21; + } inst; + uint32_t raw; +} fault_status_t; Index: kernel/arch/arm32/include/regutils.h =================================================================== --- kernel/arch/arm32/include/regutils.h (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ kernel/arch/arm32/include/regutils.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -41,5 +41,27 @@ #define STATUS_REG_MODE_MASK 0x1f -#define CP15_R1_HIGH_VECTORS_BIT (1 << 13) +/* COntrol register bit values see ch. B4.1.130 of ARM Architecture Reference + * Manual ARMv7-A and ARMv7-R edition, page 1687 */ +#define CP15_R1_MMU_EN (1 << 0) +#define CP15_R1_ALIGN_CHECK_EN (1 << 1) /* Allow alignemnt check */ +#define CP15_R1_CACHE_EN (1 << 2) +#define CP15_R1_CP15_BARRIER_EN (1 << 5) +#define CP15_R1_B_EN (1 << 7) /* ARMv6- only big endian switch */ +#define CP15_R1_SWAP_EN (1 << 10) +#define CP15_R1_BRANCH_PREDICT_EN (1 << 11) +#define CP15_R1_INST_CACHE_EN (1 << 12) +#define CP15_R1_HIGH_VECTORS_EN (1 << 13) +#define CP15_R1_ROUND_ROBIN_EN (1 << 14) +#define CP15_R1_HW_ACCESS_FLAG_EN (1 << 17) +#define CP15_R1_WRITE_XN_EN (1 << 19) /* Only if virt. supported */ +#define CP15_R1_USPCE_WRITE_XN_EN (1 << 20) /* Only if virt. supported */ +#define CP15_R1_FAST_IRQ_EN (1 << 21) /* Disbale impl.specific features */ +#define CP15_R1_UNALIGNED_EN (1 << 22) /* Must be 1 on armv7 */ +#define CP15_R1_IRQ_VECTORS_EN (1 << 24) +#define CP15_R1_BIG_ENDIAN_EXC (1 << 25) +#define CP15_R1_NMFI_EN (1 << 27) +#define CP15_R1_TEX_REMAP_EN (1 << 28) +#define CP15_R1_ACCESS_FLAG_EN (1 << 29) +#define CP15_R1_THUMB_EXC_EN (1 << 30) /* ARM Processor Operation Modes */ Index: kernel/arch/arm32/src/arm32.c =================================================================== --- kernel/arch/arm32/src/arm32.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ kernel/arch/arm32/src/arm32.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -49,4 +49,5 @@ #include #include +#include /** Performs arm32-specific initialization before main_bsp() is called. */ @@ -116,4 +117,8 @@ { machine_input_init(); + const char *platform = machine_get_platform_name(); + + sysinfo_set_item_data("platform", NULL, (void *) platform, + str_size(platform)); } Index: kernel/arch/arm32/src/cpu/cpu.c =================================================================== --- kernel/arch/arm32/src/cpu/cpu.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ kernel/arch/arm32/src/cpu/cpu.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -44,14 +44,17 @@ /** Implementators (vendor) names */ static const char *imp_data[] = { - "?", /* IMP_DATA_START_OFFSET */ - "ARM Ltd", /* 0x41 */ - "", /* 0x42 */ - "", /* 0x43 */ - "Digital Equipment Corporation", /* 0x44 */ - "", "", "", "", "", "", "", "", "", "", /* 0x45 - 0x4e */ - "", "", "", "", "", "", "", "", "", "", /* 0x4f - 0x58 */ - "", "", "", "", "", "", "", "", "", "", /* 0x59 - 0x62 */ - "", "", "", "", "", "", /* 0x63 - 0x68 */ - "Intel Corporation" /* 0x69 */ + "?", /* IMP_DATA_START_OFFSET */ + "ARM Limited", /* 0x41 */ + "", "", /* 0x42 - 0x43 */ + "Digital Equipment Corporation", /* 0x44 */ + "", "", "", "", "", "", "", "", /* 0x45 - 0x4c */ + "Motorola, Freescale Semicondutor Inc.", /* 0x4d */ + "", "", "", /* 0x4e - 0x50 */ + "Qualcomm Inc.", /* 0x51 */ + "", "", "", "", /* 0x52 - 0x55 */ + "Marvell Semiconductor", /* 0x56 */ + "", "", "", "", "", "", "", "", "", "", /* 0x57 - 0x60 */ + "", "", "", "", "", "", "", "", /* 0x61 - 0x68 */ + "Intel Corporation" /* 0x69 */ }; @@ -94,11 +97,47 @@ } -/** Does nothing on ARM. */ +/** Enables unaligned access and caching for armv6+ */ void cpu_arch_init(void) { +#if defined(PROCESSOR_armv7_a) | defined(PROCESSOR_armv6) + uint32_t control_reg = 0; + asm volatile ( + "mrc p15, 0, %[control_reg], c1, c0" + : [control_reg] "=r" (control_reg) + ); + + /* Turn off tex remap, RAZ ignores writes prior to armv7 */ + control_reg &= ~CP15_R1_TEX_REMAP_EN; + /* Turn off accessed flag, RAZ ignores writes prior to armv7 */ + control_reg &= ~(CP15_R1_ACCESS_FLAG_EN | CP15_R1_HW_ACCESS_FLAG_EN); + /* Enable unaligned access, RAZ ignores writes prior to armv6 + * switchable on armv6, RAO ignores writes on armv7, + * see ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition + * L.3.1 (p. 2456) */ + control_reg |= CP15_R1_UNALIGNED_EN; + /* Disable alignment checks, this turns unaligned access to undefined, + * unless U bit is set. */ + control_reg &= ~CP15_R1_ALIGN_CHECK_EN; + /* Enable caching, On arm prior to armv7 there is only one level + * of caches. Data cache is coherent. + * "This means that the behavior of accesses from the same observer to + * different VAs, that are translated to the same PA + * with the same memory attributes, is fully coherent." + * ARM Architecture Reference Manual ARMv7-A and ARMv7-R Edition + * B3.11.1 (p. 1383) + * ICache coherency is elaborate on in barrier.h. + * We are safe to turn these on. + */ + control_reg |= CP15_R1_CACHE_EN | CP15_R1_INST_CACHE_EN; + + asm volatile ( + "mcr p15, 0, %[control_reg], c1, c0" + :: [control_reg] "r" (control_reg) + ); +#endif } /** Retrieves processor identification and stores it to #CPU.arch */ -void cpu_identify(void) +void cpu_identify(void) { arch_cpu_identify(&CPU->arch); @@ -112,11 +151,12 @@ cpu_arch_t * cpu_arch = &m->arch; - if ((cpu_arch->imp_num) > 0 && - (cpu_arch->imp_num < (imp_data_length + IMP_DATA_START_OFFSET))) { + const unsigned imp_offset = cpu_arch->imp_num - IMP_DATA_START_OFFSET; + + if (imp_offset < imp_data_length) { vendor = imp_data[cpu_arch->imp_num - IMP_DATA_START_OFFSET]; } - if ((cpu_arch->arch_num) > 0 && - (cpu_arch->arch_num < arch_data_length)) { + // TODO CPUs with arch_num == 0xf use CPUID scheme for identification + if (cpu_arch->arch_num < arch_data_length) { architecture = arch_data[cpu_arch->arch_num]; } Index: kernel/arch/arm32/src/exception.c =================================================================== --- kernel/arch/arm32/src/exception.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ kernel/arch/arm32/src/exception.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -117,9 +117,24 @@ #ifdef HIGH_EXCEPTION_VECTORS -/** Activates use of high exception vectors addresses. */ +/** Activates use of high exception vectors addresses. + * + * "High vectors were introduced into some implementations of ARMv4 and are + * required in ARMv6 implementations. High vectors allow the exception vector + * locations to be moved from their normal address range 0x00000000-0x0000001C + * at the bottom of the 32-bit address space, to an alternative address range + * 0xFFFF0000-0xFFFF001C near the top of the address space. These alternative + * locations are known as the high vectors. + * + * Prior to ARMv6, it is IMPLEMENTATION DEFINED whether the high vectors are + * supported. When they are, a hardware configuration input selects whether + * the normal vectors or the high vectors are to be used from + * reset." ARM Architecture Reference Manual A2.6.11 (p. 64 in the PDF). + * + * ARM920T (gta02) TRM A2.3.5 (PDF p. 36) and ARM926EJ-S (icp) 2.3.2 (PDF p. 42) + * say that armv4 an armv5 chips that we support implement this. + */ static void high_vectors(void) { - uint32_t control_reg; - + uint32_t control_reg = 0; asm volatile ( "mrc p15, 0, %[control_reg], c1, c0" @@ -128,5 +143,5 @@ /* switch on the high vectors bit */ - control_reg |= CP15_R1_HIGH_VECTORS_BIT; + control_reg |= CP15_R1_HIGH_VECTORS_EN; asm volatile ( @@ -153,4 +168,5 @@ void exception_init(void) { + // TODO check for availability of high vectors for <= armv5 #ifdef HIGH_EXCEPTION_VECTORS high_vectors(); Index: kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c =================================================================== --- kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) +++ kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -0,0 +1,261 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** @addtogroup arm32beagleboardxm + * @{ + */ +/** @file + * @brief BeagleBoard-xM platform driver. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void bbxm_init(void); +static void bbxm_timer_irq_start(void); +static void bbxm_cpu_halt(void); +static void bbxm_get_memory_extents(uintptr_t *start, size_t *size); +static void bbxm_irq_exception(unsigned int exc_no, istate_t *istate); +static void bbxm_frame_init(void); +static void bbxm_output_init(void); +static void bbxm_input_init(void); +static size_t bbxm_get_irq_count(void); +static const char *bbxm_get_platform_name(void); + +#define BBXM_MEMORY_START 0x80000000 /* physical */ +#define BBXM_MEMORY_SIZE 0x20000000 /* 512 MB */ + +static struct beagleboard { + amdm37x_dispc_regs_t *dispc; + amdm37x_irc_regs_t *irc_addr; + amdm37x_uart_t uart; + amdm37x_gpt_t timer; +} beagleboard; + +struct arm_machine_ops bbxm_machine_ops = { + .machine_init = bbxm_init, + .machine_timer_irq_start = bbxm_timer_irq_start, + .machine_cpu_halt = bbxm_cpu_halt, + .machine_get_memory_extents = bbxm_get_memory_extents, + .machine_irq_exception = bbxm_irq_exception, + .machine_frame_init = bbxm_frame_init, + .machine_output_init = bbxm_output_init, + .machine_input_init = bbxm_input_init, + .machine_get_irq_count = bbxm_get_irq_count, + .machine_get_platform_name = bbxm_get_platform_name +}; + +static irq_ownership_t bb_timer_irq_claim(irq_t *irq) +{ + return IRQ_ACCEPT; +} + +static void bbxm_setup_fb(unsigned width, unsigned height, unsigned bpp) +{ + const unsigned pixel_bytes = (bpp / 8); + const size_t size = ALIGN_UP(width * height * pixel_bytes, FRAME_SIZE); + const unsigned frames = size / FRAME_SIZE; + unsigned order = 0; + unsigned frame = 1; + while (frame < frames) { + frame *= 2; + ++order; + } + /* prefer highmem as we don't care about virtual mapping. */ + void *buffer = frame_alloc(order, FRAME_LOWMEM); + if (!buffer) { + printf("Failed to allocate framebuffer.\n"); + return; + } + + amdm37x_dispc_setup_fb(beagleboard.dispc, width, height, bpp, + (uintptr_t) buffer); + + fb_properties_t prop = { + .addr = (uintptr_t)buffer, + .offset = 0, + .x = width, + .y = height, + .scan = width * pixel_bytes, + .visual = VISUAL_RGB_5_6_5_LE + }; + switch (bpp) + { + case 8: + prop.visual = VISUAL_INDIRECT_8; break; + case 16: + prop.visual = VISUAL_RGB_5_6_5_LE; break; + case 24: + prop.visual = VISUAL_BGR_8_8_8; break; + case 32: + prop.visual = VISUAL_RGB_8_8_8_0; break; + default: + printf("Invalid framebuffer bit depth: bailing out.\n"); + return; + } + outdev_t *fb_dev = fb_init(&prop); + if (fb_dev) + stdout_wire(fb_dev); + +} + +static void bb_timer_irq_handler(irq_t *irq) +{ + /* + * We are holding a lock which prevents preemption. + * Release the lock, call clock() and reacquire the lock again. + */ + amdm37x_gpt_irq_ack(&beagleboard.timer); + spinlock_unlock(&irq->lock); + clock(); + spinlock_lock(&irq->lock); +} + +static void bbxm_init(void) +{ + /* Initialize interrupt controller */ + beagleboard.irc_addr = + (void *) km_map(AMDM37x_IRC_BASE_ADDRESS, AMDM37x_IRC_SIZE, + PAGE_NOT_CACHEABLE); + ASSERT(beagleboard.irc_addr); + amdm37x_irc_init(beagleboard.irc_addr); + + /* Map display controller */ + beagleboard.dispc = (void*) km_map(AMDM37x_DISPC_BASE_ADDRESS, + AMDM37x_DISPC_SIZE, PAGE_NOT_CACHEABLE); + ASSERT(beagleboard.dispc); + + /* Initialize timer. Use timer1, because it is in WKUP power domain + * (always on) and has special capabilities for precise 1ms ticks */ + amdm37x_gpt_timer_ticks_init(&beagleboard.timer, + AMDM37x_GPT1_BASE_ADDRESS, AMDM37x_GPT1_SIZE, HZ); +} + +static void bbxm_timer_irq_start(void) +{ + /* Initialize timer IRQ */ + static irq_t timer_irq; + irq_initialize(&timer_irq); + timer_irq.devno = device_assign_devno(); + timer_irq.inr = AMDM37x_GPT1_IRQ; + timer_irq.claim = bb_timer_irq_claim; + timer_irq.handler = bb_timer_irq_handler; + irq_register(&timer_irq); + + /* Enable timer interrupt */ + amdm37x_irc_enable(beagleboard.irc_addr, AMDM37x_GPT1_IRQ); + + /* Start timer here */ + amdm37x_gpt_timer_ticks_start(&beagleboard.timer); +} + +static void bbxm_cpu_halt(void) +{ + while (1); +} + +/** Get extents of available memory. + * + * @param start Place to store memory start address (physical). + * @param size Place to store memory size. + */ +static void bbxm_get_memory_extents(uintptr_t *start, size_t *size) +{ + *start = BBXM_MEMORY_START; + *size = BBXM_MEMORY_SIZE; +} + +static void bbxm_irq_exception(unsigned int exc_no, istate_t *istate) +{ + const unsigned inum = amdm37x_irc_inum_get(beagleboard.irc_addr); + amdm37x_irc_irq_ack(beagleboard.irc_addr); + + irq_t *irq = irq_dispatch_and_lock(inum); + if (irq) { + /* The IRQ handler was found. */ + irq->handler(irq); + spinlock_unlock(&irq->lock); + } else { + /* Spurious interrupt.*/ + printf("cpu%d: spurious interrupt (inum=%d)\n", + CPU->id, inum); + } +} + +static void bbxm_frame_init(void) +{ +} + +static void bbxm_output_init(void) +{ +#ifdef CONFIG_FB + bbxm_setup_fb(CONFIG_BFB_WIDTH, CONFIG_BFB_HEIGHT, CONFIG_BFB_BPP); +#else + (void)bbxm_setup_fb; +#endif + /* UART3 is wired to external RS232 connector */ + const bool ok = amdm37x_uart_init(&beagleboard.uart, + AMDM37x_UART3_IRQ, AMDM37x_UART3_BASE_ADDRESS, AMDM37x_UART3_SIZE); + if (ok) { + stdout_wire(&beagleboard.uart.outdev); + } +} + +static void bbxm_input_init(void) +{ + srln_instance_t *srln_instance = srln_init(); + if (srln_instance) { + indev_t *sink = stdin_wire(); + indev_t *srln = srln_wire(srln_instance, sink); + amdm37x_uart_input_wire(&beagleboard.uart, srln); + amdm37x_irc_enable(beagleboard.irc_addr, AMDM37x_UART3_IRQ); + } +} + +size_t bbxm_get_irq_count(void) +{ + return AMDM37x_IRC_IRQ_COUNT; +} + +const char *bbxm_get_platform_name(void) +{ + return "beagleboardxm"; +} + +/** + * @} + */ Index: kernel/arch/arm32/src/machine_func.c =================================================================== --- kernel/arch/arm32/src/machine_func.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ kernel/arch/arm32/src/machine_func.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -42,4 +42,5 @@ #include #include +#include /** Pointer to machine_ops structure being used. */ @@ -55,4 +56,6 @@ #elif defined(MACHINE_integratorcp) machine_ops = &icp_machine_ops; +#elif defined(MACHINE_beagleboardxm) + machine_ops = &bbxm_machine_ops; #else #error Machine type not defined. @@ -131,4 +134,10 @@ } +const char * machine_get_platform_name(void) +{ + if (machine_ops->machine_get_platform_name) + return machine_ops->machine_get_platform_name(); + return NULL; +} /** @} */ Index: kernel/arch/arm32/src/mm/page.c =================================================================== --- kernel/arch/arm32/src/mm/page.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ kernel/arch/arm32/src/mm/page.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -52,14 +52,16 @@ void page_arch_init(void) { - int flags = PAGE_CACHEABLE; + int flags = PAGE_CACHEABLE | PAGE_EXEC; page_mapping_operations = &pt_mapping_operations; page_table_lock(AS_KERNEL, true); - uintptr_t cur; - /* Kernel identity mapping */ - for (cur = PHYSMEM_START_ADDR; - cur < min(config.identity_size, config.physmem_end); + //FIXME: We need to consider the possibility that + //identity_base > identity_size and physmem_end. + //This might lead to overflow if identity_size is too big. + for (uintptr_t cur = PHYSMEM_START_ADDR; + cur < min(KA2PA(config.identity_base) + + config.identity_size, config.physmem_end); cur += FRAME_SIZE) page_mapping_insert(AS_KERNEL, PA2KA(cur), cur, flags); Index: kernel/arch/arm32/src/mm/page_fault.c =================================================================== --- kernel/arch/arm32/src/mm/page_fault.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ kernel/arch/arm32/src/mm/page_fault.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -42,27 +42,124 @@ #include -/** Returns value stored in fault status register. + +/** + * FSR encoding ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition. + * + * B3.13.3 page B3-1406 (PDF page 1406) + */ +typedef enum { + DFSR_SOURCE_ALIGN = 0x0001, + DFSR_SOURCE_CACHE_MAINTENANCE = 0x0004, + DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L1 = 0x000c, + DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L2 = 0x000e, + DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L1 = 0x040c, + DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L2 = 0x040e, + DFSR_SOURCE_TRANSLATION_L1 = 0x0005, + DFSR_SOURCE_TRANSLATION_L2 = 0x0007, + DFSR_SOURCE_ACCESS_FLAG_L1 = 0x0003, /**< @note: This used to be alignment enc. */ + DFSR_SOURCE_ACCESS_FLAG_L2 = 0x0006, + DFSR_SOURCE_DOMAIN_L1 = 0x0009, + DFSR_SOURCE_DOMAIN_L2 = 0x000b, + DFSR_SOURCE_PERMISSION_L1 = 0x000d, + DFSR_SOURCE_PERMISSION_L2 = 0x000f, + DFSR_SOURCE_DEBUG = 0x0002, + DFSR_SOURCE_SYNC_EXTERNAL = 0x0008, + DFSR_SOURCE_TLB_CONFLICT = 0x0400, + DFSR_SOURCE_LOCKDOWN = 0x0404, /**< @note: Implementation defined */ + DFSR_SOURCE_COPROCESSOR = 0x040a, /**< @note Implementation defined */ + DFSR_SOURCE_SYNC_PARITY = 0x0409, + DFSR_SOURCE_ASYNC_EXTERNAL = 0x0406, + DFSR_SOURCE_ASYNC_PARITY = 0x0408, + DFSR_SOURCE_MASK = 0x0000040f, +} dfsr_source_t; + +static inline const char * dfsr_source_to_str(dfsr_source_t source) +{ + switch (source) { + case DFSR_SOURCE_TRANSLATION_L1: + return "Translation fault L1"; + case DFSR_SOURCE_TRANSLATION_L2: + return "Translation fault L2"; + case DFSR_SOURCE_PERMISSION_L1: + return "Permission fault L1"; + case DFSR_SOURCE_PERMISSION_L2: + return "Permission fault L2"; + case DFSR_SOURCE_ALIGN: + return "Alignment fault"; + case DFSR_SOURCE_CACHE_MAINTENANCE: + return "Instruction cache maintenance fault"; + case DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L1: + return "Synchronous external abort on translation table walk level 1"; + case DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L2: + return "Synchronous external abort on translation table walk level 2"; + case DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L1: + return "Synchronous parity error on translation table walk level 1"; + case DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L2: + return "Synchronous parity error on translation table walk level 2"; + case DFSR_SOURCE_ACCESS_FLAG_L1: + return "Access flag fault L1"; + case DFSR_SOURCE_ACCESS_FLAG_L2: + return "Access flag fault L2"; + case DFSR_SOURCE_DOMAIN_L1: + return "Domain fault L1"; + case DFSR_SOURCE_DOMAIN_L2: + return "Domain flault L2"; + case DFSR_SOURCE_DEBUG: + return "Debug event"; + case DFSR_SOURCE_SYNC_EXTERNAL: + return "Synchronous external abort"; + case DFSR_SOURCE_TLB_CONFLICT: + return "TLB conflict abort"; + case DFSR_SOURCE_LOCKDOWN: + return "Lockdown (Implementation defined)"; + case DFSR_SOURCE_COPROCESSOR: + return "Coprocessor abort (Implementation defined)"; + case DFSR_SOURCE_SYNC_PARITY: + return "Synchronous parity error on memory access"; + case DFSR_SOURCE_ASYNC_EXTERNAL: + return "Asynchronous external abort"; + case DFSR_SOURCE_ASYNC_PARITY: + return "Asynchronous parity error on memory access"; + case DFSR_SOURCE_MASK: + break; + } + return "Unknown data abort"; +} + + +/** Returns value stored in comnbined/data fault status register. * * @return Value stored in CP15 fault status register (FSR). - */ -static inline fault_status_t read_fault_status_register(void) -{ - fault_status_union_t fsu; + * + * "VMSAv6 added a fifth fault status bit (bit[10]) to both the IFSR and DFSR. + * It is IMPLEMENTATION DEFINED how this bit is encoded in earlier versions of + * the architecture. A write flag (bit[11] of the DFSR) has also been + * introduced." + * ARM Architecture Reference Manual version i ch. B4.6 (PDF p. 719) + * + * See ch. B4.9.6 for location of data/instruction FSR. + * + */ +static inline fault_status_t read_data_fault_status_register(void) +{ + fault_status_t fsu; - /* fault status is stored in CP15 register 5 */ + /* Combined/Data fault status is stored in CP15 register 5, c0. */ asm volatile ( "mrc p15, 0, %[dummy], c5, c0, 0" - : [dummy] "=r" (fsu.dummy) + : [dummy] "=r" (fsu.raw) ); - return fsu.fs; -} - -/** Returns FAR (fault address register) content. - * - * @return FAR (fault address register) content (address that caused a page + return fsu; +} + +/** Returns DFAR (fault address register) content. + * + * This register is equivalent to FAR on pre armv6 machines. + * + * @return DFAR (fault address register) content (address that caused a page * fault) */ -static inline uintptr_t read_fault_address_register(void) +static inline uintptr_t read_data_fault_address_register(void) { uintptr_t ret; @@ -77,4 +174,5 @@ } +#if defined(PROCESSOR_armv4) | defined(PROCESSOR_armv5) /** Decides whether read or write into memory is requested. * @@ -97,5 +195,5 @@ panic("page_fault - instruction does not access memory " "(instr_code: %#0" PRIx32 ", badvaddr:%p).", - instr_union.pc, (void *) badvaddr); + *(uint32_t*)instr_union.instr, (void *) badvaddr); return PF_ACCESS_EXEC; } @@ -136,4 +234,5 @@ inst, (void *) badvaddr); } +#endif /** Handles "data abort" exception (load or store at invalid address). @@ -145,16 +244,50 @@ void data_abort(unsigned int exc_no, istate_t *istate) { - fault_status_t fsr __attribute__ ((unused)) = - read_fault_status_register(); - uintptr_t badvaddr = read_fault_address_register(); - - pf_access_t access = get_memory_access_type(istate->pc, badvaddr); - - int ret = as_page_fault(badvaddr, access, istate); - - if (ret == AS_PF_FAULT) { - fault_if_from_uspace(istate, "Page fault: %#x.", badvaddr); - panic_memtrap(istate, access, badvaddr, NULL); + const uintptr_t badvaddr = read_data_fault_address_register(); + const fault_status_t fsr = read_data_fault_status_register(); + const dfsr_source_t source = fsr.raw & DFSR_SOURCE_MASK; + + switch (source) { + case DFSR_SOURCE_TRANSLATION_L1: + case DFSR_SOURCE_TRANSLATION_L2: + case DFSR_SOURCE_PERMISSION_L1: + case DFSR_SOURCE_PERMISSION_L2: + /* Page fault is handled further down */ + break; + case DFSR_SOURCE_ALIGN: + case DFSR_SOURCE_CACHE_MAINTENANCE: + case DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L1: + case DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L2: + case DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L1: + case DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L2: + case DFSR_SOURCE_ACCESS_FLAG_L1: + case DFSR_SOURCE_ACCESS_FLAG_L2: + case DFSR_SOURCE_DOMAIN_L1: + case DFSR_SOURCE_DOMAIN_L2: + case DFSR_SOURCE_DEBUG: + case DFSR_SOURCE_SYNC_EXTERNAL: + case DFSR_SOURCE_TLB_CONFLICT: + case DFSR_SOURCE_LOCKDOWN: + case DFSR_SOURCE_COPROCESSOR: + case DFSR_SOURCE_SYNC_PARITY: + case DFSR_SOURCE_ASYNC_EXTERNAL: + case DFSR_SOURCE_ASYNC_PARITY: + case DFSR_SOURCE_MASK: + /* Weird abort stuff */ + fault_if_from_uspace(istate, "Unhandled abort %s at address: " + "%#x.", dfsr_source_to_str(source), badvaddr); + panic("Unhandled abort %s at address: %#x.", + dfsr_source_to_str(source), badvaddr); } + +#if defined(PROCESSOR_armv6) | defined(PROCESSOR_armv7_a) + const pf_access_t access = + fsr.data.wr ? PF_ACCESS_WRITE : PF_ACCESS_READ; +#elif defined(PROCESSOR_armv4) | defined(PROCESSOR_armv5) + const pf_access_t access = get_memory_access_type(istate->pc, badvaddr); +#else +#error "Unsupported architecture" +#endif + as_page_fault(badvaddr, access, istate); } @@ -167,11 +300,5 @@ void prefetch_abort(unsigned int exc_no, istate_t *istate) { - int ret = as_page_fault(istate->pc, PF_ACCESS_EXEC, istate); - - if (ret == AS_PF_FAULT) { - fault_if_from_uspace(istate, - "Page fault - prefetch_abort: %#x.", istate->pc); - panic_memtrap(istate, PF_ACCESS_EXEC, istate->pc, NULL); - } + as_page_fault(istate->pc, PF_ACCESS_EXEC, istate); } Index: kernel/arch/ia64/include/mm/as.h =================================================================== --- kernel/arch/ia64/include/mm/as.h (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ kernel/arch/ia64/include/mm/as.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -43,6 +43,4 @@ #define USER_ADDRESS_SPACE_END_ARCH UINT64_C(0xdfffffffffffffff) -#define USTACK_ADDRESS_ARCH UINT64_C(0x0000000ff0000000) - typedef struct { } as_arch_t; Index: kernel/arch/ia64/src/mm/tlb.c =================================================================== --- kernel/arch/ia64/src/mm/tlb.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ kernel/arch/ia64/src/mm/tlb.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -113,6 +113,6 @@ va = page; - rr.word = rr_read(VA2VRN(va)); - if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA2VRN(va))))) { + rr.word = rr_read(VA2VRN(page)); + if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA2VRN(page))))) { /* * The selected region register does not contain required RID. @@ -122,6 +122,6 @@ rr0 = rr; - rr0.map.rid = ASID2RID(asid, VA2VRN(va)); - rr_write(VA2VRN(va), rr0.word); + rr0.map.rid = ASID2RID(asid, VA2VRN(page)); + rr_write(VA2VRN(page), rr0.word); srlz_d(); srlz_i(); @@ -139,38 +139,38 @@ case 1: /* cnt 4 - 15 */ ps = PAGE_WIDTH + 2; - va &= ~((1 << ps) - 1); + va &= ~((1UL << ps) - 1); break; case 2: /* cnt 16 - 63 */ ps = PAGE_WIDTH + 4; - va &= ~((1 << ps) - 1); + va &= ~((1UL << ps) - 1); break; case 3: /* cnt 64 - 255 */ ps = PAGE_WIDTH + 6; - va &= ~((1 << ps) - 1); + va &= ~((1UL << ps) - 1); break; case 4: /* cnt 256 - 1023 */ ps = PAGE_WIDTH + 8; - va &= ~((1 << ps) - 1); + va &= ~((1UL << ps) - 1); break; case 5: /* cnt 1024 - 4095 */ ps = PAGE_WIDTH + 10; - va &= ~((1 << ps) - 1); + va &= ~((1UL << ps) - 1); break; case 6: /* cnt 4096 - 16383 */ ps = PAGE_WIDTH + 12; - va &= ~((1 << ps) - 1); + va &= ~((1UL << ps) - 1); break; case 7: /* cnt 16384 - 65535 */ case 8: /* cnt 65536 - (256K - 1) */ ps = PAGE_WIDTH + 14; - va &= ~((1 << ps) - 1); + va &= ~((1UL << ps) - 1); break; default: ps = PAGE_WIDTH + 18; - va &= ~((1 << ps) - 1); - break; - } - - for (; va < (page + cnt * PAGE_SIZE); va += (1 << ps)) + va &= ~((1UL << ps) - 1); + break; + } + + for (; va < (page + cnt * PAGE_SIZE); va += (1UL << ps)) asm volatile ( "ptc.l %[va], %[ps] ;;" @@ -183,5 +183,5 @@ if (restore_rr) { - rr_write(VA2VRN(va), rr.word); + rr_write(VA2VRN(page), rr.word); srlz_d(); srlz_i(); @@ -501,9 +501,5 @@ * Forward the page fault to address space page fault handler. */ - if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) { - fault_if_from_uspace(istate, "Page fault at %p.", - (void *) va); - panic_memtrap(istate, PF_ACCESS_EXEC, va, NULL); - } + as_page_fault(va, PF_ACCESS_EXEC, istate); } } @@ -619,9 +615,5 @@ * handler. */ - if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) { - fault_if_from_uspace(istate, "Page fault at %p.", - (void *) va); - panic_memtrap(istate, PF_ACCESS_UNKNOWN, va, NULL); - } + as_page_fault(va, PF_ACCESS_READ, istate); } } @@ -667,9 +659,5 @@ dtc_pte_copy(t); } else { - if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) { - fault_if_from_uspace(istate, "Page fault at %p.", - (void *) va); - panic_memtrap(istate, PF_ACCESS_WRITE, va, NULL); - } + as_page_fault(va, PF_ACCESS_WRITE, istate); } } @@ -700,9 +688,5 @@ itc_pte_copy(t); } else { - if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) { - fault_if_from_uspace(istate, "Page fault at %p.", - (void *) va); - panic_memtrap(istate, PF_ACCESS_EXEC, va, NULL); - } + as_page_fault(va, PF_ACCESS_EXEC, istate); } } @@ -764,9 +748,5 @@ ASSERT((t) && (t->p)); ASSERT(!t->w); - if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) { - fault_if_from_uspace(istate, "Page fault at %p.", - (void *) va); - panic_memtrap(istate, PF_ACCESS_WRITE, va, NULL); - } + as_page_fault(va, PF_ACCESS_WRITE, istate); } @@ -799,9 +779,5 @@ dtc_pte_copy(t); } else { - if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) { - fault_if_from_uspace(istate, "Page fault at %p.", - (void *) va); - panic_memtrap(istate, PF_ACCESS_UNKNOWN, va, NULL); - } + as_page_fault(va, PF_ACCESS_READ, istate); } } Index: kernel/arch/mips32/src/mm/tlb.c =================================================================== --- kernel/arch/mips32/src/mm/tlb.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ kernel/arch/mips32/src/mm/tlb.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -48,9 +48,5 @@ #include -static void tlb_refill_fail(istate_t *); -static void tlb_invalid_fail(istate_t *); -static void tlb_modified_fail(istate_t *); - -static pte_t *find_mapping_and_check(uintptr_t, int, istate_t *, int *); +static pte_t *find_mapping_and_check(uintptr_t, int, istate_t *); /** Initialize TLB. @@ -92,54 +88,33 @@ uintptr_t badvaddr; pte_t *pte; - int pfrc; badvaddr = cp0_badvaddr_read(); asid = AS->asid; - pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc); - if (!pte) { - switch (pfrc) { - case AS_PF_FAULT: - goto fail; - break; - case AS_PF_DEFER: - /* - * The page fault came during copy_from_uspace() - * or copy_to_uspace(). - */ - return; - default: - panic("Unexpected pfrc (%d).", pfrc); + pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate); + if (pte) { + /* + * Record access to PTE. + */ + pte->a = 1; + + tlb_prepare_entry_hi(&hi, asid, badvaddr); + tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, + pte->cacheable, pte->pfn); + + /* + * New entry is to be inserted into TLB + */ + cp0_entry_hi_write(hi.value); + if ((badvaddr / PAGE_SIZE) % 2 == 0) { + cp0_entry_lo0_write(lo.value); + cp0_entry_lo1_write(0); + } else { + cp0_entry_lo0_write(0); + cp0_entry_lo1_write(lo.value); } - } - - /* - * Record access to PTE. - */ - pte->a = 1; - - tlb_prepare_entry_hi(&hi, asid, badvaddr); - tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, - pte->pfn); - - /* - * New entry is to be inserted into TLB - */ - cp0_entry_hi_write(hi.value); - if ((badvaddr / PAGE_SIZE) % 2 == 0) { - cp0_entry_lo0_write(lo.value); - cp0_entry_lo1_write(0); - } - else { - cp0_entry_lo0_write(0); - cp0_entry_lo1_write(lo.value); - } - cp0_pagemask_write(TLB_PAGE_MASK_16K); - tlbwr(); - - return; - -fail: - tlb_refill_fail(istate); + cp0_pagemask_write(TLB_PAGE_MASK_16K); + tlbwr(); + } } @@ -155,5 +130,4 @@ entry_hi_t hi; pte_t *pte; - int pfrc; badvaddr = cp0_badvaddr_read(); @@ -168,56 +142,31 @@ index.value = cp0_index_read(); - /* - * Fail if the entry is not in TLB. - */ - if (index.p) { - printf("TLB entry not found.\n"); - goto fail; - } - - pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc); - if (!pte) { - switch (pfrc) { - case AS_PF_FAULT: - goto fail; - break; - case AS_PF_DEFER: - /* - * The page fault came during copy_from_uspace() - * or copy_to_uspace(). - */ - return; - default: - panic("Unexpected pfrc (%d).", pfrc); - } - } - - /* - * Read the faulting TLB entry. - */ - tlbr(); - - /* - * Record access to PTE. - */ - pte->a = 1; - - tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, - pte->pfn); - - /* - * The entry is to be updated in TLB. - */ - if ((badvaddr / PAGE_SIZE) % 2 == 0) - cp0_entry_lo0_write(lo.value); - else - cp0_entry_lo1_write(lo.value); - cp0_pagemask_write(TLB_PAGE_MASK_16K); - tlbwi(); - - return; - -fail: - tlb_invalid_fail(istate); + ASSERT(!index.p); + + pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate); + if (pte) { + /* + * Read the faulting TLB entry. + */ + tlbr(); + + /* + * Record access to PTE. + */ + pte->a = 1; + + tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, + pte->cacheable, pte->pfn); + + /* + * The entry is to be updated in TLB. + */ + if ((badvaddr / PAGE_SIZE) % 2 == 0) + cp0_entry_lo0_write(lo.value); + else + cp0_entry_lo1_write(lo.value); + cp0_pagemask_write(TLB_PAGE_MASK_16K); + tlbwi(); + } } @@ -233,5 +182,4 @@ entry_hi_t hi; pte_t *pte; - int pfrc; badvaddr = cp0_badvaddr_read(); @@ -249,82 +197,32 @@ * Fail if the entry is not in TLB. */ - if (index.p) { - printf("TLB entry not found.\n"); - goto fail; - } - - pte = find_mapping_and_check(badvaddr, PF_ACCESS_WRITE, istate, &pfrc); - if (!pte) { - switch (pfrc) { - case AS_PF_FAULT: - goto fail; - break; - case AS_PF_DEFER: - /* - * The page fault came during copy_from_uspace() - * or copy_to_uspace(). - */ - return; - default: - panic("Unexpected pfrc (%d).", pfrc); - } - } - - /* - * Read the faulting TLB entry. - */ - tlbr(); - - /* - * Record access and write to PTE. - */ - pte->a = 1; - pte->d = 1; - - tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->cacheable, - pte->pfn); - - /* - * The entry is to be updated in TLB. - */ - if ((badvaddr / PAGE_SIZE) % 2 == 0) - cp0_entry_lo0_write(lo.value); - else - cp0_entry_lo1_write(lo.value); - cp0_pagemask_write(TLB_PAGE_MASK_16K); - tlbwi(); - - return; - -fail: - tlb_modified_fail(istate); -} - -void tlb_refill_fail(istate_t *istate) -{ - uintptr_t va = cp0_badvaddr_read(); - - fault_if_from_uspace(istate, "TLB Refill Exception on %p.", - (void *) va); - panic_memtrap(istate, PF_ACCESS_UNKNOWN, va, "TLB Refill Exception."); -} - - -void tlb_invalid_fail(istate_t *istate) -{ - uintptr_t va = cp0_badvaddr_read(); - - fault_if_from_uspace(istate, "TLB Invalid Exception on %p.", - (void *) va); - panic_memtrap(istate, PF_ACCESS_UNKNOWN, va, "TLB Invalid Exception."); -} - -void tlb_modified_fail(istate_t *istate) -{ - uintptr_t va = cp0_badvaddr_read(); - - fault_if_from_uspace(istate, "TLB Modified Exception on %p.", - (void *) va); - panic_memtrap(istate, PF_ACCESS_WRITE, va, "TLB Modified Exception."); + ASSERT(!index.p); + + pte = find_mapping_and_check(badvaddr, PF_ACCESS_WRITE, istate); + if (pte) { + /* + * Read the faulting TLB entry. + */ + tlbr(); + + /* + * Record access and write to PTE. + */ + pte->a = 1; + pte->d = 1; + + tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->w, + pte->cacheable, pte->pfn); + + /* + * The entry is to be updated in TLB. + */ + if ((badvaddr / PAGE_SIZE) % 2 == 0) + cp0_entry_lo0_write(lo.value); + else + cp0_entry_lo1_write(lo.value); + cp0_pagemask_write(TLB_PAGE_MASK_16K); + tlbwi(); + } } @@ -334,12 +232,8 @@ * @param access Access mode that caused the fault. * @param istate Pointer to interrupted state. - * @param pfrc Pointer to variable where as_page_fault() return code - * will be stored. * * @return PTE on success, NULL otherwise. */ -pte_t * -find_mapping_and_check(uintptr_t badvaddr, int access, istate_t *istate, - int *pfrc) +pte_t *find_mapping_and_check(uintptr_t badvaddr, int access, istate_t *istate) { entry_hi_t hi; @@ -348,11 +242,5 @@ hi.value = cp0_entry_hi_read(); - /* - * Handler cannot succeed if the ASIDs don't match. - */ - if (hi.asid != AS->asid) { - printf("EntryHi.asid=%d, AS->asid=%d\n", hi.asid, AS->asid); - return NULL; - } + ASSERT(hi.asid == AS->asid); /* @@ -366,32 +254,18 @@ */ return pte; - } else { - int rc; - - /* - * Mapping not found in page tables. - * Resort to higher-level page fault handler. - */ - switch (rc = as_page_fault(badvaddr, access, istate)) { - case AS_PF_OK: - /* - * The higher-level page fault handler succeeded, - * The mapping ought to be in place. - */ - pte = page_mapping_find(AS, badvaddr, true); - ASSERT(pte && pte->p); - ASSERT(pte->w || access != PF_ACCESS_WRITE); - return pte; - case AS_PF_DEFER: - *pfrc = AS_PF_DEFER; - return NULL; - case AS_PF_FAULT: - *pfrc = AS_PF_FAULT; - return NULL; - default: - panic("Unexpected rc (%d).", rc); - } - - } + } + + /* + * Mapping not found in page tables. + * Resort to higher-level page fault handler. + */ + if (as_page_fault(badvaddr, access, istate) == AS_PF_OK) { + pte = page_mapping_find(AS, badvaddr, true); + ASSERT(pte && pte->p); + ASSERT(pte->w || access != PF_ACCESS_WRITE); + return pte; + } + + return NULL; } Index: kernel/arch/mips64/src/mm/tlb.c =================================================================== --- kernel/arch/mips64/src/mm/tlb.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ kernel/arch/mips64/src/mm/tlb.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -79,6 +79,4 @@ * @param access Access mode that caused the fault. * @param istate Pointer to interrupted state. - * @param pfrc Pointer to variable where as_page_fault() - * return code will be stored. * * @return PTE on success, NULL otherwise. @@ -86,16 +84,10 @@ */ static pte_t *find_mapping_and_check(uintptr_t badvaddr, int access, - istate_t *istate, int *pfrc) + istate_t *istate) { entry_hi_t hi; hi.value = cp0_entry_hi_read(); - /* - * Handler cannot succeed if the ASIDs don't match. - */ - if (hi.asid != AS->asid) { - printf("EntryHi.asid=%d, AS->asid=%d\n", hi.asid, AS->asid); - return NULL; - } + ASSERT(hi.asid == AS->asid); /* @@ -109,32 +101,23 @@ */ return pte; - } else { - int rc; - - /* - * Mapping not found in page tables. - * Resort to higher-level page fault handler. - */ - switch (rc = as_page_fault(badvaddr, access, istate)) { - case AS_PF_OK: - /* - * The higher-level page fault handler succeeded, - * The mapping ought to be in place. - */ - pte = page_mapping_find(AS, badvaddr, true); - ASSERT(pte); - ASSERT(pte->p); - ASSERT((pte->w) || (access != PF_ACCESS_WRITE)); - return pte; - case AS_PF_DEFER: - *pfrc = AS_PF_DEFER; - return NULL; - case AS_PF_FAULT: - *pfrc = AS_PF_FAULT; - return NULL; - default: - panic("Unexpected return code (%d).", rc); - } - } + } + + /* + * Mapping not found in page tables. + * Resort to higher-level page fault handler. + */ + if (as_page_fault(badvaddr, access, istate) == AS_PF_OK) { + /* + * The higher-level page fault handler succeeded, + * The mapping ought to be in place. + */ + pte = page_mapping_find(AS, badvaddr, true); + ASSERT(pte); + ASSERT(pte->p); + ASSERT((pte->w) || (access != PF_ACCESS_WRITE)); + return pte; + } + + return NULL; } @@ -156,31 +139,4 @@ } -static void tlb_refill_fail(istate_t *istate) -{ - uintptr_t va = cp0_badvaddr_read(); - - fault_if_from_uspace(istate, "TLB Refill Exception on %p.", - (void *) va); - panic_memtrap(istate, PF_ACCESS_UNKNOWN, va, "TLB Refill Exception."); -} - -static void tlb_invalid_fail(istate_t *istate) -{ - uintptr_t va = cp0_badvaddr_read(); - - fault_if_from_uspace(istate, "TLB Invalid Exception on %p.", - (void *) va); - panic_memtrap(istate, PF_ACCESS_UNKNOWN, va, "TLB Invalid Exception."); -} - -static void tlb_modified_fail(istate_t *istate) -{ - uintptr_t va = cp0_badvaddr_read(); - - fault_if_from_uspace(istate, "TLB Modified Exception on %p.", - (void *) va); - panic_memtrap(istate, PF_ACCESS_WRITE, va, "TLB Modified Exception."); -} - /** Process TLB Refill Exception. * @@ -196,55 +152,34 @@ mutex_unlock(&AS->lock); - int pfrc; - pte_t *pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, - istate, &pfrc); - if (!pte) { - switch (pfrc) { - case AS_PF_FAULT: - goto fail; - break; - case AS_PF_DEFER: - /* - * The page fault came during copy_from_uspace() - * or copy_to_uspace(). - */ - return; - default: - panic("Unexpected pfrc (%d).", pfrc); + pte_t *pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate); + if (pte) { + /* + * Record access to PTE. + */ + pte->a = 1; + + entry_lo_t lo; + entry_hi_t hi; + + tlb_prepare_entry_hi(&hi, asid, badvaddr); + tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->c, + pte->frame); + + /* + * New entry is to be inserted into TLB + */ + cp0_entry_hi_write(hi.value); + + if ((badvaddr / PAGE_SIZE) % 2 == 0) { + cp0_entry_lo0_write(lo.value); + cp0_entry_lo1_write(0); + } else { + cp0_entry_lo0_write(0); + cp0_entry_lo1_write(lo.value); } - } - - /* - * Record access to PTE. - */ - pte->a = 1; - - entry_lo_t lo; - entry_hi_t hi; - - tlb_prepare_entry_hi(&hi, asid, badvaddr); - tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->c, - pte->frame); - - /* - * New entry is to be inserted into TLB - */ - cp0_entry_hi_write(hi.value); - - if ((badvaddr / PAGE_SIZE) % 2 == 0) { - cp0_entry_lo0_write(lo.value); - cp0_entry_lo1_write(0); - } else { - cp0_entry_lo0_write(0); - cp0_entry_lo1_write(lo.value); - } - - cp0_pagemask_write(TLB_PAGE_MASK_16K); - tlbwr(); - - return; - -fail: - tlb_refill_fail(istate); + + cp0_pagemask_write(TLB_PAGE_MASK_16K); + tlbwr(); + } } @@ -271,60 +206,34 @@ index.value = cp0_index_read(); - /* - * Fail if the entry is not in TLB. - */ - if (index.p) { - printf("TLB entry not found.\n"); - goto fail; - } - - int pfrc; - pte_t *pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, - istate, &pfrc); - if (!pte) { - switch (pfrc) { - case AS_PF_FAULT: - goto fail; - break; - case AS_PF_DEFER: - /* - * The page fault came during copy_from_uspace() - * or copy_to_uspace(). - */ - return; - default: - panic("Unexpected pfrc (%d).", pfrc); - } - } - - /* - * Read the faulting TLB entry. - */ - tlbr(); - - /* - * Record access to PTE. - */ - pte->a = 1; - - entry_lo_t lo; - tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->c, - pte->frame); - - /* - * The entry is to be updated in TLB. - */ - if ((badvaddr / PAGE_SIZE) % 2 == 0) - cp0_entry_lo0_write(lo.value); - else - cp0_entry_lo1_write(lo.value); - - cp0_pagemask_write(TLB_PAGE_MASK_16K); - tlbwi(); - - return; - -fail: - tlb_invalid_fail(istate); + ASSERT(!index.p); + + pte_t *pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate); + if (pte) { + /* + * Read the faulting TLB entry. + */ + tlbr(); + + /* + * Record access to PTE. + */ + pte->a = 1; + + entry_lo_t lo; + tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->c, + pte->frame); + + /* + * The entry is to be updated in TLB. + */ + if ((badvaddr / PAGE_SIZE) % 2 == 0) + cp0_entry_lo0_write(lo.value); + else + cp0_entry_lo1_write(lo.value); + + cp0_pagemask_write(TLB_PAGE_MASK_16K); + tlbwi(); + } + } @@ -351,61 +260,34 @@ index.value = cp0_index_read(); - /* - * Fail if the entry is not in TLB. - */ - if (index.p) { - printf("TLB entry not found.\n"); - goto fail; - } - - int pfrc; - pte_t *pte = find_mapping_and_check(badvaddr, PF_ACCESS_WRITE, - istate, &pfrc); - if (!pte) { - switch (pfrc) { - case AS_PF_FAULT: - goto fail; - break; - case AS_PF_DEFER: - /* - * The page fault came during copy_from_uspace() - * or copy_to_uspace(). - */ - return; - default: - panic("Unexpected pfrc (%d).", pfrc); - } - } - - /* - * Read the faulting TLB entry. - */ - tlbr(); - - /* - * Record access and write to PTE. - */ - pte->a = 1; - pte->d = 1; - - entry_lo_t lo; - tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->c, - pte->frame); - - /* - * The entry is to be updated in TLB. - */ - if ((badvaddr / PAGE_SIZE) % 2 == 0) - cp0_entry_lo0_write(lo.value); - else - cp0_entry_lo1_write(lo.value); - - cp0_pagemask_write(TLB_PAGE_MASK_16K); - tlbwi(); - - return; - -fail: - tlb_modified_fail(istate); + ASSERT(!index.p); + + pte_t *pte = find_mapping_and_check(badvaddr, PF_ACCESS_WRITE, istate); + if (pte) { + /* + * Read the faulting TLB entry. + */ + tlbr(); + + /* + * Record access and write to PTE. + */ + pte->a = 1; + pte->d = 1; + + entry_lo_t lo; + tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->c, + pte->frame); + + /* + * The entry is to be updated in TLB. + */ + if ((badvaddr / PAGE_SIZE) % 2 == 0) + cp0_entry_lo0_write(lo.value); + else + cp0_entry_lo1_write(lo.value); + + cp0_pagemask_write(TLB_PAGE_MASK_16K); + tlbwi(); + } } Index: kernel/arch/ppc32/src/mm/pht.c =================================================================== --- kernel/arch/ppc32/src/mm/pht.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ kernel/arch/ppc32/src/mm/pht.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -49,6 +49,4 @@ * @param access Access mode that caused the fault. * @param istate Pointer to interrupted state. - * @param pfrc Pointer to variable where as_page_fault() return code - * will be stored. * * @return PTE on success, NULL otherwise. @@ -56,5 +54,5 @@ */ static pte_t *find_mapping_and_check(as_t *as, uintptr_t badvaddr, int access, - istate_t *istate, int *pfrc) + istate_t *istate) { /* @@ -68,38 +66,20 @@ */ return pte; - } else { + } + /* + * Mapping not found in page tables. + * Resort to higher-level page fault handler. + */ + if (as_page_fault(badvaddr, access, istate) == AS_PF_OK) { /* - * Mapping not found in page tables. - * Resort to higher-level page fault handler. + * The higher-level page fault handler succeeded, + * The mapping ought to be in place. */ - int rc = as_page_fault(badvaddr, access, istate); - switch (rc) { - case AS_PF_OK: - /* - * The higher-level page fault handler succeeded, - * The mapping ought to be in place. - */ - pte = page_mapping_find(as, badvaddr, true); - ASSERT((pte) && (pte->present)); - *pfrc = 0; - return pte; - case AS_PF_DEFER: - *pfrc = rc; - return NULL; - case AS_PF_FAULT: - *pfrc = rc; - return NULL; - default: - panic("Unexpected rc (%d).", rc); - } - } -} - -static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate) -{ - fault_if_from_uspace(istate, "PHT Refill Exception on %p.", - (void *) badvaddr); - panic_memtrap(istate, PF_ACCESS_UNKNOWN, badvaddr, - "PHT Refill Exception."); + pte = page_mapping_find(as, badvaddr, true); + ASSERT((pte) && (pte->present)); + return pte; + } + + return NULL; } @@ -202,27 +182,12 @@ badvaddr = istate->pc; - int pfrc; pte_t *pte = find_mapping_and_check(AS, badvaddr, - PF_ACCESS_READ /* FIXME */, istate, &pfrc); - - if (!pte) { - switch (pfrc) { - case AS_PF_FAULT: - pht_refill_fail(badvaddr, istate); - return; - case AS_PF_DEFER: - /* - * The page fault came during copy_from_uspace() - * or copy_to_uspace(). - */ - return; - default: - panic("Unexpected pfrc (%d).", pfrc); - } - } - - /* Record access to PTE */ - pte->accessed = 1; - pht_insert(badvaddr, pte); + PF_ACCESS_READ /* FIXME */, istate); + + if (pte) { + /* Record access to PTE */ + pte->accessed = 1; + pht_insert(badvaddr, pte); + } } Index: kernel/arch/sparc64/src/mm/sun4u/tlb.c =================================================================== --- kernel/arch/sparc64/src/mm/sun4u/tlb.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ kernel/arch/sparc64/src/mm/sun4u/tlb.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -58,10 +58,4 @@ static void dtlb_pte_copy(pte_t *, size_t, bool); static void itlb_pte_copy(pte_t *, size_t); -static void do_fast_instruction_access_mmu_miss_fault(istate_t *, uintptr_t, - const char *); -static void do_fast_data_access_mmu_miss_fault(istate_t *, tlb_tag_access_reg_t, - const char *); -static void do_fast_data_access_protection_fault(istate_t *, - tlb_tag_access_reg_t, const char *); const char *context_encoding[] = { @@ -222,9 +216,5 @@ * handler. */ - if (as_page_fault(page_16k, PF_ACCESS_EXEC, istate) == - AS_PF_FAULT) { - do_fast_instruction_access_mmu_miss_fault(istate, - istate->tpc, __func__); - } + as_page_fault(page_16k, PF_ACCESS_EXEC, istate); } } @@ -256,12 +246,10 @@ if (!tag.vpn) { /* NULL access in kernel */ - do_fast_data_access_mmu_miss_fault(istate, tag, - "Dereferencing NULL pointer."); + panic("NULL pointer dereference."); } else if (page_8k >= end_of_identity) { /* Kernel non-identity. */ as = AS_KERNEL; } else { - do_fast_data_access_mmu_miss_fault(istate, tag, - "Unexpected kernel page fault."); + panic("Unexpected kernel page fault."); } } @@ -283,9 +271,5 @@ * handler. */ - if (as_page_fault(page_16k, PF_ACCESS_READ, istate) == - AS_PF_FAULT) { - do_fast_data_access_mmu_miss_fault(istate, tag, - __func__); - } + as_page_fault(page_16k, PF_ACCESS_READ, istate); } } @@ -332,9 +316,5 @@ * handler. */ - if (as_page_fault(page_16k, PF_ACCESS_WRITE, istate) == - AS_PF_FAULT) { - do_fast_data_access_protection_fault(istate, tag, - __func__); - } + as_page_fault(page_16k, PF_ACCESS_WRITE, istate); } } @@ -428,33 +408,4 @@ #endif - -void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, - uintptr_t va, const char *str) -{ - fault_if_from_uspace(istate, "%s, address=%p.", str, (void *) va); - panic_memtrap(istate, PF_ACCESS_EXEC, va, str); -} - -void do_fast_data_access_mmu_miss_fault(istate_t *istate, - tlb_tag_access_reg_t tag, const char *str) -{ - uintptr_t va; - - va = tag.vpn << MMU_PAGE_WIDTH; - fault_if_from_uspace(istate, "%s, page=%p (asid=%u).", str, - (void *) va, tag.context); - panic_memtrap(istate, PF_ACCESS_UNKNOWN, va, str); -} - -void do_fast_data_access_protection_fault(istate_t *istate, - tlb_tag_access_reg_t tag, const char *str) -{ - uintptr_t va; - - va = tag.vpn << MMU_PAGE_WIDTH; - fault_if_from_uspace(istate, "%s, page=%p (asid=%u).", str, - (void *) va, tag.context); - panic_memtrap(istate, PF_ACCESS_WRITE, va, str); -} void describe_dmmu_fault(void) Index: kernel/arch/sparc64/src/mm/sun4v/tlb.c =================================================================== --- kernel/arch/sparc64/src/mm/sun4v/tlb.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ kernel/arch/sparc64/src/mm/sun4v/tlb.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -62,10 +62,4 @@ static void itlb_pte_copy(pte_t *); static void dtlb_pte_copy(pte_t *, bool); -static void do_fast_instruction_access_mmu_miss_fault(istate_t *, uintptr_t, - const char *); -static void do_fast_data_access_mmu_miss_fault(istate_t *, uint64_t, - const char *); -static void do_fast_data_access_protection_fault(istate_t *, - uint64_t, const char *); /* @@ -235,8 +229,5 @@ * handler. */ - if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) { - do_fast_instruction_access_mmu_miss_fault(istate, - istate->tpc, __func__); - } + as_page_fault(va, PF_ACCESS_EXEC, istate); } } @@ -264,9 +255,7 @@ if (va == 0) { /* NULL access in kernel */ - do_fast_data_access_mmu_miss_fault(istate, page_and_ctx, - __func__); + panic("NULL pointer dereference."); } - do_fast_data_access_mmu_miss_fault(istate, page_and_ctx, "Unexpected " - "kernel page fault."); + panic("Unexpected kernel page fault."); } @@ -287,8 +276,5 @@ * handler. */ - if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) { - do_fast_data_access_mmu_miss_fault(istate, page_and_ctx, - __func__); - } + as_page_fault(va, PF_ACCESS_READ, istate); } } @@ -329,8 +315,5 @@ * handler. */ - if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) { - do_fast_data_access_protection_fault(istate, page_and_ctx, - __func__); - } + as_page_fault(va, PF_ACCESS_WRITE, istate); } } @@ -346,30 +329,4 @@ } -void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, uintptr_t va, - const char *str) -{ - fault_if_from_uspace(istate, "%s, address=%p.", str, - (void *) va); - panic_memtrap(istate, PF_ACCESS_EXEC, va, str); -} - -void do_fast_data_access_mmu_miss_fault(istate_t *istate, - uint64_t page_and_ctx, const char *str) -{ - fault_if_from_uspace(istate, "%s, page=%p (asid=%" PRId64 ").", str, - (void *) DMISS_ADDRESS(page_and_ctx), DMISS_CONTEXT(page_and_ctx)); - panic_memtrap(istate, PF_ACCESS_UNKNOWN, DMISS_ADDRESS(page_and_ctx), - str); -} - -void do_fast_data_access_protection_fault(istate_t *istate, - uint64_t page_and_ctx, const char *str) -{ - fault_if_from_uspace(istate, "%s, page=%p (asid=%" PRId64 ").", str, - (void *) DMISS_ADDRESS(page_and_ctx), DMISS_CONTEXT(page_and_ctx)); - panic_memtrap(istate, PF_ACCESS_WRITE, DMISS_ADDRESS(page_and_ctx), - str); -} - /** * Describes the exact condition which caused the last DMMU fault. Index: kernel/genarch/Makefile.inc =================================================================== --- kernel/genarch/Makefile.inc (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ kernel/genarch/Makefile.inc (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -106,4 +106,9 @@ endif +ifeq ($(CONFIG_AMDM37X_UART),y) + GENARCH_SOURCES += \ + genarch/src/drivers/amdm37x_uart/amdm37x_uart.c +endif + ifeq ($(CONFIG_VIA_CUDA),y) GENARCH_SOURCES += \ Index: kernel/genarch/include/drivers/amdm37x_dispc/amdm37x_dispc.h =================================================================== --- kernel/genarch/include/drivers/amdm37x_dispc/amdm37x_dispc.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) +++ kernel/genarch/include/drivers/amdm37x_dispc/amdm37x_dispc.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -0,0 +1,394 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** @addtogroup genarch + * @{ + */ +/** + * @file + * @brief Texas Instruments AM/DM37x SDRAM Memory Scheduler. + */ + +#ifndef KERN_AMDM37x_DISPC_H_ +#define KERN_AMDM37x_DISPC_H_ + +/* AMDM37x TRM p. 1813 */ +#define AMDM37x_DISPC_BASE_ADDRESS 0x48050400 +#define AMDM37x_DISPC_SIZE 1024 + +#define __paddname(line) PADD32_ ## line +#define _paddname(line) __paddname(line) +#define PADD32(count) uint32_t _paddname(__LINE__)[count] + +#include + +typedef struct { + const ioport32_t revision; +#define AMDM37X_DISPC_REVISION_MASK 0xff + + PADD32(3); + ioport32_t sysconfig; +#define AMDM37X_DISPC_SYSCONFIG_AUTOIDLE_FLAG (1 << 0) +#define AMDM37X_DISPC_SYSCONFIG_SOFTRESET_FLAG (1 << 1) +#define AMDM37X_DISPC_SYSCONFIG_ENWAKEUP_FLAG (1 << 2) +#define AMDM37X_DISPC_SYSCONFIG_SIDLEMODE_MASK 0x3 +#define AMDM37X_DISPC_SYSCONFIG_SIDLEMODE_SHIFT 3 +#define AMDM37X_DISPC_SYSCONFIG_CLOCKACTIVITY_MASK 0x3 +#define AMDM37X_DISPC_SYSCONFIG_CLOCKACTIVITY_SHIFT 8 +#define AMDM37X_DISPC_SYSCONFIG_MIDLEMODE_MASK 0x3 +#define AMDM37X_DISPC_SYSCONFIG_MIDLEMODE_SHIFT 12 + + const ioport32_t sysstatus; +#define AMDM37X_DISPC_SYSSTATUS_RESETDONE_FLAG (1 << 0) + + ioport32_t irqstatus; + ioport32_t irqenable; +#define AMDM37X_DISPC_IRQ_FRAMEDONE_FLAG (1 << 0) +#define AMDM37X_DISPC_IRQ_VSYNC_FLAG (1 << 1) +#define AMDM37X_DISPC_IRQ_EVSYNCEVEN_FLAG (1 << 2) +#define AMDM37X_DISPC_IRQ_EVSYNCODD_FLAG (1 << 3) +#define AMDM37X_DISPC_IRQ_ACBIASCOUNTSTATUS_FLAG (1 << 4) +#define AMDM37X_DISPC_IRQ_PROGRAMMEDLINENUMBER_FLAG (1 << 5) +#define AMDM37X_DISPC_IRQ_GFXFIFOUNDERFLOW_FLAG (1 << 6) +#define AMDM37X_DISPC_IRQ_GFXENDWINDOW_FLAG (1 << 7) +#define AMDM37X_DISPC_IRQ_PALETTEGAMMALOADING_FLAG (1 << 8) +#define AMDM37X_DISPC_IRQ_OPCERROR_FLAG (1 << 9) +#define AMDM37X_DISPC_IRQ_VID1FIFOUNDERFLOW_FLAG (1 << 10) +#define AMDM37X_DISPC_IRQ_VID1ENDWINDOW_FLAG (1 << 11) +#define AMDM37X_DISPC_IRQ_VID2FIFOUNDERFLOW_FLAG (1 << 12) +#define AMDM37X_DISPC_IRQ_VID2ENDWINDOW_FLAG (1 << 13) +#define AMDM37X_DISPC_IRQ_SYNCLOST_FLAG (1 << 14) +#define AMDM37X_DISPC_IRQ_SYNCLOSTDIGITAL_FLAG (1 << 15) +#define AMDM37X_DISPC_IRQ_WAKEUP_FLAG (1 << 16) + + PADD32(8); + ioport32_t control; +#define AMDM37X_DISPC_CONTROL_LCD_ENABLE_FLAG (1 << 0) +#define AMDM37X_DISPC_CONTROL_DIGITAL_ENABLE_FLAG (1 << 1) +#define AMDM37X_DISPC_CONTROL_MONOCOLOR_FLAG (1 << 2) +#define AMDM37X_DISPC_CONTROL_STNTFT_FLAG (1 << 3) +#define AMDM37X_DISPC_CONTROL_M8B_FLAG (1 << 4) +#define AMDM37X_DISPC_CONTROL_GOLCD_FLAG (1 << 5) +#define AMDM37X_DISPC_CONTROL_GODIGITAL_FLAG (1 << 6) +#define AMDM37X_DISPC_CONTROL_STDITHERENABLE_FLAG (1 << 7) +#define AMDM37X_DISPC_CONTROL_TFTDATALINES_MASK 0x3 +#define AMDM37X_DISPC_CONTROL_TFTDATALINES_SHIFT 8 +#define AMDM37X_DISPC_CONTROL_TFTDATALINES_12B 0 +#define AMDM37X_DISPC_CONTROL_TFTDATALINES_16B 1 +#define AMDM37X_DISPC_CONTROL_TFTDATALINES_18B 2 +#define AMDM37X_DISPC_CONTROL_TFTDATALINES_24B 3 +#define AMDM37X_DISPC_CONTROL_STALLMODE_FLAG (1 << 11) +#define AMDM37X_DISPC_CONTROL_OVERLAYOPTIMIZATION_FLAG (1 << 12) +#define AMDM37X_DISPC_CONTROL_GPIN0_FLAG (1 << 13) +#define AMDM37X_DISPC_CONTROL_GPIN1_FLAG (1 << 14) +#define AMDM37X_DISPC_CONTROL_GPOUT0_FLAG (1 << 15) +#define AMDM37X_DISPC_CONTROL_GPOUT1_FLAG (1 << 16) +#define AMDM37X_DISPC_CONTROL_HT_MASK 0x7 +#define AMDM37X_DISPC_CONTROL_HT_SHIFT 17 +#define AMDM37X_DISPC_CONTROL_TDMENABLE_FLAG (1 << 20) +#define AMDM37X_DISPC_CONTROL_TDMPARALLELMODE_MASK 0x3 +#define AMDM37X_DISPC_CONTROL_TDMPARELLELMODE_SHIFT 21 +#define AMDM37X_DISPC_CONTROL_TDMCYCLEFORMAT_MASK 0x3 +#define AMDM37X_DISPC_CONTROL_TDMCYCLEFORMAT_SHIFT 23 +#define AMDM37X_DISPC_CONTROL_TDMUNUSEDBITS_MASK 0x3 +#define AMDM37X_DISPC_CONTROL_TDMUNUSEDBITS_SHIFT 25 +#define AMDM37X_DISPC_CONTROL_PCKFREEENABLE_FLAG (1 << 27) +#define AMDM37X_DISPC_CONTROL_LCDENABLESIGNAL_FLAG (1 << 28) +#define AMDM37X_DISPC_CONTROL_KCDENABLEPOL_FLAG (1 << 29) +#define AMDM37X_DISPC_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_MASK 0x3 +#define AMDM37X_DISPC_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_SHIFT 30 + + ioport32_t config; +#define AMDM37X_DISPC_CONFIG_PIXELGATED_FLAG (1 << 0) +#define AMDM37X_DISPC_CONFIG_LOADMODE_MASK 0x3 +#define AMDM37X_DISPC_CONFIG_LOADMODE_SHIFT 1 +#define AMDM37X_DISPC_CONFIG_LOADMODE_PGDATAEVERYFRAME 0x0 +#define AMDM37X_DISPC_CONFIG_LOADMODE_PGUSER 0x1 +#define AMDM37X_DISPC_CONFIG_LOADMODE_DATAEVERYFRAME 0x2 +#define AMDM37X_DISPC_CONFIG_LOADMODE_PGDFIRSTFRAME 0x3 +#define AMDM37X_DISPC_CONFIG_PALETTEGAMMATABLE_FLAG (1 << 3) +#define AMDM37X_DISPC_CONFIG_PIXELDATAGATED_FLAG (1 << 4) +#define AMDM37X_DISPC_CONFIG_PIXELCLOCKGATED_FLAG (1 << 5) +#define AMDM37X_DISPC_CONFIG_HSYNCGATED_FLAG (1 << 6) +#define AMDM37X_DISPC_CONFIG_VSYNCGATED_FLAG (1 << 7) +#define AMDM37X_DISPC_CONFIG_ACBIASGATED_FLAG (1 << 8) +#define AMDM37X_DISPC_CONFIG_FUNCGATED_FLAG (1 << 9) +#define AMDM37X_DISPC_CONFIG_TCKLCDENABLE_FLAG (1 << 10) +#define AMDM37X_DISPC_CONFIG_TCKLCDSELECTION_FLAG (1 << 11) +#define AMDM37X_DISPC_CONFIG_TCKDIGENABLE_FLAG (1 << 12) +#define AMDM37X_DISPC_CONFIG_TCKDIGSELECTION_FLAG (1 << 13) +#define AMDM37X_DISPC_CONFIG_FIFOMERGE_FLAG (1 << 14) +#define AMDM37X_DISPC_CONFIG_CPR_FLAG (1 << 15) +#define AMDM37X_DISPC_CONFIG_FIFOHANDCHECK_FLAG (1 << 16) +#define AMDM37X_DISPC_CONFIG_FIFOFILLING_FLAG (1 << 17) +#define AMDM37X_DISPC_CONFIG_LCDPALPHABLENDERENABLDE_FLAG (1 << 18) +#define AMDM37X_DISPC_CONFIG_TVALPHABLENDERENABLE_FLAG (1 << 19) + + PADD32(1); + ioport32_t default_color[2]; + ioport32_t trans_color[2]; +#define AMDM37X_DISPC_COLOR_MASK 0xffffff + + const ioport32_t line_status; + ioport32_t line_number; +#define AMDM37X_DISPC_LINE_NUMBER_MASK 0x3ff + + ioport32_t timing_h; +#define AMDM37X_DISPC_TIMING_H_HSW_MASK 0xff +#define AMDM37X_DISPC_TIMING_H_HSW_SHIFT 0 +#define AMDM37X_DISPC_TIMING_H_HFP_MASK 0xfff +#define AMDM37X_DISPC_TIMING_H_HFP_SHIFT 8 +#define AMDM37X_DISPC_TIMING_H_HBP_MASK 0xfff +#define AMDM37X_DISPC_TIMING_H_HBP_SHIFT 20 + + ioport32_t timing_v; +#define AMDM37X_DISPC_TIMING_V_VSW_MASK 0xff +#define AMDM37X_DISPC_TIMING_V_VSW_SHIFT 0 +#define AMDM37X_DISPC_TIMING_V_VFP_MASK 0xfff +#define AMDM37X_DISPC_TIMING_V_VFP_SHIFT 8 +#define AMDM37X_DISPC_TIMING_V_VBP_MASK 0xfff +#define AMDM37X_DISPC_TIMING_V_VBP_SHIFT 20 + + ioport32_t pol_freq; +#define AMDM37X_DISPC_POL_FREQ_ACB_MASK 0xff +#define AMDM37X_DISPC_POL_FREQ_ACB_SHIFT 0 +#define AMDM37X_DISPC_POL_FREQ_ACBI_MASK 0xf +#define AMDM37X_DISPC_POL_FREQ_ACBI_SHIFT 8 +#define AMDM37X_DISPC_POL_FREQ_IVS_FLAG (1 << 12) +#define AMDM37X_DISPC_POL_FREQ_IHS_FLAG (1 << 13) +#define AMDM37X_DISPC_POL_FREQ_IPC_FLAG (1 << 14) +#define AMDM37X_DISPC_POL_FREQ_IEO_FLAG (1 << 15) +#define AMDM37X_DISPC_POL_FREQ_RF_FLAG (1 << 16) +#define AMDM37X_DISPC_POL_FREQ_ONOFF_FLAG (1 << 17) + + ioport32_t divisor; +#define AMDM37X_DISPC_DIVISOR_PCD_MASK 0xff +#define AMDM37X_DISPC_DIVISOR_PCD_SHIFT 0 +#define AMDM37X_DISPC_DIVISOR_LCD_MASK 0xff +#define AMDM37X_DISPC_DIVISOR_LCD_SHIFT 16 + + ioport32_t global_alpha; +#define AMDM37X_DISPC_GLOBAL_ALPHA_GFXGLOBALALPHA_MASK 0xff +#define AMDM37X_DISPC_GLOBAL_ALPHA_GFXGLOBALALPHA_SHIFT 0 +#define AMDM37X_DISPC_GLOBAL_ALPHA_VID2GLOBALALPHA_MASK 0xff +#define AMDM37X_DISPC_GLOBAL_ALPHA_VID2GLOBALALPHA_SHIFT 16 + + ioport32_t size_dig; + ioport32_t size_lcd; + + struct { + ioport32_t ba[2]; + ioport32_t position; +#define AMDM37X_DISPC_GFX_POSITION_GFXPOSX_MASK 0x7ff +#define AMDM37X_DISPC_GFX_POSITION_GFXPOSX_SHIFT 0 +#define AMDM37X_DISPC_GFX_POSITION_GFXPOSY_MASK 0x7ff +#define AMDM37X_DISPC_GFX_POSITION_GFXPOSY_SHIFT 16 + + ioport32_t size; +#define AMDM37X_DISPC_SIZE_WIDTH_MASK 0x7ff +#define AMDM37X_DISPC_SIZE_WIDTH_SHIFT 0 +#define AMDM37X_DISPC_SIZE_HEIGHT_MASK 0x7ff +#define AMDM37X_DISPC_SIZE_HEIGHT_SHIFT 16 + + PADD32(4); + ioport32_t attributes; +#define AMDM37X_DISPC_GFX_ATTRIBUTES_ENABLE_FLAG (1 << 0) +#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_MASK 0xf +#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_SHIFT 1 +#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_ARGB16 0x5 +#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB16 0x6 +#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB24_32 0x8 +#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB24 0x9 +#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_ARGB 0xc +#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGBA 0xd +#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGBX 0xe +#define AMDM37X_DISPC_GFX_ATTRIBUTES_REPLICATIONENABLE_FLAG (1 << 5) +#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXBURSTSIZE_MASK 0x3 +#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXBURSTSIZE_SHIFT 6 +#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXCHANNELOUT_FLAG (1 << 8) +#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXNIBBLEMODE_FLAG (1 << 9) +#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXENDIANNES_FLAG (1 << 10) +#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXFIFOPRELOAD_FLAG (1 << 11) +#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXROTATION_MASK 0x3 +#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXROTATION_SHIFT 12 +#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXARBITRATION_FLAG (1 << 14) +#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXSELFREFRESH_FLAG (1 << 15) +#define AMDM37X_DISPC_GFX_ATTRIBUTES_PREMULTIALPHA_FLAG (1 << 28) + + + ioport32_t fifo_threshold; + const ioport32_t fifo_size_status; + ioport32_t row_inc; + ioport32_t pixel_inc; + ioport32_t window_skip; + ioport32_t table_ba; + } gfx; + + struct { + ioport32_t ba[2]; + ioport32_t position; + ioport32_t size; + ioport32_t attributes; + ioport32_t fifo_threshold; + const ioport32_t fifo_size_status; + ioport32_t row_inc; + ioport32_t pixel_inc; + ioport32_t fir; + ioport32_t picture_size; + ioport32_t accui[2]; + struct { + ioport32_t hi; + ioport32_t hvi; + } fir_coef[8]; + ioport32_t conv_coef[5]; + PADD32(2); + } vid[2]; + /* 0x1d4 */ + ioport32_t data_cycle[3]; + /* 0x1e0 */ + ioport32_t vid_fir_coef_v[8]; + /* 0x200 */ + PADD32(8); + /* 0x220 */ + ioport32_t cpr_coef_r; + ioport32_t cpr_coef_g; + ioport32_t cpr_coef_b; + ioport32_t gfx_preload; + + /* 0x230 */ + ioport32_t vid_preload[2]; + +} __attribute__((packed)) amdm37x_dispc_regs_t; + + +static inline void amdm37x_dispc_setup_fb(amdm37x_dispc_regs_t *regs, + unsigned x, unsigned y, unsigned bpp, uintptr_t pa) +{ + ASSERT(regs); + /* Init sequence for dispc is in chapter 7.6.5.1.4 p. 1810, + * no idea what parts of that work. */ + + /* Disable all interrupts */ + regs->irqenable = 0; + + /* Pixel format specifics*/ + uint32_t attrib_pixel_format = 0; + uint32_t control_data_lanes = 0; + switch (bpp) + { + case 32: + attrib_pixel_format = AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGBX; + control_data_lanes = AMDM37X_DISPC_CONTROL_TFTDATALINES_24B; + break; + case 24: + attrib_pixel_format = AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB24; + control_data_lanes = AMDM37X_DISPC_CONTROL_TFTDATALINES_24B; + break; + case 16: + attrib_pixel_format = AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB16; + control_data_lanes = AMDM37X_DISPC_CONTROL_TFTDATALINES_16B; + break; + default: + ASSERT(false); + } + + /* Prepare sizes */ + const uint32_t size_reg = + (((x - 1) & AMDM37X_DISPC_SIZE_WIDTH_MASK) + << AMDM37X_DISPC_SIZE_WIDTH_SHIFT) | + (((y - 1) & AMDM37X_DISPC_SIZE_HEIGHT_MASK) + << AMDM37X_DISPC_SIZE_HEIGHT_SHIFT); + + /* modes taken from u-boot, for 1024x768 */ + // TODO replace magic values with actual correct values +// regs->timing_h = 0x1a4024c9; +// regs->timing_v = 0x02c00509; +// regs->pol_freq = 0x00007028; +// regs->divisor = 0x00010001; + + /* setup output */ + regs->size_lcd = size_reg; + regs->size_dig = size_reg; + + /* Nice blue default color */ + regs->default_color[0] = 0x0000ff; + regs->default_color[1] = 0x0000ff; + + /* Setup control register */ + uint32_t control = 0 | + AMDM37X_DISPC_CONTROL_PCKFREEENABLE_FLAG | + (control_data_lanes << AMDM37X_DISPC_CONTROL_TFTDATALINES_SHIFT) | + AMDM37X_DISPC_CONTROL_GPOUT0_FLAG | + AMDM37X_DISPC_CONTROL_GPOUT1_FLAG; + regs->control = control; + + /* No gamma stuff only data */ + uint32_t config = (AMDM37X_DISPC_CONFIG_LOADMODE_DATAEVERYFRAME + << AMDM37X_DISPC_CONFIG_LOADMODE_SHIFT); + regs->config = config; + + + /* Set framebuffer base address */ + regs->gfx.ba[0] = pa; + regs->gfx.ba[1] = pa; + regs->gfx.position = 0; + + /* Setup fb size */ + regs->gfx.size = size_reg; + + /* Set pixel format */ + uint32_t attribs = 0 | + (attrib_pixel_format << AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_SHIFT); + regs->gfx.attributes = attribs; + + /* 0x03ff03c0 is the default */ + regs->gfx.fifo_threshold = 0x03ff03c0; + /* This value should be stride - width, 1 means next pixel i.e. + * stride == width */ + regs->gfx.row_inc = 1; + /* number of bytes to next pixel in BPP multiples */ + regs->gfx.pixel_inc = 1; + /* only used if video is played over fb */ + regs->gfx.window_skip = 0; + /* Gamma and palette table */ + regs->gfx.table_ba = 0; + + /* enable frame buffer graphics */ + regs->gfx.attributes |= AMDM37X_DISPC_GFX_ATTRIBUTES_ENABLE_FLAG; + /* Update register values */ + regs->control |= AMDM37X_DISPC_CONTROL_GOLCD_FLAG; + regs->control |= AMDM37X_DISPC_CONTROL_GODIGITAL_FLAG; + /* Enable output */ + regs->control |= AMDM37X_DISPC_CONTROL_LCD_ENABLE_FLAG; + regs->control |= AMDM37X_DISPC_CONTROL_DIGITAL_ENABLE_FLAG; +} + + +#endif +/** + * @} + */ Index: kernel/genarch/include/drivers/amdm37x_gpt/amdm37x_gpt.h =================================================================== --- kernel/genarch/include/drivers/amdm37x_gpt/amdm37x_gpt.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) +++ kernel/genarch/include/drivers/amdm37x_gpt/amdm37x_gpt.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -0,0 +1,255 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** @addtogroup genarch + * @{ + */ +/** + * @file + * @brief Texas Instruments AM/DM37x MPU general purpose timer driver. + */ + +#ifndef KERN_AMDM37x_GPT_H_ +#define KERN_AMDM37x_GPT_H_ + +#include +#include + +/* AMDM37x TRM p. 2740 */ +#define AMDM37x_GPT1_BASE_ADDRESS 0x48318000 +#define AMDM37x_GPT1_SIZE 4096 +#define AMDM37x_GPT1_IRQ 37 +#define AMDM37x_GPT2_BASE_ADDRESS 0x49032000 +#define AMDM37x_GPT2_SIZE 4096 +#define AMDM37x_GPT2_IRQ 38 +#define AMDM37x_GPT3_BASE_ADDRESS 0x49034000 +#define AMDM37x_GPT3_SIZE 4096 +#define AMDM37x_GPT3_IRQ 39 +#define AMDM37x_GPT4_BASE_ADDRESS 0x49036000 +#define AMDM37x_GPT4_SIZE 4096 +#define AMDM37x_GPT4_IRQ 40 +#define AMDM37x_GPT5_BASE_ADDRESS 0x49038000 +#define AMDM37x_GPT5_SIZE 4096 +#define AMDM37x_GPT5_IRQ 41 +#define AMDM37x_GPT6_BASE_ADDRESS 0x4903a000 +#define AMDM37x_GPT6_SIZE 4096 +#define AMDM37x_GPT6_IRQ 42 +#define AMDM37x_GPT7_BASE_ADDRESS 0x4903c000 +#define AMDM37x_GPT7_SIZE 4096 +#define AMDM37x_GPT7_IRQ 43 +#define AMDM37x_GPT8_BASE_ADDRESS 0x4903e000 +#define AMDM37x_GPT8_SIZE 4096 +#define AMDM37x_GPT8_IRQ 44 +#define AMDM37x_GPT9_BASE_ADDRESS 0x49040000 +#define AMDM37x_GPT9_SIZE 4096 +#define AMDM37x_GPT9_IRQ 45 +#define AMDM37x_GPT10_BASE_ADDRESS 0x48086000 +#define AMDM37x_GPT10_SIZE 4096 +#define AMDM37x_GPT10_IRQ 46 +#define AMDM37x_GPT11_BASE_ADDRESS 0x48088000 +#define AMDM37x_GPT11_SIZE 4096 +#define AMDM37x_GPT11_IRQ 47 + + +/** GPT register map AMDM37x TRM p. 2740 */ +typedef struct { + /** IP revision */ + const ioport32_t tidr; +#define AMDM37x_GPT_TIDR_MINOR_MASK (0xf) +#define AMDM37x_GPT_TIDR_MINOR_SHIFT (0) +#define AMDM37x_GPT_TIDR_MAJOR_MASK (0xf) +#define AMDM37x_GPT_TIDR_MAJOR_SHIFT (4) + uint32_t padd0_[3]; + + /** L4 Interface parameters */ + ioport32_t tiocp_cfg; +#define AMDM37x_GPT_TIOCP_CFG_AUTOIDLE_FLAG (1 << 0) +#define AMDM37x_GPT_TIOCP_CFG_SOFTRESET_FLAG (1 << 1) +#define AMDM37x_GPT_TIOCP_CFG_ENWAKEUP_FLAG (1 << 2) +#define AMDM37x_GPT_TIOCP_CFG_IDLEMODE_MASK (0x3) +#define AMDM37x_GPT_TIOCP_CFG_IDLEMODE_SHIFT (3) +#define AMDM37x_GPT_TIOCP_CFG_EMUFREE_FlAG (1 << 5) +#define AMDM37x_GPT_TIOCP_CFG_CLOCKACTIVITY_MASK (0x3) +#define AMDM37x_GPT_TIOCP_CFG_CLOCKACTIVITY_SHIFT (8) + + /** Module status information, excluding irq */ + const ioport32_t tistat; +#define AMDM37x_GPT_TISTAT_RESET_DONE_FLAG (1 << 0) + + /** Interrupt status register */ + ioport32_t tisr; +#define AMDM37x_GPT_TISR_MAT_IRQ_FLAG (1 << 0) +#define AMDM37x_GPT_TISR_OVF_IRQ_FLAG (1 << 1) +#define AMDM37x_GPT_TISR_TCAR_IRQ_FLAG (1 << 2) + + /* Interrupt enable register */ + ioport32_t tier; +#define AMDM37x_GPT_TIER_MAT_IRQ_FLAG (1 << 0) +#define AMDM37x_GPT_TIER_OVF_IRQ_FLAG (1 << 1) +#define AMDM37x_GPT_TIER_TCAR_IRQ_FLAG (1 << 2) + + /** Wakeup enable register */ + ioport32_t twer; +#define AMDM37x_GPT_TWER_MAT_IRQ_FLAG (1 << 0) +#define AMDM37x_GPT_TWER_OVF_IRQ_FLAG (1 << 1) +#define AMDM37x_GPT_TWER_TCAR_IRQ_FLAG (1 << 2) + + /** Optional features control register */ + ioport32_t tclr; +#define AMDM37x_GPT_TCLR_ST_FLAG (1 << 0) +#define AMDM37x_GPT_TCLR_AR_FLAG (1 << 1) +#define AMDM37x_GPT_TCLR_PTV_MASK (0x7) +#define AMDM37x_GPT_TCLR_PTV_SHIFT (2) +#define AMDM37x_GPT_TCLR_PRE_FLAG (1 << 5) +#define AMDM37x_GPT_TCLR_CE_FLAG (1 << 6) +#define AMDM37x_GPT_TCLR_SCPWM (1 << 7) +#define AMDM37x_GPT_TCLR_TCM_MASK (0x3) +#define AMDM37x_GPT_TCLR_TCM_SHIFT (8) +#define AMDM37x_GPT_TCLR_TRG_MASK (0x3) +#define AMDM37x_GPT_TCLR_TRG_SHIFT (10) +#define AMDM37x_GPT_TCLR_PT_FLAG (1 << 12) +#define AMDM37x_GPT_TCLR_CAPT_MODE_FLAG (1 << 13) +#define AMDM37x_GPT_TCLR_GPO_CFG_FLAG (1 << 14) + + /** Value of timer counter */ + ioport32_t tccr; + + /** Timer load register */ + ioport32_t tldr; + + /** Timer trigger register */ + ioport32_t ttgr; + + /** Write-posted pending register */ + const ioport32_t twps; +#define AMDM37x_GPT_TWPS_TCLR_FLAG (1 << 0) +#define AMDM37x_GPT_TWPS_TCRR_FLAG (1 << 1) +#define AMDM37x_GPT_TWPS_TLDR_FLAG (1 << 2) +#define AMDM37x_GPT_TWPS_TTGR_FLAG (1 << 3) +#define AMDM37x_GPT_TWPS_TMAR_FLAG (1 << 4) +#define AMDM37x_GPT_TWPS_TPIR_FLAG (1 << 5) +#define AMDM37x_GPT_TWPS_TNIR_FLAG (1 << 6) +#define AMDM37x_GPT_TWPS_TCVR_FLAG (1 << 7) +#define AMDM37x_GPT_TWPS_TOCR_FLAG (1 << 8) +#define AMDM37x_GPT_TWPS_TOWR_FLAG (1 << 9) + + /** Timer match register */ + ioport32_t tmar; + + /** Capture value 1 register */ + const ioport32_t tcar1; + + /** Software interface control register */ + ioport32_t tsicr; +#define AMDM37x_GPT_TSICR_SFT_FLAG (1 << 1) +#define AMDM37x_GPT_TSICR_POSTED_FLAG (1 << 2) + + /** Capture value 2 register */ + const ioport32_t tcar2; + + /* GPT1,2,10 only (used for 1ms time period generation)*/ + + /** Positive increment register */ + ioport32_t tpir; + + /** Negative increment register */ + ioport32_t tnir; + + /** Counter value register */ + ioport32_t tcvr; + + /** Mask the tick interrupt for selected number of ticks */ + ioport32_t tocr; + + /** Number of masked overflow interrupts */ + ioport32_t towr; +} amdm37x_gpt_regs_t; + +typedef struct { + amdm37x_gpt_regs_t *regs; + bool special_available; +} amdm37x_gpt_t; + +static inline void amdm37x_gpt_timer_ticks_init( + amdm37x_gpt_t* timer, uintptr_t ioregs, size_t iosize, unsigned hz) +{ + /* Set 32768 Hz clock as source */ + // TODO find a nicer way to setup 32kHz clock source for timer1 + // reg 0x48004C40 is CM_CLKSEL_WKUP see page 485 of the manual + ioport32_t *clksel = (void*) km_map(0x48004C40, 4, PAGE_NOT_CACHEABLE); + *clksel &= ~1; + km_unmap((uintptr_t)clksel, 4); + + ASSERT(timer); + /* Map control register */ + timer->regs = (void*) km_map(ioregs, iosize, PAGE_NOT_CACHEABLE); + + /* Set autoreload */ + timer->regs->tclr = AMDM37x_GPT_TCLR_AR_FLAG; + + timer->special_available = ( + (ioregs == AMDM37x_GPT1_BASE_ADDRESS) || + (ioregs == AMDM37x_GPT2_BASE_ADDRESS) || + (ioregs == AMDM37x_GPT10_BASE_ADDRESS)); + timer->regs->tldr = 0xffffffff - (32768 / hz) + 1; + timer->regs->tccr = 0xffffffff - (32768 / hz) + 1; + if (timer->special_available) { + /* Set values for according to formula (manual p. 2733) */ + /* Use temporary variables for easier debugging */ + const uint32_t tpir = + ((32768 / hz + 1) * 1000000) - (32768000L * (1000 / hz)); + const uint32_t tnir = + ((32768 / hz) * 1000000) - (32768000 * (1000 / hz)); + timer->regs->tpir = tpir; + timer->regs->tnir = tnir; + } + +} + +static inline void amdm37x_gpt_timer_ticks_start(amdm37x_gpt_t* timer) +{ + ASSERT(timer); + ASSERT(timer->regs); + /* Enable overflow interrupt */ + timer->regs->tier |= AMDM37x_GPT_TIER_OVF_IRQ_FLAG; + /* Start timer */ + timer->regs->tclr |= AMDM37x_GPT_TCLR_ST_FLAG; +} + +static inline void amdm37x_gpt_irq_ack(amdm37x_gpt_t* timer) +{ + ASSERT(timer); + ASSERT(timer->regs); + /* Clear all pending interrupts */ + timer->regs->tisr = timer->regs->tisr; +} + +#endif + +/** + * @} + */ Index: kernel/genarch/include/drivers/amdm37x_irc/amdm37x_irc.h =================================================================== --- kernel/genarch/include/drivers/amdm37x_irc/amdm37x_irc.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) +++ kernel/genarch/include/drivers/amdm37x_irc/amdm37x_irc.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -0,0 +1,206 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** @addtogroup genarch + * @{ + */ +/** + * @file + * @brief Texas Instruments AM/DM37x MPU on-chip interrupt controller driver. + */ + +#ifndef KERN_AMDM37x_IRQC_H_ +#define KERN_AMDM37x_IRQC_H_ + +/* AMDM37x TRM p. 1079 */ +#define AMDM37x_IRC_BASE_ADDRESS 0x48200000 +#define AMDM37x_IRC_SIZE 4096 + +#define AMDM37x_IRC_IRQ_COUNT 96 + +#include + +typedef struct { + const ioport32_t revision; /**< Revision */ +#define AMDM37x_IRC_REV_MASK (0xff) + + uint8_t padd0_[12]; + + ioport32_t sysconfig; /**< SYS config */ +#define AMDM37x_IRC_SYSCONFIG_AUTOIDLE_FLAG (1 << 0) +#define AMDM37x_IRC_SYSCONFIG_SOFTRESET_FLAG (1 << 1) + + const ioport32_t sysstatus; /**< SYS status */ +#define AMDM37x_IRC_SYSSTATUS_RESET_DONE_FLAG (1 << 0) + + uint8_t padd1_[40]; + + const ioport32_t sir_irq; /**< Currently active irq number */ +#define AMDM37x_IRC_SIR_IRQ_ACTIVEIRQ_MASK (0x7f) +#define AMDM37x_IRC_SIR_IRQ_SPURIOUSIRQFLAG_MASK (0xfffffff8) + + const ioport32_t sir_fiq; +#define AMDM37x_IRC_SIR_FIQ_ACTIVEIRQ_MASK (0x7f) +#define AMDM37x_IRC_SIR_FIQ_SPURIOUSIRQFLAG_MASK (0xfffffff8) + + ioport32_t control; /**< New interrupt agreement. */ +#define AMDM37x_IRC_CONTROL_NEWIRQAGR_FLAG (1 << 0) +#define AMDM37x_IRC_CONTROL_NEWFIQAGR_FLAG (1 << 1) + + ioport32_t protection; /**< Protect other registers. */ +#define AMDM37x_IRC_PROTECTION_PROETCTION_FLAG (1 << 0) + + ioport32_t idle; /**< Idle and autogating */ +#define AMDM37x_IRC_IDLE_FUNCIDLE_FLAG (1 << 0) +#define AMDM37x_IRC_IDLE_TURBO_FLAG (1 << 1) + + uint8_t padd2_[12]; + + ioport32_t irq_priority; /**< Active IRQ priority */ +#define AMDM37x_IRC_IRQ_PRIORITY_IRQPRIORITY_MASK (0x7f) +#define AMDM37x_IRC_IRQ_PRIORITY_SPURIOUSIRQFLAG_MASK (0xfffffff8) + + ioport32_t fiq_priority; /**< Active FIQ priority */ +#define AMDM37x_IRC_FIQ_PRIORITY_FIQPRIORITY_MASK (0x7f) +#define AMDM37x_IRC_FIQ_PRIORITY_SPURIOUSFIQFLAG_MASK (0xfffffff8) + + ioport32_t threshold; /**< Priority threshold */ +#define AMDM37x_IRC_THRESHOLD_PRIORITYTHRESHOLD_MASK (0xff) +#define AMDM37x_IRC_THRESHOLD_PRIORITYTHRESHOLD_ENABLED (0x00) +#define AMDM37x_IRC_THRESHOLD_PRIORITYTHRESHOLD_DISABLED (0xff) + + uint8_t padd3__[20]; + + struct { + const ioport32_t itr; /**< Interrupt input status before masking */ + ioport32_t mir; /**< Interrupt mask */ + ioport32_t mir_clear; /**< Clear mir mask bits */ + ioport32_t mir_set; /**< Set mir mask bits */ + ioport32_t isr_set; /**< Set software interrupt bits */ + ioport32_t isr_clear; /**< Clear software interrupt bits */ + const ioport32_t pending_irq; /**< IRQ status after masking */ + const ioport32_t pending_fiq; /**< FIQ status after masking */ + } interrupts[3]; + + uint8_t padd4_[32]; + + ioport32_t ilr[96]; /**< FIQ/IRQ steering */ +#define AMDM37x_IRC_ILR_FIQNIRQ (1 << 0) +#define AMDM37x_IRC_ILR_PRIORITY_MASK (0x3f) +#define AMDM37x_IRC_ILR_PRIORITY_SHIFT (2) + +} amdm37x_irc_regs_t; + +static inline void amdm37x_irc_dump(amdm37x_irc_regs_t *regs) +{ +#define DUMP_REG(name) \ + printf("%s %p(%x).\n", #name, ®s->name, regs->name); + + DUMP_REG(revision); + DUMP_REG(sysconfig); + DUMP_REG(sysstatus); + DUMP_REG(sir_irq); + DUMP_REG(sir_fiq); + DUMP_REG(control); + DUMP_REG(protection); + DUMP_REG(idle); + DUMP_REG(irq_priority); + DUMP_REG(fiq_priority); + DUMP_REG(threshold); + + for (int i = 0; i < 3; ++i) { + DUMP_REG(interrupts[i].itr); + DUMP_REG(interrupts[i].mir); + DUMP_REG(interrupts[i].isr_set); + DUMP_REG(interrupts[i].pending_irq); + DUMP_REG(interrupts[i].pending_fiq); + } + for (int i = 0; i < AMDM37x_IRC_IRQ_COUNT; ++i) { + DUMP_REG(ilr[i]); + } + +#undef DUMP_REG +} + +static inline void amdm37x_irc_init(amdm37x_irc_regs_t *regs) +{ + /* AMDM37x TRM sec 12.5.1 p. 2425 */ + /* Program system config register */ + //TODO enable this when you know the meaning + //regs->sysconfig |= AMDM37x_IRC_SYSCONFIG_AUTOIDLE_FLAG; + + /* Program idle register */ + //TODO enable this when you know the meaning + //regs->sysconfig |= AMDM37x_IRC_IDLE_TURBO_FLAG; + + /* Program ilr[m] assign priority, decide fiq */ + for (unsigned i = 0; i < AMDM37x_IRC_IRQ_COUNT; ++i) { + regs->ilr[i] = 0; /* highest prio(default) route to irq */ + } + + /* Disable all interrupts */ + regs->interrupts[0].mir_set = 0xffffffff; + regs->interrupts[1].mir_set = 0xffffffff; + regs->interrupts[2].mir_set = 0xffffffff; +} + +static inline unsigned amdm37x_irc_inum_get(amdm37x_irc_regs_t *regs) +{ + return regs->sir_irq & AMDM37x_IRC_SIR_IRQ_ACTIVEIRQ_MASK; +} + +static inline void amdm37x_irc_irq_ack(amdm37x_irc_regs_t *regs) +{ + regs->control = AMDM37x_IRC_CONTROL_NEWIRQAGR_FLAG; +} + +static inline void amdm37x_irc_fiq_ack(amdm37x_irc_regs_t *regs) +{ + regs->control = AMDM37x_IRC_CONTROL_NEWFIQAGR_FLAG; +} + +static inline void amdm37x_irc_enable(amdm37x_irc_regs_t *regs, unsigned inum) +{ + ASSERT(inum < AMDM37x_IRC_IRQ_COUNT); + const unsigned set = inum / 32; + const unsigned pos = inum % 32; + regs->interrupts[set].mir_clear = (1 << pos); +} + +static inline void amdm37x_irc_disable(amdm37x_irc_regs_t *regs, unsigned inum) +{ + ASSERT(inum < AMDM37x_IRC_IRQ_COUNT); + const unsigned set = inum / 32; + const unsigned pos = inum % 32; + regs->interrupts[set].mir_set = (1 << pos); +} + +#endif + +/** + * @} + */ Index: kernel/genarch/include/drivers/amdm37x_uart/amdm37x_uart.h =================================================================== --- kernel/genarch/include/drivers/amdm37x_uart/amdm37x_uart.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) +++ kernel/genarch/include/drivers/amdm37x_uart/amdm37x_uart.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -0,0 +1,459 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** @addtogroup genarch + * @{ + */ +/** + * @file + * @brief Texas Instruments AMDM37x on-chip interrupt controller driver. + */ + +#ifndef KERN_AMDM37x_UART_H_ +#define KERN_AMDM37x_UART_H_ + +#include +#include +#include + +/* AMDM37x TRM p. 2950 */ +#define AMDM37x_UART1_BASE_ADDRESS 0x4806a000 +#define AMDM37x_UART1_SIZE 1024 +#define AMDM37x_UART1_IRQ 72 /* AMDM37x TRM p. 2418 */ + +#define AMDM37x_UART2_BASE_ADDRESS 0x4806b000 +#define AMDM37x_UART2_SIZE 1024 +#define AMDM37x_UART2_IRQ 73 /* AMDM37x TRM p. 2418 */ + +#define AMDM37x_UART3_BASE_ADDRESS 0x49020000 +#define AMDM37x_UART3_SIZE 1024 +#define AMDM37x_UART3_IRQ 74 /* AMDM37x TRM p. 2418 */ + +#define AMDM37x_UART4_BASE_ADDRESS 0x49042000 +#define AMDM37x_UART4_SIZE 1024 +#define AMDM37x_UART4_IRQ 80 /* AMDM37x TRM p. 2418 */ + +typedef struct { + union { + /** Stores lower part of the 14-bit baud divisor */ + ioport32_t dll; +#define AMDM37x_UART_DLL_MASK (0xff) + + /** Receive holding register */ + const ioport32_t rhr; +#define AMDM37x_UART_RHR_MASK (0xff) + + /** Transmit holding register */ + ioport32_t thr; +#define AMDM37x_UART_THR_MASK (0xff) + }; + + union { + /** Stores higher part of the 14-bit baud divisor */ + ioport32_t dlh; +#define AMDM37x_UART_DLH_MASK (0x1f) + + /** Interrupt enable registers */ + ioport32_t ier; +#define AMDM37x_UART_IER_RHR_IRQ_FLAG (1 << 0) +#define AMDM37x_UART_IER_THR_IRQ_FLAG (1 << 1) +#define AMDM37x_UART_IER_LINE_STS_IRQ_FLAG (1 << 2) +#define AMDM37x_UART_IER_MODEM_STS_IRQ_FLAG (1 << 3) +#define AMDM37x_UART_IER_SLEEP_MODE_FLAG (1 << 4) +#define AMDM37x_UART_IER_XOFF_IRQ_FLAG (1 << 5) +#define AMDM37x_UART_IER_RTS_IRQ_FLAG (1 << 6) +#define AMDM37x_UART_IER_CTS_IRQ_FLAG (1 << 7) + +#define AMDM37x_CIR_IER_RHR_IRQ_FLAG (1 << 0) +#define AMDM37x_CIR_IER_THR_IRQ_FLAG (1 << 1) +#define AMDM37x_CIR_IER_RX_STOP_IRQ_FLAG (1 << 2) +#define AMDM37x_CIR_IER_RX_OVERRUN_IRQ_FLAG (1 << 3) +#define AMDM37x_CIR_IER_TX_STS_IRQ_FLAG (1 << 5) + +#define AMDM37x_IRDA_IER_RHR_IRQ_FLAG (1 << 0) +#define AMDM37x_IRDA_IER_THR_IRQ_FLAG (1 << 1) +#define AMDM37x_IRDA_IER_LAST_RX_BYTE_IRQ_FLAG (1 << 2) +#define AMDM37x_IRDA_IER_RX_OVERRUN_IRQ_FLAG (1 << 3) +#define AMDM37x_IRDA_IER_STS_FIFO_TRIG_IRQ_FLAG (1 << 4) +#define AMDM37x_IRDA_IER_TX_STS_IRQ_FLAG (1 << 5) +#define AMDM37x_IRDA_IER_LINE_STS_IRQ_FLAG (1 << 6) +#define AMDM37x_IRDA_IER_EOF_IRQ_FLAG (1 << 7) + }; + + union { + /** Interrupt identification register */ + const ioport32_t iir; +#define AMDM37x_UART_IIR_IRQ_PENDING_FLAG (1 << 0) +#define AMDM37x_UART_IIR_TYPE_MASK (0x1f) +#define AMDM37x_UART_IIR_TYPE_SHIFT (1) +#define AMDM37x_UART_IIR_FCR_MASK (0x3) +#define AMDM37x_UART_IIR_FCR_SHIFT (6) + +#define AMDM37x_CIR_IIR_RHR_IRQ_FLAG (1 << 0) +#define AMDM37x_CIR_IIR_THR_IRQ_FLAG (1 << 1) +#define AMDM37x_CIR_IIR_RX_STOP_IRQ_FLAG (1 << 2) +#define AMDM37x_CIR_IIR_RX_OE_IRQ_FLAG (1 << 3) +#define AMDM37x_CIR_IIR_TX_STS_IRQ_FLAG (1 << 5) + +#define AMDM37x_IRDA_IIR_RHR_IRQ_FLAG (1 << 0) +#define AMDM37x_IRDA_IIR_THR_IRQ_FLAG (1 << 1) +#define AMDM37x_IRDA_IIR_RX_FIFO_LB_IRQ_FLAG (1 << 2) +#define AMDM37x_IRDA_IIR_RX_OE_IRQ_FLAG (1 << 3) +#define AMDM37x_IRDA_IIR_STS_FIFO_IRQ_FLAG (1 << 4) +#define AMDM37x_IRDA_IIR_TX_STS_IRQ_FLAG (1 << 5) +#define AMDM37x_IRDA_IIR_LINE_STS_IRQ_FLAG (1 << 6) +#define AMDM37x_IRDA_IIR_EOF_IRQ_FLAG (1 << 7) + + /** FIFO control register */ + ioport32_t fcr; +#define AMDM37x_UART_FCR_FIFO_EN_FLAG (1 << 0) +#define AMDM37x_UART_FCR_RX_FIFO_CLR_FLAG (1 << 1) +#define AMDM37x_UART_FCR_TX_FIFO_CLR_FLAG (1 << 3) +#define AMDM37x_UART_FCR_DMA_MODE_FLAG (1 << 4) + +#define AMDM37x_UART_FCR_TX_FIFO_TRIG_MASK (0x3) +#define AMDM37x_UART_FCR_TX_FIFO_TRIG_SHIFT (4) + +#define AMDM37x_UART_FCR_RX_FIFO_TRIG_MASK (0x3) +#define AMDM37x_UART_FCR_RX_FIFO_TRIG_SHIFT (6) + + /** Enhanced feature register */ + ioport32_t efr; +#define AMDM37x_UART_EFR_SW_FLOW_CTRL_RX_MASK (0x3) +#define AMDM37x_UART_EFR_SW_FLOW_CTRL_RX_SHIFT (0) +#define AMDM37x_UART_EFR_SW_FLOW_CTRL_TX_MASK (0x3) +#define AMDM37x_UART_EFR_SW_FLOW_CTRL_TX_SHIFT (2) + +#define AMDM37x_UART_EFR_SW_FLOW_CTRL_NONE (0x0) +#define AMDM37x_UART_EFR_SW_FLOW_CTRL_X2 (0x1) +#define AMDM37x_UART_EFR_SW_FLOW_CTRL_X1 (0x2) +#define AMDM37x_UART_EFR_SW_FLOW_CTRL_XBOTH (0x3) + +#define AMDM37x_UART_EFR_ENH_FLAG (1 << 4) +#define AMDM37x_UART_EFR_SPEC_CHAR_FLAG (1 << 5) +#define AMDM37x_UART_EFR_AUTO_RTS_EN_FLAG (1 << 6) +#define AMDM37x_UART_EFR_AUTO_CTS_EN_FLAG (1 << 7) + }; + + /** Line control register */ + ioport32_t lcr; +#define AMDM37x_UART_LCR_CHAR_LENGTH_MASK (0x3) +#define AMDM37x_UART_LCR_CHAR_LENGTH_SHIFT (0) +#define AMDM37x_UART_LCR_CHAR_LENGTH_5BITS (0x0) +#define AMDM37x_UART_LCR_CHAR_LENGTH_6BITS (0x1) +#define AMDM37x_UART_LCR_CHAR_LENGTH_7BITS (0x2) +#define AMDM37x_UART_LCR_CHAR_LENGTH_8BITS (0x3) +#define AMDM37x_UART_LCR_NB_STOP_FLAG (1 << 2) +#define AMDM37x_UART_LCR_PARITY_EN_FLAG (1 << 3) +#define AMDM37x_UART_LCR_PARITY_TYPE1_FLAG (1 << 4) +#define AMDM37x_UART_LCR_PARITY_TYPE2_FLAG (1 << 5) +#define AMDM37x_UART_LCR_BREAK_EN_FLAG (1 << 6) +#define AMDM37x_UART_LCR_DIV_EN_FLAG (1 << 7) + + + union { + /** Modem control register */ + ioport32_t mcr; +#define AMDM37x_UART_MCR_DTR_FLAG (1 << 0) +#define AMDM37x_UART_MCR_RTS_FLAG (1 << 1) +#define AMDM37x_UART_MCR_RI_STS_CH_FLAG (1 << 2) +#define AMDM37x_UART_MCR_CD_STS_CH_FLAG (1 << 3) +#define AMDM37x_UART_MCR_LOOPBACK_EN_FLAG (1 << 4) +#define AMDM37x_UART_MCR_XON_EN_FLAG (1 << 5) +#define AMDM37x_UART_MCR_TCR_TLR_FLAG (1 << 6) + + /** UART: XON1 char, IRDA: ADDR1 address */ + ioport32_t xon1_addr1; +#define AMDM37x_UART_XON1_ADDR1_MASK (0xff) + }; + + union { + /** Line status register */ + const ioport32_t lsr; +#define AMDM37x_UART_LSR_RX_FIFO_E_FLAG (1 << 0) +#define AMDM37x_UART_LSR_RX_OE_FLAG (1 << 1) +#define AMDM37x_UART_LSR_RX_PE_FLAG (1 << 2) +#define AMDM37x_UART_LSR_RX_FE_FLAG (1 << 3) +#define AMDM37x_UART_LSR_RX_BI_FLAG (1 << 4) +#define AMDM37x_UART_LSR_TX_FIFO_E_FLAG (1 << 5) +#define AMDM37x_UART_LSR_TX_SR_E_FLAG (1 << 6) +#define AMDM37x_UART_LSR_RX_FIFO_STS_FLAG (1 << 7) + +#define AMDM37x_CIR_LSR_RX_FIFO_E_FLAG (1 << 0) +#define AMDM37x_CIR_LSR_RX_STOP_FLAG (1 << 5) +#define AMDM37x_CIR_LSR_THR_EMPTY_FLAG (1 << 7) + +#define AMDM37x_IRDA_LSR_RX_FIFO_E_FLAG (1 << 0) +#define AMDM37x_IRDA_LSR_STS_FIFO_E_FLAG (1 << 1) +#define AMDM37x_IRDA_LSR_CRC_FLAG (1 << 2) +#define AMDM37x_IRDA_LSR_ABORT_FLAG (1 << 3) +#define AMDM37x_IRDA_LSR_FTL_FLAG (1 << 4) +#define AMDM37x_IRDA_LSR_RX_LAST_FLAG (1 << 5) +#define AMDM37x_IRDA_LSR_STS_FIFO_FULL_FLAG (1 << 6) +#define AMDM37x_IRDA_LSR_THR_EMPTY_FLAG (1 << 7) + + /** UART: XON2 char, IRDA: ADDR2 address */ + ioport32_t xon2_addr2; + }; + + union { + /** Modem status register */ + const ioport32_t msr; +#define AMDM37x_UART_MSR_CTS_STS_FLAG (1 << 0) +#define AMDM37x_UART_MSR_DSR_STS_FLAG (1 << 1) +#define AMDM37x_UART_MSR_RI_STS_FLAG (1 << 2) +#define AMDM37x_UART_MSR_DCD_STS_FLAG (1 << 3) +#define AMDM37x_UART_MSR_NCTS_STS_FLAG (1 << 4) +#define AMDM37x_UART_MSR_NDSR_STS_FLAG (1 << 5) +#define AMDM37x_UART_MSR_NRI_STS_FLAG (1 << 6) +#define AMDM37x_UART_MSR_NCD_STS_FLAG (1 << 7) + + /** Transmission control register */ + ioport32_t tcr; +#define AMDM37x_UART_TCR_FIFO_TRIG_MASK (0xf) +#define AMDM37x_UART_TCR_FIFO_TRIG_HALT_SHIFT (0) +#define AMDM37x_UART_TCR_FIFO_TRIG_START_SHIFT (4) + + /** UART: XOFF1 char */ + ioport32_t xoff1; +#define AMDM37x_UART_XOFF1_MASK (0xff) + }; + + union { + /* Scratchpad register, does nothing */ + ioport32_t spr; +#define AMDM37x_UART_SPR_MASK (0xff) + + /* Trigger level register */ + ioport32_t tlr; +#define AMDM37x_UART_TLR_LEVEL_MASK (0xf) +#define AMDM37x_UART_TLR_TX_FIFO_TRIG_SHIFT (0) +#define AMDM37x_UART_TLR_RX_FIFO_TRIG_SHIFT (4) + + /** UART: XOFF2 char */ + ioport32_t xoff2; +#define AMDM37x_UART_XOFF2_MASK (0xff) + }; + + /** Mode definition register. */ + ioport32_t mdr1; +#define AMDM37x_UART_MDR_MS_MASK (0x7) +#define AMDM37x_UART_MDR_MS_SHIFT (0) +#define AMDM37x_UART_MDR_MS_UART16 (0x0) +#define AMDM37x_UART_MDR_MS_SIR (0x1) +#define AMDM37x_UART_MDR_MS_UART16_AUTO (0x2) +#define AMDM37x_UART_MDR_MS_UART13 (0x3) +#define AMDM37x_UART_MDR_MS_MIR (0x4) +#define AMDM37x_UART_MDR_MS_FIR (0x5) +#define AMDM37x_UART_MDR_MS_CIR (0x6) +#define AMDM37x_UART_MDR_MS_DISABLE (0x7) + +#define AMDM37x_UART_MDR_IR_SLEEP_FLAG (1 << 3) +#define AMDM37x_UART_MDR_SET_TXIR_FLAG (1 << 4) +#define AMDM37x_UART_MDR_SCT_FLAG (1 << 5) +#define AMDM37x_UART_MDR_SIP_FLAG (1 << 6) +#define AMDM37x_UART_MDR_FRAME_END_MODE_FLAG (1 << 7) + + /** Mode definition register */ + ioport32_t mdr2; +#define AMDM37x_UART_MDR_IRTX_UNDERRUN_FLAG (1 << 0) +#define AMDM37x_UART_MDR_STS_FIFO_TRIG_MASK (0x3) +#define AMDM37x_UART_MDR_STS_FIFO_TRIG_SHIFT (1) +#define AMDM37x_UART_MDR_PULSE_SHAPING_FLAG (1 << 3) +#define AMDM37x_UART_MDR_CIR_PULSE_MODE_MASK (0x3) +#define AMDM37x_UART_MDR_CIR_PULSE_MODE_SHIFT (4) +#define AMDM37x_UART_MDR_IRRXINVERT_FLAG (1 << 6) + + + /* UART3 specific */ + union { + /** Status FIFO line status register (IrDA only) */ + const ioport32_t sflsr; +#define AMDM37x_IRDA_SFLSR_CRC_ERROR_FLAG (1 << 1) +#define AMDM37x_IRDA_SFLSR_ABORT_FLAG (1 << 2) +#define AMDM37x_IRDA_SFLSR_FTL_FLAG (1 << 3) +#define AMDM37x_IRDA_SFLSR_OE_FLAG (1 << 4) + + /** Transmit frame length low (IrDA only) */ + ioport32_t txfll; +#define AMDM37x_UART_TXFLL_MASK (0xff) + }; + + /* UART3 specific */ + union { + /** Dummy register to restart TX or RX (IrDA only) */ + const ioport32_t resume; + /** Transmit frame length high (IrDA only) */ + ioport32_t txflh; +#define AMDM37x_UART_TXFLH_MASK (0xff) + }; + + /* UART3 specific */ + union { + /** Status FIFO register low (IrDA only) */ + const ioport32_t sfregl; +#define AMDM37x_UART_SFREGL_MASK (0xff) + /** Received frame length low (IrDA only) */ + ioport32_t rxfll; +#define AMDM37x_UART_RXFLL_MASK (0xff) + }; + + /* UART3 specific */ + union { + /** Status FIFO register high (IrDA only) */ + const ioport32_t sfregh; +#define AMDM37x_UART_SFREGH_MASK (0xf) + /** Received frame length high (IrDA only) */ + ioport32_t rxflh; +#define AMDM37x_UART_RXFLH_MASK (0xf) + }; + + union { + /** UART autobauding status register */ + const ioport32_t uasr; +#define AMDM37x_UART_UASR_SPEED_MASK (0x1f) +#define AMDM37x_UART_UASR_SPEED_SHIFT (0) +#define AMDM37x_UART_UASR_8BIT_CHAR_FLAG (1 << 5) +#define AMDM37x_UART_UASR_PARITY_MASK (0x3) +#define AMDM37x_UART_UASR_PARITY_SHIFT (6) + + /** BOF control register (IrDA only) */ + ioport32_t blr; /* UART3 sepcific */ +#define AMDM37x_IRDA_BLR_XBOF_TYPE_FLAG (1 << 6) +#define AMDM37x_IRDA_BLR_STS_FIFO_RESET (1 << 7) + }; + + /** Auxiliary control register (IrDA only) */ + ioport32_t acreg; /* UART3 specific */ +#define AMDM37x_IRDA_ACREG_EOT_EN_FLAG (1 << 0) +#define AMDM37x_IRDA_ACREG_ABORT_EN_FLAG (1 << 1) +#define AMDM37x_IRDA_ACREG_SCTX_EN_FLAG (1 << 2) +#define AMDM37x_IRDA_ACREG_SEND_SIP_FLAG (1 << 3) +#define AMDM37x_IRDA_ACREG_DIS_TX_UNDERRUN_FLAG (1 << 4) +#define AMDM37x_IRDA_ACREG_DIS_IR_RX_FLAG (1 << 5) +#define AMDM37x_IRDA_ACREG_SD_MOD_FLAG (1 << 6) +#define AMDM37x_IRDA_ACREG_PULSE_TYPE_FLAG (1 << 7) + + /** Supplementary control register */ + ioport32_t scr; +#define AMDM37x_UART_SCR_DMA_MODE_CTL_FLAG (1 << 0) +#define AMDM37x_UART_SCR_DMA_MODE_MASK (0x3) +#define AMDM37x_UART_SCR_DMA_MODE_SHIFT (1) +#define AMDM37x_UART_SCR_TX_EMPTY_CTL_IRQ_FLAG (1 << 3) +#define AMDM37x_UART_SCR_RX_CTS_WU_EN_FLAG (1 << 4) +#define AMDM37x_UART_SCR_TX_TRIG_GRANU1_FLAG (1 << 6) +#define AMDM37x_UART_SCR_RX_TRIG_GRANU1_FLAG (1 << 7) + + /** Supplementary status register */ + const ioport32_t ssr; +#define AMDM37x_UART_SSR_TX_FIFO_FULL_FLAG (1 << 0) +#define AMDM37x_UART_SSR_RX_CTS_WU_STS_FLAG (1 << 1) +#define AMDM37x_UART_SSR_DMA_COUNTER_RESET_FLAG (1 << 2) + + /** BOF Length register (IrDA only)*/ + ioport32_t eblr; /* UART3 specific */ +#define AMDM37x_IRDA_EBLR_DISABLED (0x00) +#define AMDM37x_IRDA_EBLR_RX_STOP_BITS(bits) (bits & 0xff) + + uint32_t padd0_; + + /** Module version register */ + const ioport32_t mvr; +#define AMDM37x_UART_MVR_MINOR_MASK (0xf) +#define AMDM37x_UART_MVR_MINOR_SHIFT (0) +#define AMDM37x_UART_MVR_MAJOR_MASK (0xf) +#define AMDM37x_UART_MVR_MAJOR_SHIFT (4) + + /** System configuration register */ + ioport32_t sysc; +#define AMDM37x_UART_SYSC_AUTOIDLE_FLAG (1 << 0) +#define AMDM37x_UART_SYSC_SOFTRESET_FLAG (1 << 1) +#define AMDM37x_UART_SYSC_ENWAKEUP_FLAG (1 << 2) +#define AMDM37x_UART_SYSC_IDLE_MODE_MASK (0x3) +#define AMDM37x_UART_SYSC_IDLE_MODE_SHIFT (3) +#define AMDM37x_UART_SYSC_IDLE_MODE_FORCE (0x0) +#define AMDM37x_UART_SYSC_IDLE_MODE_NO (0x1) +#define AMDM37x_UART_SYSC_IDLE_MODE_SMART (0x2) + + /** System status register */ + const ioport32_t syss; +#define AMDM37x_UART_SYSS_RESETDONE_FLAG (1 << 0) + + /** Wake-up enable register */ + ioport32_t wer; +#define AMDM37x_UART_WER_CTS_ACTIVITY_FLAG (1 << 0) +#define AMDM37x_UART_WER_RI_ACTIVITY_FLAG (1 << 2) +#define AMDM37x_UART_WER_RX_ACTIVITY_FLAG (1 << 4) +#define AMDM37x_UART_WER_RHR_IRQ_FLAG (1 << 5) +#define AMDM37x_UART_WER_RLS_IRQ_FLAG (1 << 6) +#define AMDM37x_UART_WER_TX_WAKEUP_EN_FLAG (1 << 7) + + /** Carrier frequency prescaler */ + ioport32_t cfps; /* UART3 specific */ +#define AMDM37x_UART_CFPS_MASK (0xff) + + /** Number of bytes in RX fifo */ + const ioport32_t rx_fifo_lvl; +#define AMDM37x_UART_RX_FIFO_LVL_MASK (0xff) + + /** Number of bytes in TX fifo */ + const ioport32_t tx_fifo_lvl; +#define AMDM37x_UART_TX_FIFO_LVL_MASK (0xff) + + /** RX/TX empty interrupts */ + ioport32_t ier2; +#define AMDM37x_UART_IER2_RX_FIFO_EMPTY_IRQ_EN_FLAG (1 << 0) +#define AMDM37x_UART_IER2_TX_FIFO_EMPTY_IRQ_EN_FLAG (1 << 1) + + /** RX/TX empty status */ + ioport32_t isr2; +#define AMDM37x_UART_ISR2_RX_FIFO_EMPTY_FLAG (1 << 0) +#define AMDM37x_UART_ISR2_TX_FIFO_EMPTY_FLAG (1 << 1) + + uint32_t padd2_[3]; + + /** Mode definition register 3 */ + ioport32_t mdr3; +#define AMDM37x_UART_MDR3_DIS_CIR_RX_DEMOD_FLAG (1 << 0) +} amdm37x_uart_regs_t; + +typedef struct { + amdm37x_uart_regs_t *regs; + indev_t *indev; + outdev_t outdev; + irq_t irq; +} amdm37x_uart_t; + + +bool amdm37x_uart_init(amdm37x_uart_t *, inr_t, uintptr_t, size_t); +void amdm37x_uart_input_wire(amdm37x_uart_t *, indev_t *); + +#endif + +/** + * @} + */ Index: kernel/genarch/src/drivers/amdm37x_uart/amdm37x_uart.c =================================================================== --- kernel/genarch/src/drivers/amdm37x_uart/amdm37x_uart.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) +++ kernel/genarch/src/drivers/amdm37x_uart/amdm37x_uart.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -0,0 +1,163 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** @addtogroup genarch + * @{ + */ +/** + * @file + * @brief Texas Instruments AMDM37x on-chip uart serial line driver. + */ + +#include +#include +#include +#include + +static void amdm37x_uart_txb(amdm37x_uart_t *uart, uint8_t b) +{ + /* Wait for buffer */ + while (uart->regs->ssr & AMDM37x_UART_SSR_TX_FIFO_FULL_FLAG); + /* Write to the outgoing fifo */ + uart->regs->thr = b; +} + +static void amdm37x_uart_putchar(outdev_t *dev, wchar_t ch) +{ + amdm37x_uart_t *uart = dev->data; + if (!ascii_check(ch)) { + amdm37x_uart_txb(uart, U_SPECIAL); + } else { + if (ch == '\n') + amdm37x_uart_txb(uart, '\r'); + amdm37x_uart_txb(uart, ch); + } +} + +static outdev_operations_t amdm37x_uart_ops = { + .redraw = NULL, + .write = amdm37x_uart_putchar, +}; + +static irq_ownership_t amdm37x_uart_claim(irq_t *irq) +{ + return IRQ_ACCEPT; +} + +static void amdm37x_uart_handler(irq_t *irq) +{ + amdm37x_uart_t *uart = irq->instance; + while ((uart->regs->rx_fifo_lvl)) { + const uint8_t val = uart->regs->rhr; + if (uart->indev && val) { + indev_push_character(uart->indev, val); + } + } +} + +bool amdm37x_uart_init( + amdm37x_uart_t *uart, inr_t interrupt, uintptr_t addr, size_t size) +{ + ASSERT(uart); + uart->regs = (void *)km_map(addr, size, PAGE_NOT_CACHEABLE); + + ASSERT(uart->regs); + + /* See TI OMAP35X TRM ch 17.5.1.1 p. 2732 for startup routine */ +#if 0 + /* Soft reset the port */ + uart->regs->sysc = AMDM37x_UART_SYSC_SOFTRESET_FLAG; + while (!(uart->regs->syss & AMDM37x_UART_SYSS_RESETDONE_FLAG)) ; +#endif + + /* Enable access to EFR register */ + const uint8_t lcr = uart->regs->lcr; /* Save old value */ + uart->regs->lcr = 0xbf; /* Sets config mode B */ + + /* Enable access to TCL_TLR register */ + const bool enhanced = uart->regs->efr & AMDM37x_UART_EFR_ENH_FLAG; + uart->regs->efr |= AMDM37x_UART_EFR_ENH_FLAG; /* Turn on enh. */ + uart->regs->lcr = 0x80; /* Config mode A */ + + /* Set default (val 0) triggers, disable DMA enable FIFOs */ + const bool tcl_tlr = uart->regs->mcr & AMDM37x_UART_MCR_TCR_TLR_FLAG; + /* Enable access to tcr and tlr registers */ + uart->regs->mcr |= AMDM37x_UART_MCR_TCR_TLR_FLAG; + + /* Enable FIFOs */ + uart->regs->fcr = AMDM37x_UART_FCR_FIFO_EN_FLAG; + + /* Eneble fine granularity for RX FIFO and set trigger level to 1, + * TX FIFO, trigger level is irelevant*/ + uart->regs->lcr = 0xbf; /* Sets config mode B */ + uart->regs->scr = AMDM37x_UART_SCR_RX_TRIG_GRANU1_FLAG; + uart->regs->tlr = 1 << AMDM37x_UART_TLR_RX_FIFO_TRIG_SHIFT; + + /* Restore enhanced */ + if (!enhanced) + uart->regs->efr &= ~AMDM37x_UART_EFR_ENH_FLAG; + + uart->regs->lcr = 0x80; /* Config mode A */ + /* Restore tcl_lcr access flag*/ + if (!tcl_tlr) + uart->regs->mcr &= ~AMDM37x_UART_MCR_TCR_TLR_FLAG; + + /* Restore lcr */ + uart->regs->lcr = lcr; + + /* Disable interrupts */ + uart->regs->ier = 0; + + /* Setup outdev */ + outdev_initialize("amdm37x_uart_dev", &uart->outdev, &amdm37x_uart_ops); + uart->outdev.data = uart; + + /* Initialize IRQ */ + irq_initialize(&uart->irq); + uart->irq.devno = device_assign_devno(); + uart->irq.inr = interrupt; + uart->irq.claim = amdm37x_uart_claim; + uart->irq.handler = amdm37x_uart_handler; + uart->irq.instance = uart; + + return true; +} + +void amdm37x_uart_input_wire(amdm37x_uart_t *uart, indev_t *indev) +{ + ASSERT(uart); + /* Set indev */ + uart->indev = indev; + /* Register interrupt. */ + irq_register(&uart->irq); + /* Enable interrupt on receive */ + uart->regs->ier |= AMDM37x_UART_IER_RHR_IRQ_FLAG; +} + +/** + * @} + */ Index: kernel/genarch/src/mm/page_ht.c =================================================================== --- kernel/genarch/src/mm/page_ht.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ kernel/genarch/src/mm/page_ht.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -209,4 +209,8 @@ pte->frame = ALIGN_DOWN(frame, FRAME_SIZE); + /* + * Make sure that a concurrent ht_mapping_find() will see the + * new entry only after it is fully initialized. + */ write_barrier(); Index: kernel/genarch/src/mm/page_pt.c =================================================================== --- kernel/genarch/src/mm/page_pt.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ kernel/genarch/src/mm/page_pt.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -89,4 +89,9 @@ PAGE_NOT_PRESENT | PAGE_USER | PAGE_EXEC | PAGE_CACHEABLE | PAGE_WRITE); + /* + * Make sure that a concurrent hardware page table walk or + * pt_mapping_find() will see the new PTL1 only after it is + * fully initialized. + */ write_barrier(); SET_PTL1_PRESENT(ptl0, PTL0_INDEX(page)); @@ -103,4 +108,7 @@ PAGE_NOT_PRESENT | PAGE_USER | PAGE_EXEC | PAGE_CACHEABLE | PAGE_WRITE); + /* + * Make the new PTL2 visible only after it is fully initialized. + */ write_barrier(); SET_PTL2_PRESENT(ptl1, PTL1_INDEX(page)); @@ -117,4 +125,7 @@ PAGE_NOT_PRESENT | PAGE_USER | PAGE_EXEC | PAGE_CACHEABLE | PAGE_WRITE); + /* + * Make the new PTL3 visible only after it is fully initialized. + */ write_barrier(); SET_PTL3_PRESENT(ptl2, PTL2_INDEX(page)); @@ -125,4 +136,7 @@ SET_FRAME_ADDRESS(ptl3, PTL3_INDEX(page), frame); SET_FRAME_FLAGS(ptl3, PTL3_INDEX(page), flags | PAGE_NOT_PRESENT); + /* + * Make the new mapping visible only after it is fully initialized. + */ write_barrier(); SET_FRAME_PRESENT(ptl3, PTL3_INDEX(page)); @@ -296,4 +310,7 @@ #if (PTL1_ENTRIES != 0) + /* + * Always read ptl2 only after we are sure it is present. + */ read_barrier(); #endif @@ -304,4 +321,7 @@ #if (PTL2_ENTRIES != 0) + /* + * Always read ptl3 only after we are sure it is present. + */ read_barrier(); #endif Index: kernel/generic/include/config.h =================================================================== --- kernel/generic/include/config.h (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ kernel/generic/include/config.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -44,4 +44,6 @@ #define STACK_FRAMES TWO_FRAMES #define STACK_SIZE ((1 << STACK_FRAMES) << PAGE_WIDTH) + +#define STACK_SIZE_USER (1 * 1024 * 1024) #define CONFIG_INIT_TASKS 32 Index: kernel/generic/include/mm/as.h =================================================================== --- kernel/generic/include/mm/as.h (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ kernel/generic/include/mm/as.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -61,10 +61,4 @@ #define USER_ADDRESS_SPACE_END USER_ADDRESS_SPACE_END_ARCH -#ifdef USTACK_ADDRESS_ARCH - #define USTACK_ADDRESS USTACK_ADDRESS_ARCH -#else - #define USTACK_ADDRESS (USER_ADDRESS_SPACE_END - (STACK_SIZE - 1)) -#endif - /** Kernel address space. */ #define FLAG_AS_KERNEL (1 << 0) @@ -74,12 +68,15 @@ #define AS_AREA_ATTR_PARTIAL 1 /**< Not fully initialized area. */ +/** The page fault was resolved by as_page_fault(). */ +#define AS_PF_OK 0 + +/** The page fault was caused by memcpy_from_uspace() or memcpy_to_uspace(). */ +#define AS_PF_DEFER 1 + /** The page fault was not resolved by as_page_fault(). */ -#define AS_PF_FAULT 0 - -/** The page fault was resolved by as_page_fault(). */ -#define AS_PF_OK 1 - -/** The page fault was caused by memcpy_from_uspace() or memcpy_to_uspace(). */ -#define AS_PF_DEFER 2 +#define AS_PF_FAULT 2 + +/** The page fault was not resolved by as_page_fault(). Non-verbose version. */ +#define AS_PF_SILENT 3 /** Address space structure. @@ -224,4 +221,7 @@ void (* destroy)(as_area_t *); + bool (* is_resizable)(as_area_t *); + bool (* is_shareable)(as_area_t *); + int (* page_fault)(as_area_t *, uintptr_t, pf_access_t); void (* frame_free)(as_area_t *, uintptr_t, uintptr_t); Index: kernel/generic/src/console/cmd.c =================================================================== --- kernel/generic/src/console/cmd.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ kernel/generic/src/console/cmd.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -56,4 +56,5 @@ #include #include +#include #include #include @@ -81,4 +82,79 @@ .func = cmd_help, .argc = 0 +}; + +/* Data and methods for pio_read_8 command */ +static int cmd_pio_read_8(cmd_arg_t *argv); +static cmd_arg_t pio_read_8_argv[] = { { .type = ARG_TYPE_INT } }; +static cmd_info_t pio_read_8_info = { + .name = "pio_read_8", + .description = "pio_read_8
Read 1 byte from memory (or port).", + .func = cmd_pio_read_8, + .argc = 1, + .argv = pio_read_8_argv +}; + +/* Data and methods for pio_read_16 command */ +static int cmd_pio_read_16(cmd_arg_t *argv); +static cmd_arg_t pio_read_16_argv[] = { { .type = ARG_TYPE_INT } }; +static cmd_info_t pio_read_16_info = { + .name = "pio_read_16", + .description = "pio_read_16
Read 2 bytes from memory (or port).", + .func = cmd_pio_read_16, + .argc = 1, + .argv = pio_read_16_argv +}; + +/* Data and methods for pio_read_32 command */ +static int cmd_pio_read_32(cmd_arg_t *argv); +static cmd_arg_t pio_read_32_argv[] = { { .type = ARG_TYPE_INT } }; +static cmd_info_t pio_read_32_info = { + .name = "pio_read_32", + .description = "pio_read_32
Read 4 bytes from memory (or port).", + .func = cmd_pio_read_32, + .argc = 1, + .argv = pio_read_32_argv +}; + +/* Data and methods for pio_write_8 command */ +static int cmd_pio_write_8(cmd_arg_t *argv); +static cmd_arg_t pio_write_8_argv[] = { + { .type = ARG_TYPE_INT }, + { .type = ARG_TYPE_INT } +}; +static cmd_info_t pio_write_8_info = { + .name = "pio_write_8", + .description = "pio_write_8
Write 1 byte to memory (or port).", + .func = cmd_pio_write_8, + .argc = 2, + .argv = pio_write_8_argv +}; + +/* Data and methods for pio_write_16 command */ +static int cmd_pio_write_16(cmd_arg_t *argv); +static cmd_arg_t pio_write_16_argv[] = { + { .type = ARG_TYPE_INT }, + { .type = ARG_TYPE_INT } +}; +static cmd_info_t pio_write_16_info = { + .name = "pio_write_16", + .description = "pio_write_16
Write 2 bytes to memory (or port).", + .func = cmd_pio_write_16, + .argc = 2, + .argv = pio_write_16_argv +}; + +/* Data and methods for pio_write_32 command */ +static int cmd_pio_write_32(cmd_arg_t *argv); +static cmd_arg_t pio_write_32_argv[] = { + { .type = ARG_TYPE_INT }, + { .type = ARG_TYPE_INT } +}; +static cmd_info_t pio_write_32_info = { + .name = "pio_write_32", + .description = "pio_write_32
Write 4 bytes to memory (or port).", + .func = cmd_pio_write_32, + .argc = 2, + .argv = pio_write_32_argv }; @@ -531,4 +607,10 @@ &btrace_info, #endif + &pio_read_8_info, + &pio_read_16_info, + &pio_read_32_info, + &pio_write_8_info, + &pio_write_16_info, + &pio_write_32_info, NULL }; @@ -601,4 +683,187 @@ spinlock_unlock(&cmd_lock); + return 1; +} + +/** Read 1 byte from phys memory or io port. + * + * @param argv Argument vector. + * + * @return 0 on failure, 1 on success. + */ +static int cmd_pio_read_8(cmd_arg_t *argv) +{ + uint8_t *ptr = NULL; + +#ifdef IO_SPACE_BOUNDARY + if ((void *) argv->intval < IO_SPACE_BOUNDARY) + ptr = (void *) argv[0].intval; + else +#endif + ptr = (uint8_t *) km_map(argv[0].intval, sizeof(uint8_t), + PAGE_NOT_CACHEABLE); + + const uint8_t val = pio_read_8(ptr); + printf("read %" PRIxn ": %" PRIx8 "\n", argv[0].intval, val); + +#ifdef IO_SPACE_BOUNDARY + if ((void *) argv->intval < IO_SPACE_BOUNDARY) + return 1; +#endif + + km_unmap((uintptr_t) ptr, sizeof(uint8_t)); + return 1; +} + +/** Read 2 bytes from phys memory or io port. + * + * @param argv Argument vector. + * + * @return 0 on failure, 1 on success. + */ +static int cmd_pio_read_16(cmd_arg_t *argv) +{ + uint16_t *ptr = NULL; + +#ifdef IO_SPACE_BOUNDARY + if ((void *) argv->intval < IO_SPACE_BOUNDARY) + ptr = (void *) argv[0].intval; + else +#endif + ptr = (uint16_t *) km_map(argv[0].intval, sizeof(uint16_t), + PAGE_NOT_CACHEABLE); + + const uint16_t val = pio_read_16(ptr); + printf("read %" PRIxn ": %" PRIx16 "\n", argv[0].intval, val); + +#ifdef IO_SPACE_BOUNDARY + if ((void *) argv->intval < IO_SPACE_BOUNDARY) + return 1; +#endif + + km_unmap((uintptr_t) ptr, sizeof(uint16_t)); + return 1; +} + +/** Read 4 bytes from phys memory or io port. + * + * @param argv Argument vector. + * + * @return 0 on failure, 1 on success. + */ +static int cmd_pio_read_32(cmd_arg_t *argv) +{ + uint32_t *ptr = NULL; + +#ifdef IO_SPACE_BOUNDARY + if ((void *) argv->intval < IO_SPACE_BOUNDARY) + ptr = (void *) argv[0].intval; + else +#endif + ptr = (uint32_t *) km_map(argv[0].intval, sizeof(uint32_t), + PAGE_NOT_CACHEABLE); + + const uint32_t val = pio_read_32(ptr); + printf("read %" PRIxn ": %" PRIx32 "\n", argv[0].intval, val); + +#ifdef IO_SPACE_BOUNDARY + if ((void *) argv->intval < IO_SPACE_BOUNDARY) + return 1; +#endif + + km_unmap((uintptr_t) ptr, sizeof(uint32_t)); + return 1; +} + +/** Write 1 byte to phys memory or io port. + * + * @param argv Argument vector. + * + * @return 0 on failure, 1 on success. + */ +static int cmd_pio_write_8(cmd_arg_t *argv) +{ + uint8_t *ptr = NULL; + +#ifdef IO_SPACE_BOUNDARY + if ((void *) argv->intval < IO_SPACE_BOUNDARY) + ptr = (void *) argv[0].intval; + else +#endif + ptr = (uint8_t *) km_map(argv[0].intval, sizeof(uint8_t), + PAGE_NOT_CACHEABLE); + + printf("write %" PRIxn ": %" PRIx8 "\n", argv[0].intval, + (uint8_t) argv[1].intval); + pio_write_8(ptr, (uint8_t) argv[1].intval); + +#ifdef IO_SPACE_BOUNDARY + if ((void *) argv->intval < IO_SPACE_BOUNDARY) + return 1; +#endif + + km_unmap((uintptr_t) ptr, sizeof(uint8_t)); + return 1; +} + +/** Write 2 bytes to phys memory or io port. + * + * @param argv Argument vector. + * + * @return 0 on failure, 1 on success. + */ +static int cmd_pio_write_16(cmd_arg_t *argv) +{ + uint16_t *ptr = NULL; + +#ifdef IO_SPACE_BOUNDARY + if ((void *) argv->intval < IO_SPACE_BOUNDARY) + ptr = (void *) argv[0].intval; + else +#endif + ptr = (uint16_t *) km_map(argv[0].intval, sizeof(uint16_t), + PAGE_NOT_CACHEABLE); + + printf("write %" PRIxn ": %" PRIx16 "\n", argv[0].intval, + (uint16_t) argv[1].intval); + pio_write_16(ptr, (uint16_t) argv[1].intval); + +#ifdef IO_SPACE_BOUNDARY + if ((void *) argv->intval < IO_SPACE_BOUNDARY) + return 1; +#endif + + km_unmap((uintptr_t) ptr, sizeof(uint16_t)); + return 1; +} + +/** Write 4 bytes to phys memory or io port. + * + * @param argv Argument vector. + * + * @return 0 on failure, 1 on success. + */ +static int cmd_pio_write_32(cmd_arg_t *argv) +{ + uint32_t *ptr = NULL; + +#ifdef IO_SPACE_BOUNDARY + if ((void *) argv->intval < IO_SPACE_BOUNDARY) + ptr = (void *) argv[0].intval; + else +#endif + ptr = (uint32_t *) km_map(argv[0].intval, sizeof(uint32_t), + PAGE_NOT_CACHEABLE); + + printf("write %" PRIxn ": %" PRIx32 "\n", argv[0].intval, + (uint32_t) argv[1].intval); + pio_write_32(ptr, (uint32_t) argv[1].intval); + +#ifdef IO_SPACE_BOUNDARY + if ((void *) argv->intval < IO_SPACE_BOUNDARY) + return 1; +#endif + + km_unmap((uintptr_t) ptr, sizeof(uint32_t)); return 1; } Index: kernel/generic/src/console/kconsole.c =================================================================== --- kernel/generic/src/console/kconsole.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ kernel/generic/src/console/kconsole.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -524,11 +524,14 @@ /* It's a number - convert it */ uint64_t value; - int rc = str_uint64_t(text, NULL, 0, true, &value); + char *end; + int rc = str_uint64_t(text, &end, 0, false, &value); + if (end != text + len) + rc = EINVAL; switch (rc) { case EINVAL: - printf("Invalid number.\n"); + printf("Invalid number '%s'.\n", text); return false; case EOVERFLOW: - printf("Integer overflow.\n"); + printf("Integer overflow in '%s'.\n", text); return false; case EOK: @@ -538,5 +541,5 @@ break; default: - printf("Unknown error.\n"); + printf("Unknown error parsing '%s'.\n", text); return false; } Index: kernel/generic/src/interrupt/interrupt.c =================================================================== --- kernel/generic/src/interrupt/interrupt.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ kernel/generic/src/interrupt/interrupt.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -166,5 +166,6 @@ } -static NO_TRACE void fault_from_uspace_core(istate_t *istate, const char *fmt, va_list args) +static NO_TRACE +void fault_from_uspace_core(istate_t *istate, const char *fmt, va_list args) { printf("Task %s (%" PRIu64 ") killed due to an exception at " Index: kernel/generic/src/main/kinit.c =================================================================== --- kernel/generic/src/main/kinit.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ kernel/generic/src/main/kinit.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -172,4 +172,10 @@ #endif /* CONFIG_KCONSOLE */ + /* + * Store the default stack size in sysinfo so that uspace can create + * stack with this default size. + */ + sysinfo_set_item_val("default.stack_size", NULL, STACK_SIZE_USER); + interrupts_enable(); Index: kernel/generic/src/mm/as.c =================================================================== --- kernel/generic/src/mm/as.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ kernel/generic/src/mm/as.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -79,4 +79,5 @@ #include #include +#include /** @@ -426,9 +427,10 @@ /* * So far, the area does not conflict with other areas. - * Check if it doesn't conflict with kernel address space. + * Check if it is contained in the user address space. */ if (!KERNEL_ADDRESS_SPACE_SHADOWED) { - return !overlaps(addr, P2SZ(count), KERNEL_ADDRESS_SPACE_START, - KERNEL_ADDRESS_SPACE_END - KERNEL_ADDRESS_SPACE_START); + return iswithin(USER_ADDRESS_SPACE_START, + (USER_ADDRESS_SPACE_END - USER_ADDRESS_SPACE_START) + 1, + addr, P2SZ(count)); } @@ -696,9 +698,8 @@ return ENOENT; } - - if (area->backend == &phys_backend) { - /* - * Remapping of address space areas associated - * with memory mapped devices is not supported. + + if (!area->backend->is_resizable(area)) { + /* + * The backend does not support resizing for this area. */ mutex_unlock(&area->lock); @@ -1057,8 +1058,7 @@ } - if ((!src_area->backend) || (!src_area->backend->share)) { - /* - * There is no backend or the backend does not - * know how to share the area. + if (!src_area->backend->is_shareable(src_area)) { + /* + * The backend does not permit sharing of this area. */ mutex_unlock(&src_area->lock); @@ -1363,9 +1363,11 @@ int as_page_fault(uintptr_t page, pf_access_t access, istate_t *istate) { + int rc = AS_PF_FAULT; + if (!THREAD) - return AS_PF_FAULT; + goto page_fault; if (!AS) - return AS_PF_FAULT; + goto page_fault; mutex_lock(&AS->lock); @@ -1423,5 +1425,6 @@ * Resort to the backend page fault handler. */ - if (area->backend->page_fault(area, page, access) != AS_PF_OK) { + rc = area->backend->page_fault(area, page, access); + if (rc != AS_PF_OK) { page_table_unlock(AS, false); mutex_unlock(&area->lock); @@ -1444,6 +1447,11 @@ istate_set_retaddr(istate, (uintptr_t) &memcpy_to_uspace_failover_address); + } else if (rc == AS_PF_SILENT) { + printf("Killing task %" PRIu64 " due to a " + "failed late reservation request.\n", TASK->taskid); + task_kill_self(true); } else { - return AS_PF_FAULT; + fault_if_from_uspace(istate, "Page fault: %p.", (void *) page); + panic_memtrap(istate, access, page, NULL); } @@ -2132,5 +2140,5 @@ { uintptr_t virt = base; - as_area_t *area = as_area_create(AS, flags | AS_AREA_CACHEABLE, size, + as_area_t *area = as_area_create(AS, flags, size, AS_AREA_ATTR_NONE, &anon_backend, NULL, &virt, bound); if (area == NULL) Index: kernel/generic/src/mm/backend_anon.c =================================================================== --- kernel/generic/src/mm/backend_anon.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ kernel/generic/src/mm/backend_anon.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -59,4 +59,7 @@ static void anon_destroy(as_area_t *); +static bool anon_is_resizable(as_area_t *); +static bool anon_is_shareable(as_area_t *); + static int anon_page_fault(as_area_t *, uintptr_t, pf_access_t); static void anon_frame_free(as_area_t *, uintptr_t, uintptr_t); @@ -68,4 +71,7 @@ .destroy = anon_destroy, + .is_resizable = anon_is_resizable, + .is_shareable = anon_is_shareable, + .page_fault = anon_page_fault, .frame_free = anon_frame_free, @@ -74,4 +80,7 @@ bool anon_create(as_area_t *area) { + if (area->flags & AS_AREA_LATE_RESERVE) + return true; + return reserve_try_alloc(area->pages); } @@ -79,4 +88,7 @@ bool anon_resize(as_area_t *area, size_t new_pages) { + if (area->flags & AS_AREA_LATE_RESERVE) + return true; + if (new_pages > area->pages) return reserve_try_alloc(new_pages - area->pages); @@ -100,4 +112,5 @@ ASSERT(mutex_locked(&area->as->lock)); ASSERT(mutex_locked(&area->lock)); + ASSERT(!(area->flags & AS_AREA_LATE_RESERVE)); /* @@ -139,7 +152,19 @@ void anon_destroy(as_area_t *area) { + if (area->flags & AS_AREA_LATE_RESERVE) + return; + reserve_free(area->pages); } +bool anon_is_resizable(as_area_t *area) +{ + return true; +} + +bool anon_is_shareable(as_area_t *area) +{ + return !(area->flags & AS_AREA_LATE_RESERVE); +} /** Service a page fault in the anonymous memory address space area. @@ -225,4 +250,13 @@ * the different causes */ + + if (area->flags & AS_AREA_LATE_RESERVE) { + /* + * Reserve the memory for this page now. + */ + if (!reserve_try_alloc(1)) + return AS_PF_SILENT; + } + kpage = km_temporary_page_get(&frame, FRAME_NO_RESERVE); memsetb((void *) kpage, PAGE_SIZE, 0); @@ -255,5 +289,19 @@ ASSERT(mutex_locked(&area->lock)); - frame_free_noreserve(frame); + if (area->flags & AS_AREA_LATE_RESERVE) { + /* + * In case of the late reserve areas, physical memory will not + * be unreserved when the area is destroyed so we need to use + * the normal unreserving frame_free(). + */ + frame_free(frame); + } else { + /* + * The reserve will be given back when the area is destroyed or + * resized, so use the frame_free_noreserve() which does not + * manipulate the reserve or it would be given back twice. + */ + frame_free_noreserve(frame); + } } Index: kernel/generic/src/mm/backend_elf.c =================================================================== --- kernel/generic/src/mm/backend_elf.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ kernel/generic/src/mm/backend_elf.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -58,4 +58,7 @@ static void elf_destroy(as_area_t *); +static bool elf_is_resizable(as_area_t *); +static bool elf_is_shareable(as_area_t *); + static int elf_page_fault(as_area_t *, uintptr_t, pf_access_t); static void elf_frame_free(as_area_t *, uintptr_t, uintptr_t); @@ -66,4 +69,7 @@ .share = elf_share, .destroy = elf_destroy, + + .is_resizable = elf_is_resizable, + .is_shareable = elf_is_shareable, .page_fault = elf_page_fault, @@ -213,4 +219,15 @@ } +bool elf_is_resizable(as_area_t *area) +{ + return true; +} + +bool elf_is_shareable(as_area_t *area) +{ + return true; +} + + /** Service a page fault in the ELF backend address space area. * Index: kernel/generic/src/mm/backend_phys.c =================================================================== --- kernel/generic/src/mm/backend_phys.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ kernel/generic/src/mm/backend_phys.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -52,4 +52,8 @@ static void phys_destroy(as_area_t *); +static bool phys_is_resizable(as_area_t *); +static bool phys_is_shareable(as_area_t *); + + static int phys_page_fault(as_area_t *, uintptr_t, pf_access_t); @@ -59,4 +63,7 @@ .share = phys_share, .destroy = phys_destroy, + + .is_resizable = phys_is_resizable, + .is_shareable = phys_is_shareable, .page_fault = phys_page_fault, @@ -87,4 +94,15 @@ /* Nothing to do. */ } + +bool phys_is_resizable(as_area_t *area) +{ + return false; +} + +bool phys_is_shareable(as_area_t *area) +{ + return true; +} + /** Service a page fault in the address space area backed by physical memory. Index: kernel/generic/src/mm/km.c =================================================================== --- kernel/generic/src/mm/km.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ kernel/generic/src/mm/km.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -233,5 +233,6 @@ * @param[inout] framep Pointer to a variable which will receive the physical * address of the allocated frame. - * @param[in] flags Frame allocation flags. FRAME_NONE or FRAME_NO_RESERVE. + * @param[in] flags Frame allocation flags. FRAME_NONE, FRAME_NO_RESERVE + * and FRAME_ATOMIC bits are allowed. * @return Virtual address of the allocated frame. */ @@ -243,5 +244,5 @@ ASSERT(THREAD); ASSERT(framep); - ASSERT(!(flags & ~FRAME_NO_RESERVE)); + ASSERT(!(flags & ~(FRAME_NO_RESERVE | FRAME_ATOMIC))); /* @@ -255,6 +256,8 @@ ASSERT(page); // FIXME } else { - frame = (uintptr_t) frame_alloc_noreserve(ONE_FRAME, - FRAME_LOWMEM); + frame = (uintptr_t) frame_alloc(ONE_FRAME, + FRAME_LOWMEM | flags); + if (!frame) + return (uintptr_t) NULL; page = PA2KA(frame); } Index: kernel/generic/src/proc/program.c =================================================================== --- kernel/generic/src/proc/program.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ kernel/generic/src/proc/program.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -79,8 +79,14 @@ * Create the stack address space area. */ - uintptr_t virt = USTACK_ADDRESS; + uintptr_t virt = (uintptr_t) -1; + uintptr_t bound = USER_ADDRESS_SPACE_END - (STACK_SIZE_USER - 1); + + /* Adjust bound to create space for the desired guard page. */ + bound -= PAGE_SIZE; + as_area_t *area = as_area_create(as, - AS_AREA_READ | AS_AREA_WRITE | AS_AREA_CACHEABLE, - STACK_SIZE, AS_AREA_ATTR_NONE, &anon_backend, NULL, &virt, 0); + AS_AREA_READ | AS_AREA_WRITE | AS_AREA_CACHEABLE | AS_AREA_GUARD | + AS_AREA_LATE_RESERVE, STACK_SIZE_USER, AS_AREA_ATTR_NONE, + &anon_backend, NULL, &virt, bound); if (!area) { task_destroy(prg->task); @@ -93,5 +99,5 @@ kernel_uarg->uspace_entry = (void *) entry_addr; kernel_uarg->uspace_stack = (void *) virt; - kernel_uarg->uspace_stack_size = STACK_SIZE; + kernel_uarg->uspace_stack_size = STACK_SIZE_USER; kernel_uarg->uspace_thread_function = NULL; kernel_uarg->uspace_thread_arg = NULL; Index: kernel/generic/src/proc/task.c =================================================================== --- kernel/generic/src/proc/task.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ kernel/generic/src/proc/task.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -196,5 +196,5 @@ task->ucycles = 0; task->kcycles = 0; - + task->ipc_info.call_sent = 0; task->ipc_info.call_received = 0; Index: tools/mkuimage.py =================================================================== --- tools/mkuimage.py (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ tools/mkuimage.py (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -60,4 +60,5 @@ load_addr = 0 start_addr = 0 + os_type = 5 #Linux is the default while len(args) >= 2 and args[0][0] == '-': @@ -71,4 +72,6 @@ elif opt == 'saddr': start_addr = (int)(optarg, 0) + elif opt == 'ostype': + os_type = (int)(optarg, 0) else: print(base_name + ": Unrecognized option.") @@ -85,10 +88,10 @@ try: - mkuimage(inf_name, outf_name, image_name, load_addr, start_addr) + mkuimage(inf_name, outf_name, image_name, load_addr, start_addr, os_type) except: os.remove(outf_name) raise -def mkuimage(inf_name, outf_name, image_name, load_addr, start_addr): +def mkuimage(inf_name, outf_name, image_name, load_addr, start_addr, os_type): inf = open(inf_name, 'rb') outf = open(outf_name, 'wb') @@ -120,5 +123,5 @@ header.start_addr = start_addr # Address of entry point header.data_crc = data_crc - header.os = 5 # Linux + header.os = os_type header.arch = 2 # ARM header.img_type = 2 # Kernel Index: uspace/Makefile =================================================================== --- uspace/Makefile (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ uspace/Makefile (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -192,4 +192,9 @@ endif +ifeq ($(UARCH),arm32) + DIRS += \ + drv/infrastructure/rootamdm37x +endif + ## System libraries # Index: uspace/app/tester/float/softfloat1.c =================================================================== --- uspace/app/tester/float/softfloat1.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ uspace/app/tester/float/softfloat1.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -35,8 +35,9 @@ #include #include +#include #include #include "../tester.h" -#define OPERANDS 6 +#define OPERANDS 10 #define PRECISION 10000 @@ -44,21 +45,29 @@ typedef int32_t cmptype_t; -typedef void (* float_op_t)(float, float, float *, float_t *); -typedef void (* double_op_t)(double, double, double *, double_t *); + +typedef void (* uint_to_double_op_t)(unsigned int, double *, double_t *); +typedef void (* double_to_uint_op_t)(double, unsigned int *, unsigned int *); +typedef void (* float_binary_op_t)(float, float, float *, float_t *); +typedef void (* double_binary_op_t)(double, double, double *, double_t *); typedef void (* double_cmp_op_t)(double, double, cmptype_t *, cmptype_t *); -typedef void (* template_t)(void *, unsigned, unsigned, cmptype_t *, + +typedef void (* template_unary_t)(void *, unsigned, cmptype_t *, cmptype_t *); +typedef void (* template_binary_t)(void *, unsigned, unsigned, cmptype_t *, cmptype_t *); -static float fop_a[OPERANDS] = - {3.5, -2.1, 100.0, 50.0, -1024.0, 0.0}; - -static float fop_b[OPERANDS] = - {-2.1, 100.0, 50.0, -1024.0, 3.5, 0.0}; - -static double dop_a[OPERANDS] = - {3.5, -2.1, 100.0, 50.0, -1024.0, 0.0}; - -static double dop_b[OPERANDS] = - {-2.1, 100.0, 50.0, -1024.0, 3.5, 0.0}; +#define NUMBERS \ + 3.5, -2.1, 100.0, 50.0, -1024.0, 0.0, 768.3156, 1080.499999, -600.0, 1.0 + +static float fop_a[OPERANDS] = { + NUMBERS +}; + +static double dop_a[OPERANDS] = { + NUMBERS +}; + +static unsigned int uop_a[OPERANDS] = { + 4, -100, 100, 50, 1024, 0, 1000000, -1U, 0x80000000U, 500 +}; static cmptype_t cmpabs(cmptype_t a) @@ -81,5 +90,34 @@ static void -float_template(void *f, unsigned i, unsigned j, cmptype_t *pic, +uint_to_double_template(void *f, unsigned i, cmptype_t *pic, cmptype_t *pisc) +{ + double c; + double_t sc; + + uint_to_double_op_t op = (uint_to_double_op_t) f; + + op(uop_a[i], &c, &sc); + + *pic = (cmptype_t) (c * PRECISION); + *pisc = (cmptype_t) (sc.val * PRECISION); +} + +static void +double_to_uint_template(void *f, unsigned i, cmptype_t *pic, cmptype_t *pisc) +{ + unsigned int c; + unsigned int sc; + + double_to_uint_op_t op = (double_to_uint_op_t) f; + + op(dop_a[i], &c, &sc); + + *pic = (cmptype_t) c; + *pisc = (cmptype_t) sc; +} + + +static void +float_template_binary(void *f, unsigned i, unsigned j, cmptype_t *pic, cmptype_t *pisc) { @@ -87,7 +125,7 @@ float_t sc; - float_op_t op = (float_op_t) f; - - op(fop_a[i], fop_b[j], &c, &sc); + float_binary_op_t op = (float_binary_op_t) f; + + op(fop_a[i], fop_a[j], &c, &sc); *pic = (cmptype_t) (c * PRECISION); @@ -96,5 +134,5 @@ static void -double_template(void *f, unsigned i, unsigned j, cmptype_t *pic, +double_template_binary(void *f, unsigned i, unsigned j, cmptype_t *pic, cmptype_t *pisc) { @@ -102,7 +140,7 @@ double_t sc; - double_op_t op = (double_op_t) f; - - op(dop_a[i], dop_b[j], &c, &sc); + double_binary_op_t op = (double_binary_op_t) f; + + op(dop_a[i], dop_a[j], &c, &sc); *pic = (cmptype_t) (c * PRECISION); @@ -116,8 +154,28 @@ double_cmp_op_t op = (double_cmp_op_t) f; - op(dop_a[i], dop_b[j], pis, piss); -} - -static bool test_template(template_t template, void *f) + op(dop_a[i], dop_a[j], pis, piss); +} + +static bool test_template_unary(template_unary_t template, void *f) +{ + bool correct = true; + + for (unsigned int i = 0; i < OPERANDS; i++) { + cmptype_t ic; + cmptype_t isc; + + template(f, i, &ic, &isc); + cmptype_t diff = cmpabs(ic - isc); + + if (diff != 0) { + TPRINTF("i=%u diff=%" PRIdCMPTYPE "\n", i, diff); + correct = false; + } + } + + return correct; +} + +static bool test_template_binary(template_binary_t template, void *f) { bool correct = true; @@ -142,4 +200,32 @@ } +static void uint_to_double_operator(unsigned int a, double *pc, double_t *psc) +{ + *pc = (double) a; + psc->data = uint_to_double(a); +} + +static void +double_to_uint_operator(double a, unsigned int *pc, unsigned int *psc) +{ + double_t sa; + + sa.val = a; + + *pc = (unsigned int) a; + *psc = double_to_uint(sa.data); +} + +static void +double_to_int_operator(double a, unsigned int *pc, unsigned int *psc) +{ + double_t sa; + + sa.val = a; + + *pc = (int) a; + *psc = double_to_int(sa.data); +} + static void float_add_operator(float a, float b, float *pc, float_t *psc) { @@ -267,32 +353,47 @@ const char *err = NULL; - if (!test_template(float_template, float_add_operator)) { + if (!test_template_binary(float_template_binary, float_add_operator)) { err = "Float addition failed"; TPRINTF("%s\n", err); } - if (!test_template(float_template, float_mul_operator)) { + if (!test_template_binary(float_template_binary, float_mul_operator)) { err = "Float multiplication failed"; TPRINTF("%s\n", err); } - if (!test_template(float_template, float_div_operator)) { + if (!test_template_binary(float_template_binary, float_div_operator)) { err = "Float division failed"; TPRINTF("%s\n", err); } - if (!test_template(double_template, double_add_operator)) { + if (!test_template_binary(double_template_binary, double_add_operator)) { err = "Double addition failed"; TPRINTF("%s\n", err); } - if (!test_template(double_template, double_mul_operator)) { + if (!test_template_binary(double_template_binary, double_mul_operator)) { err = "Double multiplication failed"; TPRINTF("%s\n", err); } - if (!test_template(double_template, double_div_operator)) { + if (!test_template_binary(double_template_binary, double_div_operator)) { err = "Double division failed"; TPRINTF("%s\n", err); } - if (!test_template(double_compare_template, double_cmp_operator)) { + if (!test_template_binary(double_compare_template, double_cmp_operator)) { err = "Double comparison failed"; TPRINTF("%s\n", err); } + if (!test_template_unary(uint_to_double_template, + uint_to_double_operator)) { + err = "Conversion from unsigned int to double failed"; + TPRINTF("%s\n", err); + } + if (!test_template_unary(double_to_uint_template, + double_to_uint_operator)) { + err = "Conversion from double to unsigned int failed"; + TPRINTF("%s\n", err); + } + if (!test_template_unary(double_to_uint_template, + double_to_int_operator)) { + err = "Conversion from double to signed int failed"; + TPRINTF("%s\n", err); + } return err; Index: uspace/app/tester/mm/common.c =================================================================== --- uspace/app/tester/mm/common.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ uspace/app/tester/mm/common.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -343,5 +343,5 @@ area->addr = as_area_create(AS_AREA_ANY, size, - AS_AREA_WRITE | AS_AREA_READ); + AS_AREA_WRITE | AS_AREA_READ | AS_AREA_CACHEABLE); if (area->addr == AS_MAP_FAILED) { free(area); Index: uspace/app/tester/mm/mapping1.c =================================================================== --- uspace/app/tester/mm/mapping1.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ uspace/app/tester/mm/mapping1.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -43,5 +43,5 @@ void *result = as_area_create(AS_AREA_ANY, size, - AS_AREA_READ | AS_AREA_WRITE); + AS_AREA_READ | AS_AREA_WRITE | AS_AREA_CACHEABLE); if (result == AS_MAP_FAILED) return NULL; Index: uspace/drv/bus/isa/i8237.c =================================================================== --- uspace/drv/bus/isa/i8237.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ uspace/drv/bus/isa/i8237.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -40,5 +40,4 @@ #include #include -#include #include #include "i8237.h" Index: uspace/drv/bus/pci/pciintel/pci.c =================================================================== --- uspace/drv/bus/pci/pciintel/pci.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ uspace/drv/bus/pci/pciintel/pci.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -58,5 +58,4 @@ #include #include -#include #include Index: uspace/drv/bus/usb/ehci/ehci.ma =================================================================== --- uspace/drv/bus/usb/ehci/ehci.ma (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ uspace/drv/bus/usb/ehci/ehci.ma (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -1,1 +1,2 @@ +20 usb/host=ehci 10 pci/class=0c&subclass=03&progif=20 Index: uspace/drv/bus/usb/ohci/ohci.ma =================================================================== --- uspace/drv/bus/usb/ohci/ohci.ma (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ uspace/drv/bus/usb/ohci/ohci.ma (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -1,1 +1,2 @@ +20 usb/host=ohci 10 pci/class=0c&subclass=03&progif=10 Index: uspace/drv/bus/usb/ohci/ohci_regs.h =================================================================== --- uspace/drv/bus/usb/ohci/ohci_regs.h (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ uspace/drv/bus/usb/ohci/ohci_regs.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -245,5 +245,5 @@ #define RHPS_PRSC_FLAG (1 << 20) /* port reset status change WC */ #define RHPS_CHANGE_WC_MASK (0x1f0000) -} __attribute__((packed)) ohci_regs_t; +} ohci_regs_t; #endif /** Index: uspace/drv/bus/usb/uhci/hc.c =================================================================== --- uspace/drv/bus/usb/uhci/hc.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ uspace/drv/bus/usb/uhci/hc.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -35,5 +35,5 @@ #include #include -#include +#include #include Index: uspace/drv/bus/usb/uhci/hc.h =================================================================== --- uspace/drv/bus/usb/uhci/hc.h (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ uspace/drv/bus/usb/uhci/hc.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -37,6 +37,4 @@ #include -#include - #include Index: uspace/drv/bus/usb/uhcirh/port.c =================================================================== --- uspace/drv/bus/usb/uhcirh/port.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ uspace/drv/bus/usb/uhcirh/port.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -32,5 +32,5 @@ * @brief UHCI root hub port routines */ -#include /* pio_read and pio_write */ +#include #include /* async_usleep */ #include Index: uspace/drv/char/i8042/i8042.c =================================================================== --- uspace/drv/char/i8042/i8042.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ uspace/drv/char/i8042/i8042.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -41,5 +41,4 @@ #include #include -#include #include #include Index: uspace/drv/char/ns8250/ns8250.c =================================================================== --- uspace/drv/char/ns8250/ns8250.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ uspace/drv/char/ns8250/ns8250.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -51,5 +51,4 @@ #include #include -#include #include Index: uspace/drv/infrastructure/rootamdm37x/Makefile =================================================================== --- uspace/drv/infrastructure/rootamdm37x/Makefile (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) +++ uspace/drv/infrastructure/rootamdm37x/Makefile (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -0,0 +1,38 @@ +# +# Copyright (c) 2012 Jan Vesely +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# - Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# - Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# - The name of the author may not be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +USPACE_PREFIX = ../../.. +LIBS = $(LIBDRV_PREFIX)/libdrv.a +EXTRA_CFLAGS += -I$(LIBDRV_PREFIX)/include +BINARY = rootamdm37x + +SOURCES = \ + amdm37x.c \ + rootamdm37x.c + +include $(USPACE_PREFIX)/Makefile.common Index: uspace/drv/infrastructure/rootamdm37x/amdm37x.c =================================================================== --- uspace/drv/infrastructure/rootamdm37x/amdm37x.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) +++ uspace/drv/infrastructure/rootamdm37x/amdm37x.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -0,0 +1,404 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @defgroup root_amdm37x TI AM/DM37x platform driver. + * @brief HelenOS TI AM/DM37x platform driver. + * @{ + */ + +/** @file + */ + +#include "amdm37x.h" + +#include +#include +#include +#include +#include + +static void log(const volatile void *place, uint32_t val, volatile void* base, size_t size, void *data, bool write) +{ + printf("PIO %s: %p(%p) %#"PRIx32"\n", write ? "WRITE" : "READ", + (place - base) + data, place, val); +} + + +int amdm37x_init(amdm37x_t *device, bool trace) +{ + assert(device); + int ret = EOK; + + ret = pio_enable((void*)USBHOST_CM_BASE_ADDRESS, USBHOST_CM_SIZE, + (void**)&device->cm.usbhost); + if (ret != EOK) + return ret; + + ret = pio_enable((void*)CORE_CM_BASE_ADDRESS, CORE_CM_SIZE, + (void**)&device->cm.core); + if (ret != EOK) + return ret; + + ret = pio_enable((void*)CLOCK_CONTROL_CM_BASE_ADDRESS, + CLOCK_CONTROL_CM_SIZE, (void**)&device->cm.clocks); + if (ret != EOK) + return ret; + + ret = pio_enable((void*)MPU_CM_BASE_ADDRESS, + MPU_CM_SIZE, (void**)&device->cm.mpu); + if (ret != EOK) + return ret; + + ret = pio_enable((void*)IVA2_CM_BASE_ADDRESS, + IVA2_CM_SIZE, (void**)&device->cm.iva2); + if (ret != EOK) + return ret; + + ret = pio_enable((void*)CLOCK_CONTROL_PRM_BASE_ADDRESS, + CLOCK_CONTROL_PRM_SIZE, (void**)&device->prm.clocks); + if (ret != EOK) + return ret; + + ret = pio_enable((void*)GLOBAL_REG_PRM_BASE_ADDRESS, + GLOBAL_REG_PRM_SIZE, (void**)&device->prm.global); + if (ret != EOK) + return ret; + + ret = pio_enable((void*)AMDM37x_USBTLL_BASE_ADDRESS, + AMDM37x_USBTLL_SIZE, (void**)&device->tll); + if (ret != EOK) + return ret; + + ret = pio_enable((void*)AMDM37x_UHH_BASE_ADDRESS, + AMDM37x_UHH_SIZE, (void**)&device->uhh); + if (ret != EOK) + return ret; + + if (trace) { + pio_trace_enable(device->tll, AMDM37x_USBTLL_SIZE, log, (void*)AMDM37x_USBTLL_BASE_ADDRESS); + pio_trace_enable(device->cm.clocks, CLOCK_CONTROL_CM_SIZE, log, (void*)CLOCK_CONTROL_CM_BASE_ADDRESS); + pio_trace_enable(device->cm.core, CORE_CM_SIZE, log, (void*)CORE_CM_BASE_ADDRESS); + pio_trace_enable(device->cm.mpu, MPU_CM_SIZE, log, (void*)MPU_CM_BASE_ADDRESS); + pio_trace_enable(device->cm.iva2, IVA2_CM_SIZE, log, (void*)IVA2_CM_BASE_ADDRESS); + pio_trace_enable(device->cm.usbhost, USBHOST_CM_SIZE, log, (void*)USBHOST_CM_BASE_ADDRESS); + pio_trace_enable(device->uhh, AMDM37x_UHH_SIZE, log, (void*)AMDM37x_UHH_BASE_ADDRESS); + pio_trace_enable(device->prm.clocks, CLOCK_CONTROL_PRM_SIZE, log, (void*)CLOCK_CONTROL_PRM_BASE_ADDRESS); + pio_trace_enable(device->prm.global, GLOBAL_REG_PRM_SIZE, log, (void*)GLOBAL_REG_PRM_BASE_ADDRESS); + } + return EOK; +} + + +/** Set DPLLs 1,2,3,4,5 to ON (locked) and autoidle. + * @param device Register map. + * + * The idea is to get all DPLLs running and make hw control their power mode, + * based on the module requirements (module ICLKs and FCLKs). + */ +void amdm37x_setup_dpll_on_autoidle(amdm37x_t *device) +{ + assert(device); + /* Get SYS_CLK value, it is used as reference clock by all DPLLs, + * NFI who sets this or why it is set to specific value. */ + const unsigned osc_clk = pio_read_32(&device->prm.clocks->clksel) + & CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_MASK; + const unsigned clk_reg = pio_read_32(&device->prm.global->clksrc_ctrl); + const unsigned base_freq = sys_clk_freq_kHz(osc_clk) + / GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKDIV_GET(clk_reg); + ddf_msg(LVL_NOTE, "Base frequency: %d.%dMhz", + base_freq / 1000, base_freq % 1000); + + + /* DPLL1 provides MPU(CPU) clock. + * It uses SYS_CLK as reference clock and core clock (DPLL3) as + * high frequency bypass (MPU then runs on L3 interconnect freq). + * It should be setup by fw or u-boot.*/ + mpu_cm_regs_t *mpu = device->cm.mpu; + + /* Current MPU frequency. */ + if (pio_read_32(&mpu->clkstst) & MPU_CM_CLKSTST_CLKACTIVITY_MPU_ACTIVE_FLAG) { + if (pio_read_32(&mpu->idlest_pll) & MPU_CM_IDLEST_PLL_ST_MPU_CLK_LOCKED_FLAG) { + /* DPLL active and locked */ + const uint32_t reg = pio_read_32(&mpu->clksel1_pll); + const unsigned multiplier = + (reg & MPU_CM_CLKSEL1_PLL_MPU_DPLL_MULT_MASK) + >> MPU_CM_CLKSEL1_PLL_MPU_DPLL_MULT_SHIFT; + const unsigned divisor = + (reg & MPU_CM_CLKSEL1_PLL_MPU_DPLL_DIV_MASK) + >> MPU_CM_CLKSEL1_PLL_MPU_DPLL_DIV_SHIFT; + const unsigned divisor2 = + (pio_read_32(&mpu->clksel2_pll) + & MPU_CM_CLKSEL2_PLL_MPU_DPLL_CLKOUT_DIV_MASK); + if (multiplier && divisor && divisor2) { + /** See AMDM37x TRM p. 300 for the formula */ + const unsigned freq = + ((base_freq * multiplier) / (divisor + 1)) + / divisor2; + ddf_msg(LVL_NOTE, "MPU running at %d.%d MHz", + freq / 1000, freq % 1000); + } else { + ddf_msg(LVL_WARN, "Frequency divisor and/or " + "multiplier value invalid: %d %d %d", + multiplier, divisor, divisor2); + } + } else { + /* DPLL in LP bypass mode */ + const unsigned divisor = + MPU_CM_CLKSEL1_PLL_MPU_CLK_SRC_VAL( + pio_read_32(&mpu->clksel1_pll)); + ddf_msg(LVL_NOTE, "MPU DPLL in bypass mode, running at" + " CORE CLK / %d MHz", divisor); + } + } else { + ddf_msg(LVL_WARN, "MPU clock domain is not active, we should not be running..."); + } + // TODO: Enable this (automatic MPU downclocking): +#if 0 + /* Enable low power bypass mode, this will take effect the next lock or + * relock sequence. */ + //TODO: We might need to force re-lock after enabling this + pio_set_32(&mpu->clken_pll, MPU_CM_CLKEN_PLL_EN_MPU_DPLL_LP_MODE_FLAG, 5); + /* Enable automatic relocking */ + pio_change_32(&mpu->autoidle_pll, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_ENABLED, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_MASK, 5); +#endif + + /* DPLL2 provides IVA(video acceleration) clock. + * It uses SYS_CLK as reference clokc and core clock (DPLL3) as + * high frequency bypass (IVA runs on L3 freq). + */ + // TODO: We can probably turn this off entirely. IVA is left unused. + /* Enable low power bypass mode, this will take effect the next lock or + * relock sequence. */ + //TODO: We might need to force re-lock after enabling this + pio_set_32(&device->cm.iva2->clken_pll, MPU_CM_CLKEN_PLL_EN_MPU_DPLL_LP_MODE_FLAG, 5); + /* Enable automatic relocking */ + pio_change_32(&device->cm.iva2->autoidle_pll, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_ENABLED, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_MASK, 5); + + /* DPLL3 provides tons of clocks: + * CORE_CLK, COREX2_CLK, DSS_TV_CLK, 12M_CLK, 48M_CLK, 96M_CLK, L3_ICLK, + * and L4_ICLK. It uses SYS_CLK as reference clock and low frequency + * bypass. It should be setup by fw or u-boot as it controls critical + * interconnects. + */ + if (pio_read_32(&device->cm.clocks->idlest_ckgen) & CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_CORE_CLK_FLAG) { + /* DPLL active and locked */ + const uint32_t reg = + pio_read_32(&device->cm.clocks->clksel1_pll); + const unsigned multiplier = + CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_MULT_GET(reg); + const unsigned divisor = + CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_DIV_GET(reg); + const unsigned divisor2 = + CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_CLKOUT_DIV_GET(reg); + if (multiplier && divisor && divisor2) { + /** See AMDM37x TRM p. 300 for the formula */ + const unsigned freq = + ((base_freq * multiplier) / (divisor + 1)) / divisor2; + ddf_msg(LVL_NOTE, "CORE CLK running at %d.%d MHz", + freq / 1000, freq % 1000); + const unsigned l3_div = + pio_read_32(&device->cm.core->clksel) + & CORE_CM_CLKSEL_CLKSEL_L3_MASK; + if (l3_div == CORE_CM_CLKSEL_CLKSEL_L3_DIVIDED1 || + l3_div == CORE_CM_CLKSEL_CLKSEL_L3_DIVIDED2) { + ddf_msg(LVL_NOTE, "L3 interface at %d.%d MHz", + (freq / l3_div) / 1000, + (freq / l3_div) % 1000); + } else { + ddf_msg(LVL_WARN,"L3 interface clock divisor is" + " invalid: %d", l3_div); + } + } else { + ddf_msg(LVL_WARN, "DPLL3 frequency divisor and/or " + "multiplier value invalid: %d %d %d", + multiplier, divisor, divisor2); + } + } else { + ddf_msg(LVL_WARN, "CORE CLK in bypass mode, fruunig at SYS_CLK" + " frreq of %d.%d MHz", base_freq / 1000, base_freq % 1000); + } + + /* Set DPLL3 to automatic to save power */ + pio_change_32(&device->cm.clocks->autoidle_pll, + CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_AUTOMATIC, + CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_MASK, 5); + + /* DPLL4 provides peripheral domain clocks: + * CAM_MCLK, EMU_PER_ALWON_CLK, DSS1_ALWON_FCLK, and 96M_ALWON_FCLK. + * It uses SYS_CLK as reference clock and low frequency bypass. + * 96M clock is used by McBSP[1,5], MMC[1,2,3], I2C[1,2,3], so + * we can probably turn this off entirely (DSS is still non-functional). + */ + /* Set DPLL4 to automatic to save power */ + pio_change_32(&device->cm.clocks->autoidle_pll, + CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_AUTOMATIC, + CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_MASK, 5); + + /* DPLL5 provide peripheral domain clocks: 120M_FCLK. + * It uses SYS_CLK as reference clock and low frequency bypass. + * 120M clock is used by HS USB and USB TLL. + */ + // TODO setup DPLL5 + if ((pio_read_32(&device->cm.clocks->clken2_pll) + & CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_MASK) + != CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_LOCK) { + /* Compute divisors and multiplier + * See AMDM37x TRM p. 300 for the formula */ + // TODO: base_freq does not have to be rounded to Mhz + // (that's why I used KHz as unit). + const unsigned mult = 120; + const unsigned div = (base_freq / 1000) - 1; + const unsigned div2 = 1; + if ( ((base_freq % 1000) != 0) || (div > 127)) { + ddf_msg(LVL_ERROR, "Rounding error, or divisor to big " + "freq: %d, div: %d", base_freq, div); + return; + }; + assert(div <= 127); + + /* Set multiplier */ + pio_change_32(&device->cm.clocks->clksel4_pll, + CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT_CREATE(mult), + CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT_MASK, 10); + + /* Set DPLL divisor */ + pio_change_32(&device->cm.clocks->clksel4_pll, + CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV_CREATE(div), + CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV_MASK, 10); + + /* Set output clock divisor */ + pio_change_32(&device->cm.clocks->clksel5_pll, + CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M_CREATE(div2), + CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M_MASK, 10); + + /* Start DPLL5 */ + pio_change_32(&device->cm.clocks->clken2_pll, + CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_LOCK, + CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_MASK, 10); + + } + /* Set DPLL5 to automatic to save power */ + pio_change_32(&device->cm.clocks->autoidle2_pll, + CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_AUTOMATIC, + CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_MASK, 5); +} + +/** Enable/disable function and interface clocks for USBTLL and USBHOST. + * @param device Register map. + * @param on True to switch clocks on. + */ +void amdm37x_usb_clocks_set(amdm37x_t *device, bool enabled) +{ + if (enabled) { + /* Enable interface and function clock for USB TLL */ + pio_set_32(&device->cm.core->fclken3, + CORE_CM_FCLKEN3_EN_USBTLL_FLAG, 5); + pio_set_32(&device->cm.core->iclken3, + CORE_CM_ICLKEN3_EN_USBTLL_FLAG, 5); + + /* Enable interface and function clock for USB hosts */ + pio_set_32(&device->cm.usbhost->fclken, + USBHOST_CM_FCLKEN_EN_USBHOST1_FLAG | + USBHOST_CM_FCLKEN_EN_USBHOST2_FLAG, 5); + pio_set_32(&device->cm.usbhost->iclken, + USBHOST_CM_ICLKEN_EN_USBHOST, 5); +#if 0 + printf("DPLL5 (and everything else) should be on: %" + PRIx32" %"PRIx32".\n", + pio_read_32(&device->cm.clocks->idlest_ckgen), + pio_read_32(&device->cm.clocks->idlest2_ckgen)); +#endif + } else { + /* Disable interface and function clock for USB hosts */ + pio_clear_32(&device->cm.usbhost->iclken, + USBHOST_CM_ICLKEN_EN_USBHOST, 5); + pio_clear_32(&device->cm.usbhost->fclken, + USBHOST_CM_FCLKEN_EN_USBHOST1_FLAG | + USBHOST_CM_FCLKEN_EN_USBHOST2_FLAG, 5); + + /* Disable interface and function clock for USB TLL */ + pio_clear_32(&device->cm.core->iclken3, + CORE_CM_ICLKEN3_EN_USBTLL_FLAG, 5); + pio_clear_32(&device->cm.core->fclken3, + CORE_CM_FCLKEN3_EN_USBTLL_FLAG, 5); + } +} + +/** Initialize USB TLL port connections. + * + * Different modes are on page 3312 of the Manual Figure 22-34. + * Select mode than can operate in FS/LS. + */ +int amdm37x_usb_tll_init(amdm37x_t *device) +{ + /* Check access */ + if (pio_read_32(&device->cm.core->idlest3) & CORE_CM_IDLEST3_ST_USBTLL_FLAG) { + ddf_msg(LVL_ERROR, "USB TLL is not accessible"); + return EIO; + } + + /* Reset USB TLL */ + pio_set_32(&device->tll->sysconfig, TLL_SYSCONFIG_SOFTRESET_FLAG, 5); + ddf_msg(LVL_DEBUG2, "Waiting for USB TLL reset"); + while (!(pio_read_32(&device->tll->sysstatus) & TLL_SYSSTATUS_RESET_DONE_FLAG)); + ddf_msg(LVL_DEBUG, "USB TLL Reset done."); + + /* Setup idle mode (smart idle) */ + pio_change_32(&device->tll->sysconfig, + TLL_SYSCONFIG_CLOCKACTIVITY_FLAG | TLL_SYSCONFIG_AUTOIDLE_FLAG | + TLL_SYSCONFIG_SIDLE_MODE_SMART, TLL_SYSCONFIG_SIDLE_MODE_MASK, 5); + + /* Smart idle for UHH */ + pio_change_32(&device->uhh->sysconfig, + UHH_SYSCONFIG_CLOCKACTIVITY_FLAG | UHH_SYSCONFIG_AUTOIDLE_FLAG | + UHH_SYSCONFIG_SIDLE_MODE_SMART, UHH_SYSCONFIG_SIDLE_MODE_MASK, 5); + + /* Set all ports to go through TLL(UTMI) + * Direct connection can only work in HS mode */ + pio_set_32(&device->uhh->hostconfig, + UHH_HOSTCONFIG_P1_ULPI_BYPASS_FLAG | + UHH_HOSTCONFIG_P2_ULPI_BYPASS_FLAG | + UHH_HOSTCONFIG_P3_ULPI_BYPASS_FLAG, 5); + + /* What is this? */ + pio_set_32(&device->tll->shared_conf, TLL_SHARED_CONF_FCLK_IS_ON_FLAG, 5); + + for (unsigned i = 0; i < 3; ++i) { + /* Serial mode is the only one capable of FS/LS operation. + * Select FS/LS mode, no idea what the difference is + * one of bidirectional modes might be good choice + * 2 = 3pin bidi phy. */ + pio_change_32(&device->tll->channel_conf[i], + TLL_CHANNEL_CONF_CHANMODE_UTMI_SERIAL_MODE | + TLL_CHANNEL_CONF_FSLSMODE_3PIN_BIDI_PHY, + TLL_CHANNEL_CONF_CHANMODE_MASK | + TLL_CHANNEL_CONF_FSLSMODE_MASK, 5); + } + return EOK; +} Index: uspace/drv/infrastructure/rootamdm37x/amdm37x.h =================================================================== --- uspace/drv/infrastructure/rootamdm37x/amdm37x.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) +++ uspace/drv/infrastructure/rootamdm37x/amdm37x.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup amdm37xdrv + * @{ + */ +/** @file + * @brief AM/DM 37x device. + */ +#ifndef AMDM37x_H +#define AMDM37x_H + +#include "uhh.h" +#include "usbtll.h" + +#include "cm/core.h" +#include "cm/clock_control.h" +#include "cm/usbhost.h" +#include "cm/mpu.h" +#include "cm/iva2.h" + +#include "prm/clock_control.h" +#include "prm/global_reg.h" + +#include + +typedef struct { + uhh_regs_t *uhh; + tll_regs_t *tll; + struct { + mpu_cm_regs_t *mpu; + iva2_cm_regs_t *iva2; + core_cm_regs_t *core; + clock_control_cm_regs_t *clocks; + usbhost_cm_regs_t *usbhost; + } cm; + struct { + clock_control_prm_regs_t *clocks; + global_reg_prm_regs_t *global; + } prm; +} amdm37x_t; + +int amdm37x_init(amdm37x_t *device, bool trace_io); +int amdm37x_usb_tll_init(amdm37x_t *device); +void amdm37x_setup_dpll_on_autoidle(amdm37x_t *device); +void amdm37x_usb_clocks_set(amdm37x_t *device, bool enabled); + +#endif +/** + * @} + */ Index: uspace/drv/infrastructure/rootamdm37x/cm/clock_control.h =================================================================== --- uspace/drv/infrastructure/rootamdm37x/cm/clock_control.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) +++ uspace/drv/infrastructure/rootamdm37x/cm/clock_control.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup amdm37xdrvclockcontrolcm + * @{ + */ +/** @file + * @brief Clock Control Clock Management IO register structure. + */ +#ifndef AMDM37x_CLOCK_CONTROL_CM_H +#define AMDM37x_CLOCK_CONTROL_CM_H +#include +#include + +/* AM/DM37x TRM p.485 */ +#define CLOCK_CONTROL_CM_BASE_ADDRESS 0x48004d00 +#define CLOCK_CONTROL_CM_SIZE 8192 + +/** Clock control register map + * + * Periph DPLL == DPLL4 + * Core DPLL == DPLL3 + */ +typedef struct { + ioport32_t clken_pll; +#define CLOCK_CONTROL_CM_CLKEN_PLL_PWRDN_EMU_PERIPH_FLAG (1 << 31) +#define CLOCK_CONTROL_CM_CLKEN_PLL_PWRDN_CAM_FLAG (1 << 30) +#define CLOCK_CONTROL_CM_CLKEN_PLL_PWRDN_DSS1_FLAG (1 << 29) +#define CLOCK_CONTROL_CM_CLKEN_PLL_PWRDN_TV_FLAG (1 << 28) +#define CLOCK_CONTROL_CM_CLKEN_PLL_PWRDN_96M_FLAG (1 << 27) +#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH_DPLL_DRIFTGUARD_FLAG (1 << 19) +#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH_DPLL_MASK (0x7 << 16) +#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH_DPLL_LP_STOP (0x1 << 16) +#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH_DPLL_LOCK (0x7 << 16) +#define CLOCK_CONTROL_CM_CLKEN_PLL_PWRDN_EMU_CORE_FLAG (1 << 12) +#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_CORE_DPLL_LPMODE_FLAG (1 << 10) +#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_CORE_DPLL_DRIFTGUARD_FLAG (1 << 3) +#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_CORE_DPLL_MASK (0x7) +#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_CORE_DPLL_LP_BYPASS (0x5) +#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_CORE_DPLL_FAST_RELOCK (0x6) +#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_CORE_DPLL_LOCK (0x7) + + ioport32_t clken2_pll; +#define CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_LPMODE_FLAG (1 << 10) +#define CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_DRIFTGUARD_FLAG (1 << 3) +#define CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_MASK (0x7) +#define CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_LP_STOP (0x1) +#define CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_LOCK (0x7) + + PADD32[6]; + + const ioport32_t idlest_ckgen; +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_EMU_PERIPH_CLK_FLAG (1 << 13) +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_CAM_CLK_FLAG (1 << 12) +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_DSS1_CLK_FLAG (1 << 11) +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_TV_CLK_FLAG (1 << 10) +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_FUNC96M_CLK_FLAG (1 << 9) +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_EMU_CORE_CLK_FLAG (1 << 8) +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_54M_CLK_FLAG (1 << 5) +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_12M_CLK_FLAG (1 << 4) +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_48M_CLK_FLAG (1 << 3) +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_96M_CLK_FLAG (1 << 2) +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_PERIPH_CLK_FLAG (1 << 1) +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_CORE_CLK_FLAG (1 << 0) + + const ioport32_t idlest2_ckgen; +#define CLOCK_CONTROL_CM_IDLEST2_CKGEN_ST_FUNC120M_CLK_FLAG (1 << 3) +#define CLOCK_CONTROL_CM_IDLEST2_CKGEN_ST_120M_CLK_FLAG (1 << 1) +#define CLOCK_CONTROL_CM_IDLEST2_CKGEN_ST_PERIPH2_CLK_FLAG (1 << 0) + + PADD32[2]; + + ioport32_t autoidle_pll; +#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_MASK (0x7 << 3) +#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_DISABLED (0x0 << 3) +#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_AUTOMATIC (0x1 << 3) +#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_MASK (0x7) +#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_DISABLED (0x0) +#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_AUTOMATIC (0x1) +#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_AUTOMATIC_BYPASS (0x5) + + ioport32_t autoidle2_pll; +#define CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_MASK (0x7) +#define CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_DISABLED (0x0) +#define CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_AUTOMATIC (0x1) + + PADD32[2]; + + ioport32_t clksel1_pll; +#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27) +#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_CLKOUT_DIV_CREATE(x) (((x) & 0x1f) << 27) +#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_CLKOUT_DIV_GET(x) (((x) >> 27) & 0x1f) +#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_MULT_MASK (0x7ff << 16) +#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_MULT_CREATE(x) (((x) & 0x7ff) << 16) +#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_MULT_GET(x) (((x) >> 16) & 0x7ff) +#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_DIV_MASK (0x7f << 8) +#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_DIV_CREATE(x) (((x) & 0x7f) << 8) +#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_DIV_GET(x) (((x) >> 8) & 0x7f) +#define CLOCK_CONTROL_CM_CLKSEL1_PLL_SOURCE_96M_FLAG (1 << 6) +#define CLOCK_CONTROL_CM_CLKSEL1_PLL_SOURCE_54M_FLAG (1 << 5) +#define CLOCK_CONTROL_CM_CLKSEL1_PLL_SOURCE_48M_FLAG (1 << 3) + + ioport32_t clksel2_pll; +#define CLOCK_CONTROL_CM_CLKSEL2_PLL_SD_DIV_MASK (0xff << 24) +#define CLOCK_CONTROL_CM_CLKSEL2_PLL_SD_DIV_(x) (((x) & 0xff) << 24) +#define CLOCK_CONTROL_CM_CLKSEL2_PLL_DCO_SEL_MASK (0x7 << 21) +#define CLOCK_CONTROL_CM_CLKSEL2_PLL_DCO_SEL_500 (0x2 << 21) +#define CLOCK_CONTROL_CM_CLKSEL2_PLL_DCO_SEL_1000 (0x4 << 21) +#define CLOCK_CONTROL_CM_CLKSEL2_PLL_PERIPH_DPLL_MULT_MASK (0xfff << 8) +#define CLOCK_CONTROL_CM_CLKSEL2_PLL_PERIPH_DPLL_MULT(x) (((x) & 0xfff) << 8) +#define CLOCK_CONTROL_CM_CLKSEL2_PLL_PERIPH_DPLL_DIV_MASK (0x7f) +#define CLOCK_CONTROL_CM_CLKSEL2_PLL_PERIPH_DPLL_DIV(x) ((x) & 0x7f) + + ioport32_t clksel3_pll; +#define CLOCK_CONTROL_CM_CLKSEL3_PLL_DIV_96M_MASK (0xf) +#define CLOCK_CONTROL_CM_CLKSEL3_PLL_DIV_96M(x) ((x) & 0xf) + + ioport32_t clksel4_pll; +#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT_MASK (0x7ff << 8) +#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT_CREATE(x) (((x) & 0x7ff) << 8) +#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT_GET(x) (((x) >> 8) & 0x7ff) +#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV_MASK (0x7f) +#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV_CREATE(x) ((x) & 0x7f) +#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV_GET(x) ((x) & 0x7f) + + ioport32_t clksel5_pll; +#define CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M_MASK (0x1f) +#define CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M_CREATE(x) ((x) & 0x1f) +#define CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M_GET(x) ((x) & 0x1f) +} clock_control_cm_regs_t; + +#endif +/** + * @} + */ + Index: uspace/drv/infrastructure/rootamdm37x/cm/core.h =================================================================== --- uspace/drv/infrastructure/rootamdm37x/cm/core.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) +++ uspace/drv/infrastructure/rootamdm37x/cm/core.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -0,0 +1,188 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup amdm37xdrvcorecm + * @{ + */ +/** @file + * @brief CORE Clock Management IO register structure. + */ +#ifndef AMDM37x_CORE_CM_H +#define AMDM37x_CORE_CM_H +#include +#include + +/* AM/DM37x TRM p.447 */ +#define CORE_CM_BASE_ADDRESS 0x48004a00 +#define CORE_CM_SIZE 8192 + +typedef struct { + ioport32_t fclken1; +#define CORE_CM_FCLKEN1_EN_MCBSP1_FLAG (1 << 9) +#define CORE_CM_FCLKEN1_EN_MCBSP5_FLAG (1 << 10) +#define CORE_CM_FCLKEN1_EN_GPT10_FLAG (1 << 11) +#define CORE_CM_FCLKEN1_EN_GPT11_FLAG (1 << 12) +#define CORE_CM_FCLKEN1_EN_UART1_FLAG (1 << 13) +#define CORE_CM_FCLKEN1_EN_UART2_FLAG (1 << 14) +#define CORE_CM_FCLKEN1_EN_I2C1_FLAG (1 << 15) +#define CORE_CM_FCLKEN1_EN_I2C2_FLAG (1 << 16) +#define CORE_CM_FCLKEN1_EN_I2C3_FLAG (1 << 17) +#define CORE_CM_FCLKEN1_EN_MCSPI1_FLAG (1 << 18) +#define CORE_CM_FCLKEN1_EN_MCSPI2_FLAG (1 << 19) +#define CORE_CM_FCLKEN1_EN_MCSPI3_FLAG (1 << 20) +#define CORE_CM_FCLKEN1_EN_MCSPI4_FLAG (1 << 21) +#define CORE_CM_FCLKEN1_EN_HDQ_FLAG (1 << 22) +#define CORE_CM_FCLKEN1_EN_MMC1_FLAG (1 << 24) +#define CORE_CM_FCLKEN1_EN_MMC2_FLAG (1 << 25) +#define CORE_CM_FCLKEN1_EN_MMC3_FLAG (1 << 30) + + PADD32; + ioport32_t fclken3; +#define CORE_CM_FCLKEN3_EN_TS_FLAG (1 << 1) +#define CORE_CM_FCLKEN3_EN_USBTLL_FLAG (1 << 2) + + PADD32; + ioport32_t iclken1; +#define CORE_CM_ICLKEN1_EN_SDRC_FLAG (1 << 1) +#define CORE_CM_ICLKEN1_EN_HSOTGUSB_FLAG (1 << 4) +#define CORE_CM_ICLKEN1_EN_SCMCTRL_FLAG (1 << 6) +#define CORE_CM_ICLKEN1_EN_MAILBOXES_FLAG (1 << 7) +#define CORE_CM_ICLKEN1_EN_MCBSP1_FLAG (1 << 9) +#define CORE_CM_ICLKEN1_EN_MCBSP5_FLAG (1 << 10) +#define CORE_CM_ICLKEN1_EN_GPT10_FLAG (1 << 11) +#define CORE_CM_ICLKEN1_EN_GPT11_FLAG (1 << 12) +#define CORE_CM_ICLKEN1_EN_UART1_FLAG (1 << 13) +#define CORE_CM_ICLKEN1_EN_UART2_FLAG (1 << 14) +#define CORE_CM_ICLKEN1_EN_I2C1_FLAG (1 << 15) +#define CORE_CM_ICLKEN1_EN_I2C2_FLAG (1 << 16) +#define CORE_CM_ICLKEN1_EN_I2C3_FLAG (1 << 17) +#define CORE_CM_ICLKEN1_EN_MCSPI1_FLAG (1 << 18) +#define CORE_CM_ICLKEN1_EN_MCSPI2_FLAG (1 << 19) +#define CORE_CM_ICLKEN1_EN_MCSPI3_FLAG (1 << 20) +#define CORE_CM_ICLKEN1_EN_MCSPI4_FLAG (1 << 21) +#define CORE_CM_ICLKEN1_EN_HDQ_FLAG (1 << 22) +#define CORE_CM_ICLKEN1_EN_MMC1_FLAG (1 << 24) +#define CORE_CM_ICLKEN1_EN_MMC2_FLAG (1 << 25) +#define CORE_CM_ICLKEN1_EN_ICR_FLAG (1 << 29) +#define CORE_CM_ICLKEN1_EN_MMC3_FLAG (1 << 30) + + ioport32_t reserved1; + ioport32_t iclken3; +#define CORE_CM_ICLKEN3_EN_USBTLL_FLAG (1 << 2) + + PADD32; + const ioport32_t idlest1; +#define CORE_CM_IDLEST1_ST_SDRC_FLAG (1 << 1) +#define CORE_CM_IDLEST1_ST_SDMA_FLAG (1 << 2) +#define CORE_CM_IDLEST1_ST_HSOTGUSB_STBY_FLAG (1 << 4) +#define CORE_CM_IDLEST1_ST_HSOTGUSB_IDLE_FLAG (1 << 5) +#define CORE_CM_IDLEST1_ST_SCMCTRL_FLAG (1 << 6) +#define CORE_CM_IDLEST1_ST_MAILBOXES_FLAG (1 << 7) +#define CORE_CM_IDLEST1_ST_MCBSP1_FLAG (1 << 9) +#define CORE_CM_IDLEST1_ST_MCBSP5_FLAG (1 << 10) +#define CORE_CM_IDLEST1_ST_GPT10_FLAG (1 << 11) +#define CORE_CM_IDLEST1_ST_GPT11_FLAG (1 << 12) +#define CORE_CM_IDLEST1_ST_UART1_FLAG (1 << 13) +#define CORE_CM_IDLEST1_ST_UART2_FLAG (1 << 14) +#define CORE_CM_IDLEST1_ST_I2C1_FLAG (1 << 15) +#define CORE_CM_IDLEST1_ST_I2C2_FLAG (1 << 16) +#define CORE_CM_IDLEST1_ST_I2C3_FLAG (1 << 17) +#define CORE_CM_IDLEST1_ST_MCSPI1_FLAG (1 << 18) +#define CORE_CM_IDLEST1_ST_MCSPI2_FLAG (1 << 19) +#define CORE_CM_IDLEST1_ST_MCSPI3_FLAG (1 << 20) +#define CORE_CM_IDLEST1_ST_MCSPI4_FLAG (1 << 21) +#define CORE_CM_IDLEST1_ST_HDQ_FLAG (1 << 22) +#define CORE_CM_IDLEST1_ST_MMC1_FLAG (1 << 24) +#define CORE_CM_IDLEST1_ST_MMC2_FLAG (1 << 25) +#define CORE_CM_IDLEST1_ST_ICR_FLAG (1 << 29) +#define CORE_CM_IDLEST1_ST_MMC3_FLAG (1 << 30) + + const ioport32_t reserved2; + const ioport32_t idlest3; +#define CORE_CM_IDLEST3_ST_USBTLL_FLAG (1 << 2) + + PADD32; + ioport32_t autoidle1; +#define CORE_CM_AUTOIDLE1_AUTO_HSOTGUSB_FLAG (1 << 4) +#define CORE_CM_AUTOIDLE1_AUTO_SCMCTRL_FLAG (1 << 6) +#define CORE_CM_AUTOIDLE1_AUTO_MAILBOXES_FLAG (1 << 7) +#define CORE_CM_AUTOIDLE1_AUTO_MCBSP1_FLAG (1 << 9) +#define CORE_CM_AUTOIDLE1_AUTO_MCBSP5_FLAG (1 << 10) +#define CORE_CM_AUTOIDLE1_AUTO_GPT10_FLAG (1 << 11) +#define CORE_CM_AUTOIDLE1_AUTO_GPT11_FLAG (1 << 12) +#define CORE_CM_AUTOIDLE1_AUTO_UART1_FLAG (1 << 13) +#define CORE_CM_AUTOIDLE1_AUTO_UART2_FLAG (1 << 14) +#define CORE_CM_AUTOIDLE1_AUTO_I2C1_FLAG (1 << 15) +#define CORE_CM_AUTOIDLE1_AUTO_I2C2_FLAG (1 << 16) +#define CORE_CM_AUTOIDLE1_AUTO_I2C3_FLAG (1 << 17) +#define CORE_CM_AUTOIDLE1_AUTO_MCSPI1_FLAG (1 << 18) +#define CORE_CM_AUTOIDLE1_AUTO_MCSPI2_FLAG (1 << 19) +#define CORE_CM_AUTOIDLE1_AUTO_MCSPI3_FLAG (1 << 20) +#define CORE_CM_AUTOIDLE1_AUTO_MCSPI4_FLAG (1 << 21) +#define CORE_CM_AUTOIDLE1_AUTO_HDQ_FLAG (1 << 22) +#define CORE_CM_AUTOIDLE1_AUTO_MMC1_FLAG (1 << 24) +#define CORE_CM_AUTOIDLE1_AUTO_MMC2_FLAG (1 << 25) +#define CORE_CM_AUTOIDLE1_AUTO_ICR_FLAG (1 << 29) +#define CORE_CM_AUTOIDLE1_AUTO_MMC3_FLAG (1 << 30) + + ioport32_t reserved3; + ioport32_t autoidle3; +#define CORE_CM_AUTOIDLE3_AUTO_USBTLL_FLAG (1 << 2) + + PADD32; + ioport32_t clksel; +#define CORE_CM_CLKSEL_CLKSEL_L3_MASK (0x3 << 0) +#define CORE_CM_CLKSEL_CLKSEL_L3_DIVIDED1 (0x1 << 0) +#define CORE_CM_CLKSEL_CLKSEL_L3_DIVIDED2 (0x2 << 0) +#define CORE_CM_CLKSEL_CLKSEL_L4_MASK (0x3 << 2) +#define CORE_CM_CLKSEL_CLKSEL_L4_DIVIDED1 (0x1 << 2) +#define CORE_CM_CLKSEL_CLKSEL_L4_DIVIDED2 (0x2 << 2) +#define CORE_CM_CLKSEL_CLKSEL_96M_MASK (0x3 << 12) +#define CORE_CM_CLKSEL_CLKSEL_96M_DIVIDED1 (0x1 << 12) +#define CORE_CM_CLKSEL_CLKSEL_96M_DIVIDED2 (0x2 << 12) +#define CORE_CM_CLKSEL_CLKSEL_GPT10_FLAG (1 << 6) +#define CORE_CM_CLKSEL_CLKSEL_GPT11_FLAG (1 << 7) + + PADD32; + ioport32_t clkstctrl; +#define CORE_CM_CLKCTRL_CLKCTRL_L3_MASK (0x3 << 0) +#define CORE_CM_CLKCTRL_CLKCTRL_L3_AUTO_EN (0x0 << 0) +#define CORE_CM_CLKCTRL_CLKCTRL_L3_AUTO_DIS (0x3 << 0) +#define CORE_CM_CLKCTRL_CLKCTRL_L4_MASK (0x3 << 2) +#define CORE_CM_CLKCTRL_CLKCTRL_L4_AUTO_EN (0x0 << 2) +#define CORE_CM_CLKCTRL_CLKCTRL_L4_AUTO_DIS (0x3 << 2) + + const ioport32_t clkstst; +#define CORE_CM_CLKSTST_CLKACTIVITY_L3_FLAG (1 << 0) +#define CORE_CM_CLKSTST_CLKACTIVITY_L4_FLAG (1 << 1) +} core_cm_regs_t; + +#endif +/** + * @} + */ Index: uspace/drv/infrastructure/rootamdm37x/cm/iva2.h =================================================================== --- uspace/drv/infrastructure/rootamdm37x/cm/iva2.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) +++ uspace/drv/infrastructure/rootamdm37x/cm/iva2.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup amdm37xdrvcm + * @{ + */ +/** @file + * @brief MPU Clock Management IO register structure. + */ +#ifndef AMDM37x_IVA2_CM_H +#define AMDM37x_IVA2_CM_H +#include +#include + +/* AM/DM37x TRM p.446 */ +#define IVA2_CM_BASE_ADDRESS 0x48004000 +#define IVA2_CM_SIZE 8192 + +typedef struct { + ioport32_t fclken; +#define IVA2_CM_FCLKEN_EN_IVA2_FLAG (1 << 0) + + ioport32_t clken_pll; +#define IVA2_CM_CLKEN_PLL_EN_IVA2_DPLL_LP_MODE_FLAG (1 << 10) +#define IVA2_CM_CLKEN_PLL_EN_IVA2_DPLL_DRIFTGUARD (1 << 3) +#define IVA2_CM_CLKEN_PLL_EN_IVA2_DPLL_EN_IVA2_DPLL_MASK (0x7) +#define IVA2_CM_CLKEN_PLL_EN_IVA2_DPLL_EN_IVA2_DPLL_LP_STOP (0x1) +#define IVA2_CM_CLKEN_PLL_EN_IVA2_DPLL_EN_IVA2_DPLL_LP_BYPASS (0x5) +#define IVA2_CM_CLKEN_PLL_EN_IVA2_DPLL_EN_IVA2_DPLL_LOCKED (0x7) + + PADD32[6]; + const ioport32_t idlest; +#define IVA2_CM_IDLEST_ST_IVA2_STANDBY_FLAG (1 << 0) + + const ioport32_t idlest_pll; +#define IVA2_CM_IDLEST_PLL_ST_IVA2_CLK_LOCKED_FLAG (1 << 0) + + PADD32[3]; + ioport32_t autoidle_pll; +#define IVA2_CM_AUTOIDLE_PLL_AUTO_IVA2_DPLL_MASK (0x7) +#define IVA2_CM_AUTOIDLE_PLL_AUTO_IVA2_DPLL_DISABLED (0x0) +#define IVA2_CM_AUTOIDLE_PLL_AUTO_IVA2_DPLL_ENABLED (0x1) + + PADD32[2]; + ioport32_t clksel1_pll; +#define IVA2_CM_CLKSEL1_PLL_IVA2_CLK_SRC_MASK (0x7 << 19) +#define IVA2_CM_CLKSEL1_PLL_IVA2_CLK_SRC_SHIFT (19) +#define IVA2_CM_CLKSEL1_PLL_IVA2_CLK_SRC_VAL(x) ((x >> 19) & 0x7) +#define IVA2_CM_CLKSEL1_PLL_IVA2_CLK_SRC_CORE_DIV_1 (0x1 << 19) +#define IVA2_CM_CLKSEL1_PLL_IVA2_CLK_SRC_CORE_DIV_2 (0x2 << 19) +#define IVA2_CM_CLKSEL1_PLL_IVA2_CLK_SRC_CORE_DIV_4 (0x4 << 19) +#define IVA2_CM_CLKSEL1_PLL_IVA2_DPLL_MULT_MASK (0x7ff << 8) +#define IVA2_CM_CLKSEL1_PLL_IVA2_DPLL_MULT_SHIFT (8) +#define IVA2_CM_CLKSEL1_PLL_IVA2_DPLL_DIV_MASK (0x7f << 0) +#define IVA2_CM_CLKSEL1_PLL_IVA2_DPLL_DIV_SHIFT (0) + + ioport32_t clksel2_pll; +#define IVA2_CM_CLKSEL2_PLL_IVA2_DPLL_CLKOUT_DIV_MASK (0x1f) + + ioport32_t clkstctrl; +#define IVA2_CM_CLKSCTRL_CLKTRCTRL_IVA2_MASK (0x3) +#define IVA2_CM_CLKSCTRL_CLKTRCTRL_IVA2_DISABLED (0x0) +#define IVA2_CM_CLKSCTRL_CLKTRCTRL_IVA2_START_SLEEP (0x2) +#define IVA2_CM_CLKSCTRL_CLKTRCTRL_IVA2_START_WAKEUP (0x2) +#define IVA2_CM_CLKSCTRL_CLKTRCTRL_IVA2_AUTOMATIC (0x3) + + const ioport32_t clkstst; +#define IVA2_CM_CLKSTST_CLKACTIVITY_IVA2_ACTIVE_FLAG (1 << 0) + +} iva2_cm_regs_t; + +#endif +/** + * @} + */ + Index: uspace/drv/infrastructure/rootamdm37x/cm/mpu.h =================================================================== --- uspace/drv/infrastructure/rootamdm37x/cm/mpu.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) +++ uspace/drv/infrastructure/rootamdm37x/cm/mpu.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup amdm37xdrvcm + * @{ + */ +/** @file + * @brief MPU Clock Management IO register structure. + */ +#ifndef AMDM37x_MPU_CM_H +#define AMDM37x_MPU_CM_H +#include +#include + +/* AM/DM37x TRM p.455 */ +#define MPU_CM_BASE_ADDRESS 0x48004900 +#define MPU_CM_SIZE 8192 + +typedef struct { + PADD32; + ioport32_t clken_pll; +#define MPU_CM_CLKEN_PLL_EN_MPU_DPLL_LP_MODE_FLAG (1 << 10) +#define MPU_CM_CLKEN_PLL_EN_MPU_DPLL_DRIFTGUARD (1 << 3) +#define MPU_CM_CLKEN_PLL_EN_MPU_DPLL_EN_MPU_DPLL_MASK (0x7) +#define MPU_CM_CLKEN_PLL_EN_MPU_DPLL_EN_MPU_DPLL_LP_BYPASS (0x5) +#define MPU_CM_CLKEN_PLL_EN_MPU_DPLL_EN_MPU_DPLL_LOCKED (0x7) + + PADD32[6]; + const ioport32_t idlest; +#define MPU_CM_IDLEST_ST_MPU_STANDBY_FLAG (1 << 0) + + const ioport32_t idlest_pll; +#define MPU_CM_IDLEST_PLL_ST_MPU_CLK_LOCKED_FLAG (1 << 0) + + PADD32[3]; + ioport32_t autoidle_pll; +#define MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_MASK (0x7) +#define MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_DISABLED (0x0) +#define MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_ENABLED (0x1) + + PADD32[2]; + ioport32_t clksel1_pll; +#define MPU_CM_CLKSEL1_PLL_MPU_CLK_SRC_MASK (0x7 << 19) +#define MPU_CM_CLKSEL1_PLL_MPU_CLK_SRC_SHIFT (19) +#define MPU_CM_CLKSEL1_PLL_MPU_CLK_SRC_VAL(x) ((x >> 19) & 0x7) +#define MPU_CM_CLKSEL1_PLL_MPU_CLK_SRC_CORE_DIV_1 (0x1 << 19) +#define MPU_CM_CLKSEL1_PLL_MPU_CLK_SRC_CORE_DIV_2 (0x2 << 19) +#define MPU_CM_CLKSEL1_PLL_MPU_CLK_SRC_CORE_DIV_4 (0x4 << 19) +#define MPU_CM_CLKSEL1_PLL_MPU_DPLL_MULT_MASK (0x7ff << 8) +#define MPU_CM_CLKSEL1_PLL_MPU_DPLL_MULT_SHIFT (8) +#define MPU_CM_CLKSEL1_PLL_MPU_DPLL_DIV_MASK (0x7f << 0) +#define MPU_CM_CLKSEL1_PLL_MPU_DPLL_DIV_SHIFT (0) + + ioport32_t clksel2_pll; +#define MPU_CM_CLKSEL2_PLL_MPU_DPLL_CLKOUT_DIV_MASK (0x1f) + + ioport32_t clkstctrl; +#define MPU_CM_CLKSCTRL_CLKTRCTRL_MPU_MASK (0x3) +#define MPU_CM_CLKSCTRL_CLKTRCTRL_MPU_DISABLED (0x0) +#define MPU_CM_CLKSCTRL_CLKTRCTRL_MPU_START_WAKEUP (0x2) +#define MPU_CM_CLKSCTRL_CLKTRCTRL_MPU_AUTOMATIC (0x3) + + const ioport32_t clkstst; +#define MPU_CM_CLKSTST_CLKACTIVITY_MPU_ACTIVE_FLAG (1 << 0) + +} mpu_cm_regs_t; + +#endif +/** + * @} + */ + Index: uspace/drv/infrastructure/rootamdm37x/cm/usbhost.h =================================================================== --- uspace/drv/infrastructure/rootamdm37x/cm/usbhost.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) +++ uspace/drv/infrastructure/rootamdm37x/cm/usbhost.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup amdm37xdrvusbhostcm + * @{ + */ +/** @file + * @brief USBHOST Clock Management IO register structure. + */ +#ifndef AMDM37x_USBHOST_CM_H +#define AMDM37x_USBHOST_CM_H +#include +#include + +/* AM/DM37x TRM p.447 */ +#define USBHOST_CM_BASE_ADDRESS 0x48005400 +#define USBHOST_CM_SIZE 8192 + +typedef struct { + ioport32_t fclken; +#define USBHOST_CM_FCLKEN_EN_USBHOST1_FLAG (1 << 0) +#define USBHOST_CM_FCLKEN_EN_USBHOST2_FLAG (1 << 1) + + PADD32[3]; + ioport32_t iclken; +#define USBHOST_CM_ICLKEN_EN_USBHOST (1 << 0) + + PADD32[3]; + const ioport32_t idlest; +#define USBHOST_CM_IDLEST_ST_USBHOST_STDBY_FLAG (1 << 0) +#define USBHOST_CM_IDLEST_ST_USBHOST_IDLE_FLAG (1 << 1) + + PADD32[3]; + ioport32_t autoidle; +#define USBHOST_CM_AUTOIDLE_AUTO_USBHOST_FLAG (1 << 0) + + PADD32[4]; + ioport32_t sleepdep; +#define USBHOST_CM_SLEEPDEP_EN_MPU_FLAG (1 << 1) +#define USBHOST_CM_SLEEPDEP_EN_IVA2_FLAG (1 << 2) + + ioport32_t clkstctrl; +#define USBHOST_CM_CLKSTCTRL_CLKSTCTRL_USBHOST_MASK (0x3 << 0) +#define USBHOST_CM_CLKSTCTRL_CLKSTCTRL_USBHOST_AUTO_DIS (0x0 << 0) +#define USBHOST_CM_CLKSTCTRL_CLKSTCTRL_USBHOST_SUPERVISED_SLEEP (0x1 << 0) +#define USBHOST_CM_CLKSTCTRL_CLKSTCTRL_USBHOST_SUPERVISED_WAKEUP (0x2 << 0) +#define USBHOST_CM_CLKSTCTRL_CLKSTCTRL_USBHOST_AUTO_EN (0x3 << 0) + + ioport32_t clkstst; +#define USBHOST_CM_CLKSTCTRL_CLKSTST_CLKACTIVITY_USBHOST (1 << 0) +} usbhost_cm_regs_t; + +#endif +/** + * @} + */ + Index: uspace/drv/infrastructure/rootamdm37x/prm/clock_control.h =================================================================== --- uspace/drv/infrastructure/rootamdm37x/prm/clock_control.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) +++ uspace/drv/infrastructure/rootamdm37x/prm/clock_control.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup amdm37xdrvprm + * @{ + */ +/** @file + * @brief Clock Control Clock Management IO register structure. + */ +#ifndef AMDM37X_PRM_CLOCK_CONTROL_H +#define AMDM37X_PRM_CLOCK_CONTROL_H +#include +#include + +/* AM/DM37x TRM p.536 and p.589 */ +#define CLOCK_CONTROL_PRM_BASE_ADDRESS 0x48306d00 +#define CLOCK_CONTROL_PRM_SIZE 8192 + +/** Clock control PRM register map + */ +typedef struct { + PADD32[16]; + ioport32_t clksel; +#define CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_MASK (0x7) +#define CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_12M (0x0) +#define CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_13M (0x1) +#define CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_19_2M (0x2) +#define CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_26M (0x3) +#define CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_38_4M (0x4) +#define CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_16_8M (0x5) + + PADD32[12]; + ioport32_t clkout_ctrl; +#define CLOCK_CONTROL_PRM_CLKOUT_CTRL_CLKOUOUT_EN_FLAG (1 << 7) + +} clock_control_prm_regs_t; + +static inline unsigned sys_clk_freq_kHz(unsigned reg_val) +{ + switch(reg_val) + { + case CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_12M: return 12000; + case CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_13M: return 13000; + case CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_19_2M: return 19200; + case CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_26M: return 26000; + case CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_38_4M: return 38400; + case CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_16_8M: return 16800; + } + return 0; +} + + +#endif +/** + * @} + */ Index: uspace/drv/infrastructure/rootamdm37x/prm/global_reg.h =================================================================== --- uspace/drv/infrastructure/rootamdm37x/prm/global_reg.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) +++ uspace/drv/infrastructure/rootamdm37x/prm/global_reg.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -0,0 +1,300 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup amdm37xdrvprm + * @{ + */ +/** @file + * @brief Clock Control Clock Management IO register structure. + */ +#ifndef AMDM37X_PRM_GLOBAL_REG_H +#define AMDM37X_PRM_GLOBAL_REG_H +#include +#include + +/* AM/DM37x TRM p.536 and p.615 */ +#define GLOBAL_REG_PRM_BASE_ADDRESS 0x48307200 +#define GLOBAL_REG_PRM_SIZE 65536 + +/** Global Reg PRM register map + */ +typedef struct { + PADD32[8]; + struct { + ioport32_t smps_sa; +#define GLOBAL_REG_PRM_VC_SMPS_SA_SA0_MASK (0x7f << 0) +#define GLOBAL_REG_PRM_VC_SMPS_SA_SA0_CREATE(x) (((x) & 0x7f) << 0) +#define GLOBAL_REG_PRM_VC_SMPS_SA_SA0_GET(r) (r & 0x7f) +#define GLOBAL_REG_PRM_VC_SMPS_SA_SA1_MASK (0x7f << 16) +#define GLOBAL_REG_PRM_VC_SMPS_SA_SA1_CREATE(x) (((x) & 0x7f) << 16) +#define GLOBAL_REG_PRM_VC_SMPS_SA_SA1_GET(r) (((r) >> 16 ) & 0x7f) + + ioport32_t smps_vol_ra; +#define GLOBAL_REG_PRM_VC_SMPS_VOL_RA_VOLRA0_MASK (0xff << 0) +#define GLOBAL_REG_PRM_VC_SMPS_VOL_RA_VOLRA0_CREATE(x) (((x) & 0xff) << 0) +#define GLOBAL_REG_PRM_VC_SMPS_VOL_RA_VOLRA0_GET(r) (r & 0xff) +#define GLOBAL_REG_PRM_VC_SMPS_VOL_RA_VOLRA1_MASK (0xff << 16) +#define GLOBAL_REG_PRM_VC_SMPS_VOL_RA_VOLRA1_CREATE(x) (((x) & 0xff) << 16) +#define GLOBAL_REG_PRM_VC_SMPS_VOL_RA_VOLRA1_GET(r) (((r) >> 16 ) & 0xff) + + ioport32_t smps_cmd_ra; +#define GLOBAL_REG_PRM_VC_SMPS_CMD_RA_CMDRA0_MASK (0xff << 0) +#define GLOBAL_REG_PRM_VC_SMPS_CMD_RA_CMDRA0_CREATE(x) (((x) & 0xff) << 0) +#define GLOBAL_REG_PRM_VC_SMPS_CMD_RA_CMDRA0_GET(r) (r & 0xff) +#define GLOBAL_REG_PRM_VC_SMPS_CMD_RA_CMDRA1_MASK (0xff << 16) +#define GLOBAL_REG_PRM_VC_SMPS_CMD_RA_CMDRA1_CREATE(x) (((x) & 0xff) << 16) +#define GLOBAL_REG_PRM_VC_SMPS_CMD_RA_CMDRA1_GET(r) (((r) >> 16 ) & 0xff) + + ioport32_t cmd_val_0; +#define GLOBAL_REG_PRM_VC_CMD_VAL_0_ON_MASK (0xff << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_0_ON_CREATE(x) (((x) & 0xff) << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_0_ON_GET(r) (((x) >> 24) & 0xff) +#define GLOBAL_REG_PRM_VC_CMD_VAL_0_ONLP_MASK (0xff << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_0_ONLP_CREATE(x) (((x) & 0xff) << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_0_ONLP_GET(r) (((x) >> 24) & 0xff) +#define GLOBAL_REG_PRM_VC_CMD_VAL_0_RET_MASK (0xff << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_0_RET_CREATE(x) (((x) & 0xff) << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_0_RET_GET(r) (((x) >> 24) & 0xff) +#define GLOBAL_REG_PRM_VC_CMD_VAL_0_OFF_MASK (0xff << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_0_OFF_CREATE(x) (((x) & 0xff) << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_0_OFF_GET(r) (((x) >> 24) & 0xff) + + ioport32_t cmd_val_1; +#define GLOBAL_REG_PRM_VC_CMD_VAL_1_ON_MASK (0xff << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_1_ON_CREATE(x) (((x) & 0xff) << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_1_ON_GET(r) (((x) >> 24) & 0xff) +#define GLOBAL_REG_PRM_VC_CMD_VAL_1_ONLP_MASK (0xff << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_1_ONLP_CREATE(x) (((x) & 0xff) << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_1_ONLP_GET(r) (((x) >> 24) & 0xff) +#define GLOBAL_REG_PRM_VC_CMD_VAL_1_RET_MASK (0xff << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_1_RET_CREATE(x) (((x) & 0xff) << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_1_RET_GET(r) (((x) >> 24) & 0xff) +#define GLOBAL_REG_PRM_VC_CMD_VAL_1_OFF_MASK (0xff << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_1_OFF_CREATE(x) (((x) & 0xff) << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_1_OFF_GET(r) (((x) >> 24) & 0xff) + + ioport32_t ch_conf; +#define GLOBAL_REG_PRM_VC_CH_CONF_CMD1_FLAG (1 << 20) +#define GLOBAL_REG_PRM_VC_CH_CONF_RACEN1_FLAG (1 << 19) +#define GLOBAL_REG_PRM_VC_CH_CONF_RAC1_FLAG (1 << 18) +#define GLOBAL_REG_PRM_VC_CH_CONF_RAV1_FLAG (1 << 17) +#define GLOBAL_REG_PRM_VC_CH_CONF_SA1_FLAG (1 << 16) +#define GLOBAL_REG_PRM_VC_CH_CONF_CMD0_FLAG (1 << 4) +#define GLOBAL_REG_PRM_VC_CH_CONF_RACEN0_FLAG (1 << 3) +#define GLOBAL_REG_PRM_VC_CH_CONF_RAC0_FLAG (1 << 2) +#define GLOBAL_REG_PRM_VC_CH_CONF_RAV0_FLAG (1 << 1) +#define GLOBAL_REG_PRM_VC_CH_CONF_SA0_FLAG (1 << 0) + + ioport32_t i2c_cfg; +#define GLOBAL_REG_PRM_VC_I2C_CFG_HSMASTER_FLAG (1 << 5) +#define GLOBAL_REG_PRM_VC_I2C_CFG_SREN_FLAG (1 << 4) +#define GLOBAL_REG_PRM_VC_I2C_CFG_HSEN_FLAG (1 << 3) +#define GLOBAL_REG_PRM_VC_I2C_CFG_MCODE_MASK (0x3 << 0) +#define GLOBAL_REG_PRM_VC_I2C_CFG_MCODE_CREATE(x) ((x) & 0x3) +#define GLOBAL_REG_PRM_VC_I2C_CFG_MCODE_GET(r) ((r) & 0x3) + + ioport32_t bypass_val; +#define GLOBAL_REG_PRM_VC_BYPASS_VAL_VALID_FLAG (1 << 24) +#define GLOBAL_REG_PRM_VC_BYPASS_VAL_DATA_MASK (0xff << 16) +#define GLOBAL_REG_PRM_VC_BYPASS_VAL_DATA_CREATE(x) (((x) & 0xff) << 16) +#define GLOBAL_REG_PRM_VC_BYPASS_VAL_DATA_GET(r) (((r) >> 16) & 0xff) +#define GLOBAL_REG_PRM_VC_BYPASS_VAL_REGADDR_MASK (0xff << 8) +#define GLOBAL_REG_PRM_VC_BYPASS_VAL_REGADDR_CREATE(x) (((x) & 0xff) << 8) +#define GLOBAL_REG_PRM_VC_BYPASS_VAL_REGADDR_GET(r) (((r) >> 8) & 0xff) +#define GLOBAL_REG_PRM_VC_BYPASS_VAL_SLAVEADDR_MASK (0x7f << 0) +#define GLOBAL_REG_PRM_VC_BYPASS_VAL_SLAVEADDR_CREATE(x) (((x) & 0x7f) << 0) +#define GLOBAL_REG_PRM_VC_BYPASS_VAL_SLAVEADDR_GET(r) (((r) >> 0) & 0x7f) + } vc; + + PADD32[4]; + ioport32_t rstctrl; +#define GLOBAL_REG_PRM_RSTCTRL_RST_DPLL3_FLAG (1 << 2) +#define GLOBAL_REG_PRM_RSTCTRL_RST_GS_FLAG (1 << 1) + + ioport32_t rsttime; +#define GLOBAL_REG_PRM_RSTTIME_RSTTIME2_MASK (0x1f << 8) +#define GLOBAL_REG_PRM_RSTTIME_RSTTIME2_CREATE(x) (((x) & 0x1f) << 8) +#define GLOBAL_REG_PRM_RSTTIME_RSTTIME2_GET(r) (((r) >> 8) & 0x1f) +#define GLOBAL_REG_PRM_RSTTIME_RSTTIME1_MASK (0xff << 0) +#define GLOBAL_REG_PRM_RSTTIME_RSTTIME1_CREATE(x) (((x) & 0xff) << 0) +#define GLOBAL_REG_PRM_RSTTIME_RSTTIME1_GET(r) (((r) >> 0) & 0xff) + + ioport32_t rstst; +#define GLOBAL_REG_PRM_RSTST_ICECRUSHER_RST_FLAG (1 << 10) +#define GLOBAL_REG_PRM_RSTST_ICEPICK_RST_FLAG (1 << 9) +#define GLOBAL_REG_PRM_RSTST_VDD2_VOLTAGE_MGR_RST_FLAG (1 << 8) +#define GLOBAL_REG_PRM_RSTST_VDD1_VOLTAGE_MGR_RST_FLAG (1 << 7) +#define GLOBAL_REG_PRM_RSTST_EXTERNAL_WARM_REST_FLAG (1 << 6) +#define GLOBAL_REG_PRM_RSTST_MPU_WD_RST_FLAG (1 << 4) +#define GLOBAL_REG_PRM_RSTST_GLOBAL_SW_RST_FLAG (1 << 1) +#define GLOBAL_REG_PRM_RSTST_GLOABL_COLD_RST_FLAG (1 << 0) + + PADD32; + ioport32_t volctrl; +#define GLOBAL_REG_PRM_VOLCTRL_SEL_VMODE_FLAG (1 << 4) +#define GLOBAL_REG_PRM_VOLCTRL_SEL_OFF_FLAG (1 << 3) +#define GLOBAL_REG_PRM_VOLCTRL_AUTO_OFF_FLAG (1 << 2) +#define GLOBAL_REG_PRM_VOLCTRL_AUTO_RET_FLAG (1 << 1) +#define GLOBAL_REG_PRM_VOLCTRL_AUTO_SLEEP_FLAG (1 << 0) + + ioport32_t sram_pcharge; +#define GLOBAL_REG_PRM_SRAM_PCHARGE_PCHARGE_TIME_MASK (0xff) +#define GLOBAL_REG_PRM_SRAM_PCHARGE_PCHARGE_TIME_CREATE(x) ((x) & 0xff) +#define GLOBAL_REG_PRM_SRAM_PCHARGE_PCHARGE_TIME_GET(r) ((r) & 0xff) + + PADD32[2]; + ioport32_t clksrc_ctrl; +#define GLOBAL_REG_PRM_CLKSRC_CTRL_DPLL4_CLKINP_DIV_65_FLAG (1 << 8) +#define GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKDIV_MASK (0x3 << 6) +#define GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKDIV_1 (0x1 << 6) +#define GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKDIV_2 (0x2 << 6) +#define GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKDIV_GET(r) (((r) >> 6) & 0x3) +#define GLOBAL_REG_PRM_CLKSRC_CTRL_AUTOEXTCLKMODE_MASK (0x3 << 3) +#define GLOBAL_REG_PRM_CLKSRC_CTRL_AUTOEXTCLKMODE_ON (0x0 << 3) +#define GLOBAL_REG_PRM_CLKSRC_CTRL_AUTOEXTCLKMODE_SLEEP (0x1 << 3) +#define GLOBAL_REG_PRM_CLKSRC_CTRL_AUTOEXTCLKMODE_RET (0x2 << 3) +#define GLOBAL_REG_PRM_CLKSRC_CTRL_AUTOEXTCLKMODE_OFF (0x3 << 3) +#define GLOBAL_REG_PRM_CLKSRC_CTRL_AUTOEXTCLKMODE_GET(r) (((r) >> 3) & 0x3) +#define GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKSEL_MASK (0x3 << 0) +#define GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKSEL_BYPASS (0x0 << 0) +#define GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKSEL_OSCILLATOR (0x1 << 0) +#define GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKSEL_UNKNOWN (0x3 << 0) +#define GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKSEL_GET(r) (((r) >> 0) & 0x3) + + PADD32[3]; + const ioport32_t obs; +#define GLOBAL_REG_PRM_OBS_OBS_BUS_MASK (0x3ff) + + PADD32[3]; + ioport32_t voltsetup1; +#define GLOBAL_REG_PRM_VOLTSETUP1_SETUPTIME2_MASK (0xff << 16) +#define GLOBAL_REG_PRM_VOLTSETUP1_SETUPTIME2_CREATE(x) (((x) & 0xff) << 16) +#define GLOBAL_REG_PRM_VOLTSETUP1_SETUPTIME2_GET(r) (((r) >> 16) & 0xff) +#define GLOBAL_REG_PRM_VOLTSETUP1_SETUPTIME1_MASK (0xff << 0) +#define GLOBAL_REG_PRM_VOLTSETUP1_SETUPTIME1_CREATE(x) (((x) & 0xff) << 0) +#define GLOBAL_REG_PRM_VOLTSETUP1_SETUPTIME1_GET(r) (((r) >> 0) & 0xff) + + ioport32_t voltoffset; +#define GLOBAL_REG_PRM_VOLTOFFSET_OFFSET_TIME_MASK (0xffff << 0) +#define GLOBAL_REG_PRM_VOLTOFFSET_OFFSET_TIME_CREATE(x) (((x) & 0xffff) << 0) +#define GLOBAL_REG_PRM_VOLTOFFSET_OFFSET_TIME_GET(r) (((r) >> 0) & 0xffff) + + ioport32_t clksetup; +#define GLOBAL_REG_PRM_CLKSETUP_SETUP_TIME_MASK (0xffff << 0) +#define GLOBAL_REG_PRM_CLKSETUP_SETUP_TIME_CREATE(x) (((x) & 0xffff) << 0) +#define GLOBAL_REG_PRM_CLKSETUP_SETUP_TIME_GET(r) (((r) >> 0) & 0xffff) + + ioport32_t polctrl; +#define GLOBAL_REG_PRM_POLCTRL_OFFMODE_POL_FLAG (1 << 3) +#define GLOBAL_REG_PRM_POLCTRL_CLKOUT_POL_FLAG (1 << 2) +#define GLOBAL_REG_PRM_POLCTRL_CLKREG_POL_FLAG (1 << 1) +#define GLOBAL_REG_PRM_POLCTRL_EXTVOL_POL_FLAG (1 << 0) + + ioport32_t voltsetup2; +#define GLOBAL_REG_PRM_VOLTSETUP2_OFFMODESETUPTIME_MASK (0xffff << 0) +#define GLOBAL_REG_PRM_VOLTSETUP2_OFFMODESETUPTIME_CREATE(x) (((x) & 0xffff) << 0) +#define GLOBAL_REG_PRM_VOLTSETUP2_OFFMODESETUPTIME_GET(r) (((r) >> 0) & 0xffff) + + PADD32[3]; + struct { + ioport32_t config; +#define GLOBAL_REG_PRM_VP_CONFIG_ERROROFFSET_MASK (0xff << 24) +#define GLOBAL_REG_PRM_VP_CONFIG_ERROROFFSET_CREATE(x) (((x) & 0xff) << 24) +#define GLOBAL_REG_PRM_VP_CONFIG_ERROROFFSET_GET(r) (((r) >> 0xff << 24) +#define GLOBAL_REG_PRM_VP_CONFIG_ERRORGAIN_MASK (0xff << 16) +#define GLOBAL_REG_PRM_VP_CONFIG_ERRORGAIN_CREATE(x) (((x) & 0xff) << 16) +#define GLOBAL_REG_PRM_VP_CONFIG_ERRORGAIN_GET(r) (((r) >> 0xff << 16) +#define GLOBAL_REG_PRM_VP_CONFIG_INITVOLTAGE_MASK (0xff << 8) +#define GLOBAL_REG_PRM_VP_CONFIG_INITVOLTAGE_CREATE(x) (((x) & 0xff) << 8) +#define GLOBAL_REG_PRM_VP_CONFIG_INITVOLTAGE_GET(r) (((r) >> 0xff << 8) +#define GLOBAL_REG_PRM_VP_CONFIG_TIMEOUTEN_FLAG (1 << 3) +#define GLOBAL_REG_PRM_VP_CONFIG_INITVDD_FLAG (1 << 2) +#define GLOBAL_REG_PRM_VP_CONFIG_FORCEUPDATE_FLAG (1 << 1) +#define GLOBAL_REG_PRM_VP_CONFIG_VPENABLE_FLAG (1 << 0) + + ioport32_t vstepmin; +#define GLOBAL_REG_PRM_VP_VSTEPMIN_SMPSWAITTIMEMIN_MASK (0xffff << 8) +#define GLOBAL_REG_PRM_VP_VSTEPMIN_SMPSWAITTIMEMIN_CREATE(x) (((x)0xffff << 8) +#define GLOBAL_REG_PRM_VP_VSTEPMIN_SMPSWAITTIMEMIN_GET(r) (((r) >> 8) & 0xffff) +#define GLOBAL_REG_PRM_VP_VSTEPMIN_VSTEPMIN_MASK (0xff << 0) +#define GLOBAL_REG_PRM_VP_VSTEPMIN_VSTEPMIN_CREATE(x) (((x)0xff << 0) +#define GLOBAL_REG_PRM_VP_VSTEPMIN_VSTEPMIN_GET(r) (((r) >> 0) & 0xff) + + ioport32_t vstepmax; +#define GLOBAL_REG_PRM_VP_VSTEPMAX_SMPSWAITTIMEMIN_MASK (0xffff << 8) +#define GLOBAL_REG_PRM_VP_VSTEPMAX_SMPSWAITTIMEMIN_CREATE(x) (((x)0xffff << 8) +#define GLOBAL_REG_PRM_VP_VSTEPMAX_SMPSWAITTIMEMIN_GET(r) (((r) >> 8) & 0xffff) +#define GLOBAL_REG_PRM_VP_VSTEPMAX_VSTEPMIN_MASK (0xff << 0) +#define GLOBAL_REG_PRM_VP_VSTEPMAX_VSTEPMIN_CREATE(x) (((x)0xff << 0) +#define GLOBAL_REG_PRM_VP_VSTEPMAX_VSTEPMIN_GET(r) (((r) >> 0) & 0xff) + + ioport32_t vlimitto; +#define GLOBAL_REG_PRM_VP_VLIMITTO_VDDMAX_MASK (0xff << 24) +#define GLOBAL_REG_PRM_VP_VLIMITTO_VDDMAX_CREATE(x) (((x)0xff << 24) +#define GLOBAL_REG_PRM_VP_VLIMITTO_VDDMAX_GET(r) (((r) >> 24) & 0xff) +#define GLOBAL_REG_PRM_VP_VLIMITTO_VDDMIN_MASK (0xff << 16) +#define GLOBAL_REG_PRM_VP_VLIMITTO_VDDMIN_CREATE(x) (((x)0xff << 16) +#define GLOBAL_REG_PRM_VP_VLIMITTO_VDDMIN_GET(r) (((r) >> 16) & 0xff) +#define GLOBAL_REG_PRM_VP_VLIMITTO_TIMEOUT_MASK (0xffff << 0) +#define GLOBAL_REG_PRM_VP_VLIMITTO_TIMEOUT_CREATE(x) (((x)0xffff << 0) +#define GLOBAL_REG_PRM_VP_VLIMITTO_TIMEOUT_GET(r) (((r) >> 0) & 0xffff) + + const ioport32_t voltage; +#define GLOBAL_REG_PRM_VP_VOLTAGE_VPVOLTAGE_MASK (0xff) +#define GLOBAL_REG_PRM_VP_VOLTAGE_VPVOLTAGE_GET(r) ((r) & 0xff) + + const ioport32_t status; +#define GLOBAL_REG_PRM_VP_STATUS_VPINIDLE_FLAG (1 << 0) + + PADD32[2]; + } vp[2]; + + ioport32_t ldo_abb_setup; +#define GLOBAL_REG_PRM_LDO_ABB_SETUP_SR2_IN_TRANSITION (1 << 6) +#define GLOBAL_REG_PRM_LDO_ABB_SETUP_SR2_STATUS_MASK (0x3 << 3) +#define GLOBAL_REG_PRM_LDO_ABB_SETUP_SR2_STATUS_BYPASS (0x0 << 3) +#define GLOBAL_REG_PRM_LDO_ABB_SETUP_SR2_STATUS_FBB (0x2 << 3) +#define GLOBAL_REG_PRM_LDO_ABB_SETUP_SR2_OPP_CHANGE_FLAG (1 << 2) +#define GLOBAL_REG_PRM_LDO_ABB_SETUP_OPP_SEL_MASK (0x3 << 0) +#define GLOBAL_REG_PRM_LDO_ABB_SETUP_OPP_SEL_DEFAULT (0x0 << 0) +#define GLOBAL_REG_PRM_LDO_ABB_SETUP_OPP_SEL_FAST (0x1 << 0) +#define GLOBAL_REG_PRM_LDO_ABB_SETUP_OPP_SEL_NOMINAL (0x2 << 0) +#define GLOBAL_REG_PRM_LDO_ABB_SETUP_OPP_SEL_SLOW (0x3 << 0) + + ioport32_t ldo_abb_ctrl; +#define GLOBAL_REG_PRM_LDO_ABB_CTRL_SR2_WTCNT_VALUE_MASK (0xff << 8) +#define GLOBAL_REG_PRM_LDO_ABB_CTRL_SR2_WTCNT_VALUE_CREATE(x) (((x) & 0xff) << 8) +#define GLOBAL_REG_PRM_LDO_ABB_CTRL_SR2_WTCNT_VALUE_GET(r) (((r) >> 8) & 0xff) +#define GLOBAL_REG_PRM_LDO_ABB_CTRL_ACTIVE_FBB_SEL_FLAG (1 << 2) +#define GLOBAL_REG_PRM_LDO_ABB_CTRL_SR2EN (1 << 0) +} global_reg_prm_regs_t; + +#endif +/** + * @} + */ Index: uspace/drv/infrastructure/rootamdm37x/prm/usbhost.h =================================================================== --- uspace/drv/infrastructure/rootamdm37x/prm/usbhost.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) +++ uspace/drv/infrastructure/rootamdm37x/prm/usbhost.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup amdm37xdrvprm + * @{ + */ +/** @file + * @brief Clock Control Clock Management IO register structure. + */ +#ifndef AMDM37X_PRM_CLOCK_CONTROL_H +#define AMDM37X_PRM_CLOCK_CONTROL_H +#include +#include + +/* AM/DM37x TRM p.536 and p.589 */ +#define CLOCK_CONTROL_CM_BASE_ADDRESS 0x48307400 +#define CLOCK_CONTROL_CM_SIZE 8192 + +/** Clock control PRM register map + * + * Periph DPLL == DPLL4 + * Core DPLL == DPLL3 + */ +typedef struct { + PADD32[22]; + ioport32_t rm_rstst; +#define USBHOST_PRM_RM_RSTST_COREDOMAINWKUP_RST_FLAG (1 << 3) +#define USBHOST_PRM_RM_RSTST_DOMAINWKUP_RST_FLAG (1 << 2) +#define USBHOST_PRM_RM_RSTST_GLOBALWARM_RST_FLAG (1 << 1) +#define USBHOST_PRM_RM_RSTST_GLOBALCOLD_RST_FLAG (1 << 0) + + PADD32[18]; + ioport32_t pm_wken; +#define USBHOST_PRM_PM_WKEN_EN_USBHOST_FLAG (1 << 0) + + ioport32_t pm_mpugrpsel; +#define USBHOST_PRM_PM_MPUGRPSEL_GRPSEL_USBHOST_FLAG (1 << 0) + + ioport32_t pm_iva2grpsel; +#define USBHOST_PRM_PM_IVA2GRPSEL_GRPSEL_USBHOST_FLAG (1 << 0) + + PADD32; + ioport32_t pm_wkst; +#define USBHOST_PRM_PM_WKST_ST_USBHOST_FLAG (1 << 0) + + PADD32[5]; + ioport32_t pm_wkdep; +#define USBHOST_PRM_PM_WKDEP_EN_WKUP_FLAG (1 << 4) +#define USBHOST_PRM_PM_WKDEP_EN_IVA2_FLAG (1 << 2) +#define USBHOST_PRM_PM_WKDEP_EN_MPU_FLAG (1 << 1) +#define USBHOST_PRM_PM_WKDEP_EN_CORE_FLAG (1 << 0) + + PADD32[5]; + ioport32_t pm_pwstctrl; +#define USBHOST_PRM_PM_PWSTCTRL_MEMONSTATE_MASK (0x3 << 16) +#define USBHOST_PRM_PM_PWSTCTRL_MEMONSTATE_ALWAYS_ON (0x3 << 16) +#define USBHOST_PRM_PM_PWSTCTRL_MEMRETSTATE_FLAG (1 << 8) +#define USBHOST_PRM_PM_PWSTCTRL_SAVEANDRESTORE_FLAG (1 << 4) +#define USBHOST_PRM_PM_PWSTCTRL_LOGICRESTATE_FLAG (1 << 2) +#define USBHOST_PRM_PM_PWSTCTRL_POWERSTATE_MASK (0x3 << 0) +#define USBHOST_PRM_PM_PWSTCTRL_POWERSTATE_OFF (0x0 << 0) +#define USBHOST_PRM_PM_PWSTCTRL_POWERSTATE_RETENTION (0x1 << 0) +#define USBHOST_PRM_PM_PWSTCTRL_POWERSTATE_ON (0x3 << 0) + + const ioport32_t pm_pwstst; +#define USBHOST_PRM_PM_PWSTST_INTRANSITION_FLAG (1 << 20) +#define USBHOST_PRM_PM_PWSTST_POWERSTATEST_MASK (0x3 << 0) +#define USBHOST_PRM_PM_PWSTST_POWERSTATEST_OFF (0x0 << 0) +#define USBHOST_PRM_PM_PWSTST_POWERSTATEST_RETENTION (0x1 << 0) +#define USBHOST_PRM_PM_PWSTST_POWERSTATEST_INACTIVE (0x2 << 0) +#define USBHOST_PRM_PM_PWSTST_POWERSTATEST_ON (0x3 << 0) + + ioport32_t pm_prepwstst; +#define USBHOST_PRM_PM_PREPWSTST_LASTPOWERSTATEENTERED_MASK (0x3 << 0) +#define USBHOST_PRM_PM_PREPWSTST_LASTPOWERSTATEENTERED_OFF (0x0 << 0) +#define USBHOST_PRM_PM_PREPWSTST_LASTPOWERSTATEENTERED_RETENTION (0x1 << 0) +#define USBHOST_PRM_PM_PREPWSTST_LASTPOWERSTATEENTERED_INACTIVE (0x2 << 0) +#define USBHOST_PRM_PM_PREPWSTST_LASTPOWERSTATEENTERED_ON (0x3 << 0) + +} usbhost_prm_regs_t; + +#endif +/** + * @} + */ + Index: uspace/drv/infrastructure/rootamdm37x/rootamdm37x.c =================================================================== --- uspace/drv/infrastructure/rootamdm37x/rootamdm37x.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) +++ uspace/drv/infrastructure/rootamdm37x/rootamdm37x.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -0,0 +1,234 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @defgroup root_amdm37x TI AM/DM37x platform driver. + * @brief HelenOS TI AM/DM37x platform driver. + * @{ + */ + +/** @file + */ + +#define DEBUG_CM 0 + +#include +#include +#include +#include + +#include "amdm37x.h" + +#define NAME "rootamdm37x" + +typedef struct { + hw_resource_list_t hw_resources; +} rootamdm37x_fun_t; + +/* See amdm37x TRM page. 3316 for these values */ +#define OHCI_BASE_ADDRESS 0x48064400 +#define OHCI_SIZE 1024 +#define EHCI_BASE_ADDRESS 0x48064800 +#define EHCI_SIZE 1024 + +static hw_resource_t ohci_res[] = { + { + .type = MEM_RANGE, + .res.io_range = { + .address = OHCI_BASE_ADDRESS, + .size = OHCI_SIZE, + .endianness = LITTLE_ENDIAN + }, + }, + { + .type = INTERRUPT, + .res.interrupt = { .irq = 76 }, + }, +}; + +static hw_resource_t ehci_res[] = { + { + .type = MEM_RANGE, + /* See amdm37x TRM page. 3316 for these values */ + .res.io_range = { + .address = EHCI_BASE_ADDRESS, + .size = EHCI_SIZE, + .endianness = LITTLE_ENDIAN + }, + }, + { + .type = INTERRUPT, + .res.interrupt = { .irq = 77 }, + }, +}; + +static const rootamdm37x_fun_t ohci = { + .hw_resources = { + .resources = ohci_res, + .count = sizeof(ohci_res)/sizeof(ohci_res[0]), + } +}; + +static const rootamdm37x_fun_t ehci = { + .hw_resources = { + .resources = ehci_res, + .count = sizeof(ehci_res) / sizeof(ehci_res[0]), + } +}; + +static hw_resource_list_t *rootamdm37x_get_resources(ddf_fun_t *fnode); +static bool rootamdm37x_enable_interrupt(ddf_fun_t *fun); + +static hw_res_ops_t fun_hw_res_ops = { + .get_resource_list = &rootamdm37x_get_resources, + .enable_interrupt = &rootamdm37x_enable_interrupt, +}; + +static ddf_dev_ops_t rootamdm37x_fun_ops = { + .interfaces[HW_RES_DEV_IFACE] = &fun_hw_res_ops +}; + +static int rootamdm37x_add_fun(ddf_dev_t *dev, const char *name, + const char *str_match_id, const rootamdm37x_fun_t *fun) +{ + ddf_msg(LVL_DEBUG, "Adding new function '%s'.", name); + + /* Create new device function. */ + ddf_fun_t *fnode = ddf_fun_create(dev, fun_inner, name); + if (fnode == NULL) + return ENOMEM; + + /* Add match id */ + int ret = ddf_fun_add_match_id(fnode, str_match_id, 100); + if (ret != EOK) { + ddf_fun_destroy(fnode); + return ret; + } + + /* Alloc needed data */ + rootamdm37x_fun_t *rf = + ddf_fun_data_alloc(fnode, sizeof(rootamdm37x_fun_t)); + if (!rf) { + ddf_fun_destroy(fnode); + return ENOMEM; + } + *rf = *fun; + + /* Set provided operations to the device. */ + ddf_fun_set_ops(fnode, &rootamdm37x_fun_ops); + + /* Register function. */ + ret = ddf_fun_bind(fnode); + if (ret != EOK) { + ddf_msg(LVL_ERROR, "Failed binding function %s.", name); + ddf_fun_destroy(fnode); + return ret; + } + + return EOK; +} + +/** Add the root device. + * + * @param dev Device which is root of the whole device tree + * (both of HW and pseudo devices). + * + * @return Zero on success, negative error number otherwise. + * + */ +static int rootamdm37x_dev_add(ddf_dev_t *dev) +{ + assert(dev); + amdm37x_t *device = ddf_dev_data_alloc(dev, sizeof(amdm37x_t)); + if (!device) + return ENOMEM; + int ret = amdm37x_init(device, DEBUG_CM); + if (ret != EOK) { + ddf_msg(LVL_FATAL, "Failed to setup hw access!.\n"); + return ret; + } + + /* Set dplls to ON and automatic */ + amdm37x_setup_dpll_on_autoidle(device); + + /* Enable function and interface clocks */ + amdm37x_usb_clocks_set(device, true); + + /* Init TLL */ + ret = amdm37x_usb_tll_init(device); + if (ret != EOK) { + ddf_msg(LVL_FATAL, "Failed to init USB TLL!.\n"); + amdm37x_usb_clocks_set(device, false); + return ret; + } + + /* Register functions */ + if (rootamdm37x_add_fun(dev, "ohci", "usb/host=ohci", &ohci) != EOK) + ddf_msg(LVL_ERROR, "Failed to add OHCI function for " + "BeagleBoard-xM platform."); + if (rootamdm37x_add_fun(dev, "ehci", "usb/host=ehci", &ehci) != EOK) + ddf_msg(LVL_ERROR, "Failed to add EHCI function for " + "BeagleBoard-xM platform."); + + return EOK; +} + +/** The root device driver's standard operations. */ +static driver_ops_t rootamdm37x_ops = { + .dev_add = &rootamdm37x_dev_add +}; + +/** The root device driver structure. */ +static driver_t rootamdm37x_driver = { + .name = NAME, + .driver_ops = &rootamdm37x_ops +}; + +static hw_resource_list_t * rootamdm37x_get_resources(ddf_fun_t *fnode) +{ + rootamdm37x_fun_t *fun = ddf_fun_data_get(fnode); + assert(fun != NULL); + return &fun->hw_resources; +} + +static bool rootamdm37x_enable_interrupt(ddf_fun_t *fun) +{ + //TODO: Implement + return false; +} + +int main(int argc, char *argv[]) +{ + printf("%s: HelenOS AM/DM37x(OMAP37x) platform driver\n", NAME); + ddf_log_init(NAME); + return ddf_driver_main(&rootamdm37x_driver); +} + +/** + * @} + */ Index: uspace/drv/infrastructure/rootamdm37x/rootamdm37x.ma =================================================================== --- uspace/drv/infrastructure/rootamdm37x/rootamdm37x.ma (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) +++ uspace/drv/infrastructure/rootamdm37x/rootamdm37x.ma (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -0,0 +1,1 @@ +10 platform/beagleboardxm Index: uspace/drv/infrastructure/rootamdm37x/uhh.h =================================================================== --- uspace/drv/infrastructure/rootamdm37x/uhh.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) +++ uspace/drv/infrastructure/rootamdm37x/uhh.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup amdm37xdrvuhh + * @{ + */ +/** @file + * @brief UHH IO register structure. + */ +#ifndef AMDM37x_UHH_H +#define AMDM37x_UHH_H +#include +#include + +#define AMDM37x_UHH_BASE_ADDRESS 0x48064000 +#define AMDM37x_UHH_SIZE 1024 + +typedef struct { + const ioport32_t revision; +#define UHH_REVISION_MINOR_MASK 0x0f +#define UHH_REVISION_MAJOR_MASK 0xf0 + + PADD32[3]; + ioport32_t sysconfig; +#define UHH_SYSCONFIG_AUTOIDLE_FLAG (1 << 0) +#define UHH_SYSCONFIG_SOFTRESET_FLAG (1 << 1) +#define UHH_SYSCONFIG_ENWAKEUP_FLAG (1 << 2) +#define UHH_SYSCONFIG_SIDLE_MODE_MASK (0x3 << 3) +#define UHH_SYSCONFIG_SIDLE_MODE_FORCE (0x0 << 3) +#define UHH_SYSCONFIG_SIDLE_MODE_NO (0x1 << 3) +#define UHH_SYSCONFIG_SIDLE_MODE_SMART (0x2 << 3) +#define UHH_SYSCONFIG_CLOCKACTIVITY_FLAG (1 << 8) +#define UHH_SYSCONFIG_MIDLE_MODE_MASK (0x3 << 12) +#define UHH_SYSCONFIG_MIDLE_MODE_FORCE (0x0 << 12) +#define UHH_SYSCONFIG_MIDLE_MODE_NO (0x1 << 12) +#define UHH_SYSCONFIG_MIDLE_MODE_SMART (0x2 << 12) + + const ioport32_t sysstatus; +#define UHH_SYSSTATUS_RESETDONE_FLAG (1 << 0) +#define UHH_SYSSTATUS_OHCI_RESETDONE_FLAG (1 << 1) +#define UHH_SYSSTATUS_EHCI_RESETDONE_FLAG (1 << 2) + + PADD32[10]; + ioport32_t hostconfig; +#define UHH_HOSTCONFIG_P1_ULPI_BYPASS_FLAG (1 << 0) +#define UHH_HOSTCONFIG_AUTOPPD_ON_OVERCUR_EN_FLAG (1 << 1) +#define UHH_HOSTCONFIG_ENA_INCR4_FLAG (1 << 2) +#define UHH_HOSTCONFIG_ENA_INCR8_FLAG (1 << 3) +#define UHH_HOSTCONFIG_ENA_INCR16_FLA (1 << 4) +#define UHH_HOSTCONFIG_ENA_INCR_ALIGN_FLAG (1 << 5) +#define UHH_HOSTCONFIG_P1_CONNECT_STATUS_FLAG (1 << 8) +#define UHH_HOSTCONFIG_P2_CONNECT_STATUS_FLAG (1 << 9) +#define UHH_HOSTCONFIG_P3_CONNECT_STATUS_FLAG (1 << 10) +#define UHH_HOSTCONFIG_P2_ULPI_BYPASS_FLAG (1 << 11) +#define UHH_HOSTCONFIG_P3_ULPI_BYPASS_FLAG (1 << 12) + + ioport32_t debug_csr; +#define UHH_DEBUG_CSR_EHCI_FLADJ_MASK (0x3f << 0) +#define UHH_DEBUG_CSR_EHCI_FLADJ(x) ((x) & 0x3f) +#define UHH_DEBUG_CSR_EHCI_SIMULATION_MODE_FLAG (1 << 6) +#define UHH_DEBUG_CSR_OHCI_CNTSEL_FLAG (1 << 7) +#define UHH_DEBUG_CSR_OHCI_GLOBAL_sUSPEND_FLAG (1 << 16) +#define UHH_DEBUG_CSR_OHCI_CCS1_FLAG (1 << 17) +#define UHH_DEBUG_CSR_OHCI_CCS2_FLAG (1 << 18) +#define UHH_DEBUG_CSR_OHCI_CCS3_FLAG (1 << 19) + +} uhh_regs_t; + +#endif +/** + * @} + */ Index: uspace/drv/infrastructure/rootamdm37x/usbtll.h =================================================================== --- uspace/drv/infrastructure/rootamdm37x/usbtll.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) +++ uspace/drv/infrastructure/rootamdm37x/usbtll.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup amdm37xdrvusbtll + * @{ + */ +/** @file + * @brief USBTLL IO register structure. + */ +#ifndef AMDM37x_USBTLL_H +#define AMDM37x_USBTLL_H +#include +#include + +#define AMDM37x_USBTLL_BASE_ADDRESS 0x48062000 +#define AMDM37x_USBTLL_SIZE 4096 + +typedef struct { + const ioport32_t revision; +#define TLL_REVISION_MINOR_MASK 0x0f +#define TLL_REVISION_MAJOR_MASK 0xf0 + + PADD32[3]; + ioport32_t sysconfig; +#define TLL_SYSCONFIG_AUTOIDLE_FLAG (1 << 0) +#define TLL_SYSCONFIG_SOFTRESET_FLAG (1 << 1) +#define TLL_SYSCONFIG_ENWAKEUP_FLAG (1 << 2) +#define TLL_SYSCONFIG_SIDLE_MODE_MASK (0x3 << 3) +#define TLL_SYSCONFIG_SIDLE_MODE_FORCE (0x0 << 3) +#define TLL_SYSCONFIG_SIDLE_MODE_NO (0x1 << 3) +#define TLL_SYSCONFIG_SIDLE_MODE_SMART (0x2 << 3) +#define TLL_SYSCONFIG_CLOCKACTIVITY_FLAG (1 << 8) + + const ioport32_t sysstatus; +#define TLL_SYSSTATUS_RESET_DONE_FLAG (1 << 0) + + const ioport32_t irqstatus; +#define TLL_IRQSTATUS_FCLK_START_FLAG (1 << 0) +#define TLL_IRQSTATUS_FCLK_END_FLAG (1 << 1) +#define TLL_IRQSTATUS_ACCESS_ERROR_FLAG (1 << 2) + + ioport32_t irqenable; +#define TLL_IRQSTATUS_FCLK_START_EN_FLAG (1 << 0) +#define TLL_IRQSTATUS_FCLK_END_EN_FLAG (1 << 1) +#define TLL_IRQSTATUS_ACCESS_ERROR_EN_FLAG (1 << 2) + + PADD32[4]; + ioport32_t shared_conf; +#define TLL_SHARED_CONF_FCLK_IS_ON_FLAG (1 << 0) +#define TLL_SHARED_CONF_FCLK_REQ_FLAG (1 << 1) +#define TLL_SHARED_CONF_USB_DIVRATIO_MASK (0x7 << 2) +#define TLL_SHARED_CONF_USB_DIVRATIO(x) (((x) & 0x7) << 2) +#define TLL_SHARED_CONF_USB_180D_SDR_EN_FLAG (1 << 5) +#define TLL_SHARED_CONF_USB_90D_DDR_EN_FLAG (1 << 6) + + PADD32[3]; + ioport32_t channel_conf[3]; +#define TLL_CHANNEL_CONF_CHANEN_FLAG (1 << 0) +#define TLL_CHANNEL_CONF_CHANMODE_MASK (0x3 << 1) +#define TLL_CHANNEL_CONF_CHANMODE_UTMI_ULPI_MODE (0x0 << 1) +#define TLL_CHANNEL_CONF_CHANMODE_UTMI_SERIAL_MODE (0x1 << 1) +#define TLL_CHANNEL_CONF_CHANMODE_UTMI_TRANS_MODE (0x2 << 1) +#define TLL_CHANNEL_CONF_CHANMODE_NO_MODE (0x3 << 1) +#define TLL_CHANNEL_CONF_UTMIISADEV_FLAG (1 << 3) +#define TLL_CHANNEL_CONF_TLLATTACH_FLAG (1 << 4) +#define TLL_CHANNEL_CONF_TLLCONNECT_FLAG (1 << 5) +#define TLL_CHANNEL_CONF_TLLFULLSPEED_FLAG (1 << 6) +#define TLL_CHANNEL_CONF_ULPIOUTCLKMODE_FLAG (1 << 7) +#define TLL_CHANNEL_CONF_ULPIDDRMODE_FLAG (1 << 8) +#define TLL_CHANNEL_CONF_UTMIAUTOIDLE_FLAG (1 << 9) +#define TLL_CHANNEL_CONF_ULPIAUTOIDLE_FLAG (1 << 10) +#define TLL_CHANNEL_CONF_ULPINOBITSTUFF_FLAG (1 << 11) +#define TLL_CHANNEL_CONF_CHRGVBUS_FLAG (1 << 15) +#define TLL_CHANNEL_CONF_DRVVBUS_FLAG (1 << 16) +#define TLL_CHANNEL_CONF_TESTEN_FLAG (1 << 17) +#define TLL_CHANNEL_CONF_TESTTXEN_FLAG (1 << 18) +#define TLL_CHANNEL_CONF_TESTTXDAT_FLAG (1 << 19) +#define TLL_CHANNEL_CONF_TESTTXSE0_FLAG (1 << 20) +#define TLL_CHANNEL_CONF_FSLSMODE_MASK (0xf << 24) +#define TLL_CHANNEL_CONF_FSLSMODE_6PIN_UNI_PHY_TX_DATSE0 (0x0 << 24) +#define TLL_CHANNEL_CONF_FSLSMODE_6PIN_UNI_PHY_TX_DPDM (0x1 << 24) +#define TLL_CHANNEL_CONF_FSLSMODE_3PIN_BIDI_PHY (0x2 << 24) +#define TLL_CHANNEL_CONF_FSLSMODE_4PIN_BIDI_PHY (0x3 << 24) +#define TLL_CHANNEL_CONF_FSLSMODE_6PIN_UNI_TLL_TX_DATSE0 (0x4 << 24) +#define TLL_CHANNEL_CONF_FSLSMODE_6PIN_UNI_TLL_TX_DPDM (0x5 << 24) +#define TLL_CHANNEL_CONF_FSLSMODE_3PIN_BIDI_TLL (0x6 << 24) +#define TLL_CHANNEL_CONF_FSLSMODE_4PIN_BIDI_TLL (0x7 << 24) +#define TLL_CHANNEL_CONF_FSLSMODE_2PIN_BIDI_TLL_DATSE0 (0xa << 24) +#define TLL_CHANNEL_CONF_FSLSMODE_2PIN_BIDI_TLL_DPDM (0xb << 24) + +#define TLL_CHANNEL_CONF_FSLSLINESTATE_MASK (0x3 << 28) +#define TLL_CHANNEL_CONF_FSLSLINESTATE_SE0 (0x0 << 28) +#define TLL_CHANNEL_CONF_FSLSLINESTATE_FS_J (0x1 << 28) +#define TLL_CHANNEL_CONF_FSLSLINESTATE_FS_K (0x2 << 28) +#define TLL_CHANNEL_CONF_FSLSLINESTATE_SE1 (0x3 << 28) + + /* The rest are 8bit ULPI registers */ +} tll_regs_t; + +#endif +/** + * @} + */ + Index: uspace/drv/nic/e1k/e1k.c =================================================================== --- uspace/drv/nic/e1k/e1k.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ uspace/drv/nic/e1k/e1k.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -45,5 +45,5 @@ #include #include -#include +#include #include #include Index: uspace/drv/nic/ne2k/dp8390.c =================================================================== --- uspace/drv/nic/ne2k/dp8390.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ uspace/drv/nic/ne2k/dp8390.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -58,5 +58,5 @@ #include #include -#include +#include #include "dp8390.h" Index: uspace/drv/nic/rtl8139/defs.h =================================================================== --- uspace/drv/nic/rtl8139/defs.h (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ uspace/drv/nic/rtl8139/defs.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -37,5 +37,5 @@ #include -#include +#include /** Size of RTL8139 registers address space */ Index: uspace/drv/nic/rtl8139/driver.c =================================================================== --- uspace/drv/nic/rtl8139/driver.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ uspace/drv/nic/rtl8139/driver.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -34,5 +34,4 @@ #include #include -#include #include Index: uspace/drv/time/cmos-rtc/cmos-rtc.c =================================================================== --- uspace/drv/time/cmos-rtc/cmos-rtc.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ uspace/drv/time/cmos-rtc/cmos-rtc.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -40,5 +40,4 @@ #include #include -#include #include #include Index: uspace/lib/c/Makefile =================================================================== --- uspace/lib/c/Makefile (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ uspace/lib/c/Makefile (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -140,9 +140,11 @@ generic/net/socket_client.c \ generic/net/socket_parse.c \ + generic/stack.c \ generic/stacktrace.c \ generic/arg_parse.c \ generic/sort.c \ generic/stats.c \ - generic/assert.c + generic/assert.c \ + generic/pio_trace.c ifeq ($(CONFIG_RTLD),y) Index: uspace/lib/c/arch/abs32le/include/ddi.h =================================================================== --- uspace/lib/c/arch/abs32le/include/ddi.h (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ uspace/lib/c/arch/abs32le/include/ddi.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -36,30 +36,30 @@ #include -static inline void pio_write_8(ioport8_t *port, uint8_t v) +static inline void arch_pio_write_8(ioport8_t *port, uint8_t v) { *port = v; } -static inline void pio_write_16(ioport16_t *port, uint16_t v) +static inline void arch_pio_write_16(ioport16_t *port, uint16_t v) { *port = v; } -static inline void pio_write_32(ioport32_t *port, uint32_t v) +static inline void arch_pio_write_32(ioport32_t *port, uint32_t v) { *port = v; } -static inline uint8_t pio_read_8(ioport8_t *port) +static inline uint8_t arch_pio_read_8(const ioport8_t *port) { return *port; } -static inline uint16_t pio_read_16(ioport16_t *port) +static inline uint16_t arch_pio_read_16(const ioport16_t *port) { return *port; } -static inline uint32_t pio_read_32(ioport32_t *port) +static inline uint32_t arch_pio_read_32(const ioport32_t *port) { return *port; Index: uspace/lib/c/arch/arm32/Makefile.common =================================================================== --- uspace/lib/c/arch/arm32/Makefile.common (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ uspace/lib/c/arch/arm32/Makefile.common (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -29,5 +29,5 @@ BASE_LIBS += $(LIBSOFTFLOAT_PREFIX)/libsoftfloat.a -GCC_CFLAGS += -ffixed-r9 -mtp=soft -fno-omit-frame-pointer -march=armv4 -mapcs-frame +GCC_CFLAGS += -ffixed-r9 -mtp=soft -fno-omit-frame-pointer -mapcs-frame -march=$(subst _,-,$(PROCESSOR)) ENDIANESS = LE Index: uspace/lib/c/arch/arm32/include/ddi.h =================================================================== --- uspace/lib/c/arch/arm32/include/ddi.h (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ uspace/lib/c/arch/arm32/include/ddi.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -37,30 +37,30 @@ #include -static inline void pio_write_8(ioport8_t *port, uint8_t v) +static inline void arch_pio_write_8(ioport8_t *port, uint8_t v) { *port = v; } -static inline void pio_write_16(ioport16_t *port, uint16_t v) +static inline void arch_pio_write_16(ioport16_t *port, uint16_t v) { *port = v; } -static inline void pio_write_32(ioport32_t *port, uint32_t v) +static inline void arch_pio_write_32(ioport32_t *port, uint32_t v) { *port = v; } -static inline uint8_t pio_read_8(ioport8_t *port) +static inline uint8_t arch_pio_read_8(const ioport8_t *port) { return *port; } -static inline uint16_t pio_read_16(ioport16_t *port) +static inline uint16_t arch_pio_read_16(const ioport16_t *port) { return *port; } -static inline uint32_t pio_read_32(ioport32_t *port) +static inline uint32_t arch_pio_read_32(const ioport32_t *port) { return *port; Index: uspace/lib/c/arch/ia32/include/ddi.h =================================================================== --- uspace/lib/c/arch/ia32/include/ddi.h (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ uspace/lib/c/arch/ia32/include/ddi.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -39,5 +39,5 @@ #define IO_SPACE_BOUNDARY ((void *) (64 * 1024)) -static inline uint8_t pio_read_8(ioport8_t *port) +static inline uint8_t arch_pio_read_8(const ioport8_t *port) { if (port < (ioport8_t *) IO_SPACE_BOUNDARY) { @@ -55,5 +55,5 @@ } -static inline uint16_t pio_read_16(ioport16_t *port) +static inline uint16_t arch_pio_read_16(const ioport16_t *port) { if (port < (ioport16_t *) IO_SPACE_BOUNDARY) { @@ -71,5 +71,5 @@ } -static inline uint32_t pio_read_32(ioport32_t *port) +static inline uint32_t arch_pio_read_32(const ioport32_t *port) { if (port < (ioport32_t *) IO_SPACE_BOUNDARY) { @@ -87,5 +87,5 @@ } -static inline void pio_write_8(ioport8_t *port, uint8_t val) +static inline void arch_pio_write_8(ioport8_t *port, uint8_t val) { if (port < (ioport8_t *) IO_SPACE_BOUNDARY) { @@ -98,5 +98,5 @@ } -static inline void pio_write_16(ioport16_t *port, uint16_t val) +static inline void arch_pio_write_16(ioport16_t *port, uint16_t val) { if (port < (ioport16_t *) IO_SPACE_BOUNDARY) { @@ -109,5 +109,5 @@ } -static inline void pio_write_32(ioport32_t *port, uint32_t val) +static inline void arch_pio_write_32(ioport32_t *port, uint32_t val) { if (port < (ioport32_t *) IO_SPACE_BOUNDARY) { Index: uspace/lib/c/arch/ia64/include/ddi.h =================================================================== --- uspace/lib/c/arch/ia64/include/ddi.h (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ uspace/lib/c/arch/ia64/include/ddi.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -50,5 +50,5 @@ (ia64_iospace_address = get_ia64_iospace_address())) -static inline void pio_write_8(ioport8_t *port, uint8_t v) +static inline void arch_pio_write_8(ioport8_t *port, uint8_t v) { if (port < (ioport8_t *) IO_SPACE_BOUNDARY) { @@ -65,5 +65,5 @@ } -static inline void pio_write_16(ioport16_t *port, uint16_t v) +static inline void arch_pio_write_16(ioport16_t *port, uint16_t v) { if (port < (ioport16_t *) IO_SPACE_BOUNDARY) { @@ -80,5 +80,5 @@ } -static inline void pio_write_32(ioport32_t *port, uint32_t v) +static inline void arch_pio_write_32(ioport32_t *port, uint32_t v) { if (port < (ioport32_t *) IO_SPACE_BOUNDARY) { @@ -95,5 +95,5 @@ } -static inline uint8_t pio_read_8(ioport8_t *port) +static inline uint8_t arch_pio_read_8(const ioport8_t *port) { uint8_t v; @@ -115,5 +115,5 @@ } -static inline uint16_t pio_read_16(ioport16_t *port) +static inline uint16_t arch_pio_read_16(const ioport16_t *port) { uint16_t v; @@ -135,5 +135,5 @@ } -static inline uint32_t pio_read_32(ioport32_t *port) +static inline uint32_t arch_pio_read_32(const ioport32_t *port) { uint32_t v; Index: uspace/lib/c/arch/ia64/src/ddi.c =================================================================== --- uspace/lib/c/arch/ia64/src/ddi.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ uspace/lib/c/arch/ia64/src/ddi.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -1,2 +1,29 @@ +/* + * Copyright (c) 2006 Martin Decky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ #include #include @@ -12,3 +39,2 @@ return addr; } - Index: uspace/lib/c/arch/mips32/include/ddi.h =================================================================== --- uspace/lib/c/arch/mips32/include/ddi.h (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ uspace/lib/c/arch/mips32/include/ddi.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -37,30 +37,30 @@ #include -static inline void pio_write_8(ioport8_t *port, uint8_t v) +static inline void arch_pio_write_8(ioport8_t *port, uint8_t v) { *port = v; } -static inline void pio_write_16(ioport16_t *port, uint16_t v) +static inline void arch_pio_write_16(ioport16_t *port, uint16_t v) { *port = v; } -static inline void pio_write_32(ioport32_t *port, uint32_t v) +static inline void arch_pio_write_32(ioport32_t *port, uint32_t v) { *port = v; } -static inline uint8_t pio_read_8(ioport8_t *port) +static inline uint8_t arch_pio_read_8(const ioport8_t *port) { return *port; } -static inline uint16_t pio_read_16(ioport16_t *port) +static inline uint16_t arch_pio_read_16(const ioport16_t *port) { return *port; } -static inline uint32_t pio_read_32(ioport32_t *port) +static inline uint32_t arch_pio_read_32(const ioport32_t *port) { return *port; Index: uspace/lib/c/arch/mips64/include/ddi.h =================================================================== --- uspace/lib/c/arch/mips64/include/ddi.h (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ uspace/lib/c/arch/mips64/include/ddi.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -37,30 +37,30 @@ #include -static inline void pio_write_8(ioport8_t *port, uint8_t v) +static inline void arch_pio_write_8(ioport8_t *port, uint8_t v) { *port = v; } -static inline void pio_write_16(ioport16_t *port, uint16_t v) +static inline void arch_pio_write_16(ioport16_t *port, uint16_t v) { *port = v; } -static inline void pio_write_32(ioport32_t *port, uint32_t v) +static inline void arch_pio_write_32(ioport32_t *port, uint32_t v) { *port = v; } -static inline uint8_t pio_read_8(ioport8_t *port) +static inline uint8_t arch_pio_read_8(const ioport8_t *port) { return *port; } -static inline uint16_t pio_read_16(ioport16_t *port) +static inline uint16_t arch_pio_read_16(const ioport16_t *port) { return *port; } -static inline uint32_t pio_read_32(ioport32_t *port) +static inline uint32_t arch_pio_read_32(const ioport32_t *port) { return *port; Index: uspace/lib/c/arch/ppc32/include/ddi.h =================================================================== --- uspace/lib/c/arch/ppc32/include/ddi.h (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ uspace/lib/c/arch/ppc32/include/ddi.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -37,30 +37,30 @@ #include -static inline void pio_write_8(ioport8_t *port, uint8_t v) +static inline void arch_pio_write_8(ioport8_t *port, uint8_t v) { *port = v; } -static inline void pio_write_16(ioport16_t *port, uint16_t v) +static inline void arch_pio_write_16(ioport16_t *port, uint16_t v) { *port = v; } -static inline void pio_write_32(ioport32_t *port, uint32_t v) +static inline void arch_pio_write_32(ioport32_t *port, uint32_t v) { *port = v; } -static inline uint8_t pio_read_8(ioport8_t *port) +static inline uint8_t arch_pio_read_8(const ioport8_t *port) { return *port; } -static inline uint16_t pio_read_16(ioport16_t *port) +static inline uint16_t arch_pio_read_16(const ioport16_t *port) { return *port; } -static inline uint32_t pio_read_32(ioport32_t *port) +static inline uint32_t arch_pio_read_32(const ioport32_t *port) { return *port; Index: uspace/lib/c/arch/sparc64/include/ddi.h =================================================================== --- uspace/lib/c/arch/sparc64/include/ddi.h (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ uspace/lib/c/arch/sparc64/include/ddi.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -45,5 +45,5 @@ } -static inline void pio_write_8(ioport8_t *port, uint8_t v) +static inline void arch_pio_write_8(ioport8_t *port, uint8_t v) { *port = v; @@ -51,5 +51,5 @@ } -static inline void pio_write_16(ioport16_t *port, uint16_t v) +static inline void arch_pio_write_16(ioport16_t *port, uint16_t v) { *port = v; @@ -57,5 +57,5 @@ } -static inline void pio_write_32(ioport32_t *port, uint32_t v) +static inline void arch_pio_write_32(ioport32_t *port, uint32_t v) { *port = v; @@ -63,5 +63,5 @@ } -static inline uint8_t pio_read_8(ioport8_t *port) +static inline uint8_t arch_pio_read_8(const ioport8_t *port) { uint8_t rv; @@ -73,5 +73,5 @@ } -static inline uint16_t pio_read_16(ioport16_t *port) +static inline uint16_t arch_pio_read_16(const ioport16_t *port) { uint16_t rv; @@ -83,5 +83,5 @@ } -static inline uint32_t pio_read_32(ioport32_t *port) +static inline uint32_t arch_pio_read_32(const ioport32_t *port) { uint32_t rv; Index: uspace/lib/c/generic/ddi.c =================================================================== --- uspace/lib/c/generic/ddi.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ uspace/lib/c/generic/ddi.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -34,5 +34,7 @@ #include +#include #include +#include #include #include @@ -47,4 +49,5 @@ #include "private/libc.h" + /** Return unique device number. * @@ -120,11 +123,11 @@ * */ -int iospace_enable(task_id_t id, void *ioaddr, unsigned long size) -{ - ddi_ioarg_t arg; - - arg.task_id = id; - arg.ioaddr = ioaddr; - arg.size = size; +static int iospace_enable(task_id_t id, void *ioaddr, size_t size) +{ + const ddi_ioarg_t arg = { + .task_id = id, + .ioaddr = ioaddr, + .size = size + }; return __SYSCALL1(SYS_IOSPACE_ENABLE, (sysarg_t) &arg); @@ -136,5 +139,5 @@ * @param size Size of the I/O region. * @param virt Virtual address for application's - * PIO operations. + * PIO operations. Can be NULL for PMIO. * * @return EOK on success. @@ -146,9 +149,14 @@ #ifdef IO_SPACE_BOUNDARY if (pio_addr < IO_SPACE_BOUNDARY) { - *virt = pio_addr; + if (virt) + *virt = pio_addr; return iospace_enable(task_get_id(), pio_addr, size); } +#else + (void) iospace_enable; #endif - + if (!virt) + return EINVAL; + void *phys_frame = (void *) ALIGN_DOWN((uintptr_t) pio_addr, PAGE_SIZE); @@ -166,4 +174,43 @@ } +void pio_write_8(ioport8_t *reg, uint8_t val) +{ + pio_trace_log(reg, val, true); + arch_pio_write_8(reg, val); +} + +void pio_write_16(ioport16_t *reg, uint16_t val) +{ + pio_trace_log(reg, val, true); + arch_pio_write_16(reg, val); +} + +void pio_write_32(ioport32_t *reg, uint32_t val) +{ + pio_trace_log(reg, val, true); + arch_pio_write_32(reg, val); +} + +uint8_t pio_read_8(const ioport8_t *reg) +{ + const uint8_t val = arch_pio_read_8(reg); + pio_trace_log(reg, val, false); + return val; +} + +uint16_t pio_read_16(const ioport16_t *reg) +{ + const uint16_t val = arch_pio_read_16(reg); + pio_trace_log(reg, val, false); + return val; +} + +uint32_t pio_read_32(const ioport32_t *reg) +{ + const uint32_t val = arch_pio_read_32(reg); + pio_trace_log(reg, val, false); + return val; +} + /** Register IRQ notification. * Index: uspace/lib/c/generic/fibril.c =================================================================== --- uspace/lib/c/generic/fibril.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ uspace/lib/c/generic/fibril.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -37,6 +37,9 @@ #include #include +#include #include #include +#include +#include #include #include @@ -46,8 +49,4 @@ #include #include - -#ifndef FIBRIL_INITIAL_STACK_PAGES_NO - #define FIBRIL_INITIAL_STACK_PAGES_NO 1 -#endif /** @@ -195,5 +194,5 @@ * stack member filled. */ - free(stack); + as_area_destroy(stack); } fibril_teardown(srcf->clean_after_me); @@ -269,7 +268,9 @@ return 0; - fibril->stack = - (char *) malloc(FIBRIL_INITIAL_STACK_PAGES_NO * getpagesize()); - if (!fibril->stack) { + size_t stack_size = stack_size_get(); + fibril->stack = as_area_create((void *) -1, stack_size, + AS_AREA_READ | AS_AREA_WRITE | AS_AREA_CACHEABLE | AS_AREA_GUARD | + AS_AREA_LATE_RESERVE); + if (fibril->stack == (void *) -1) { fibril_teardown(fibril); return 0; @@ -281,5 +282,5 @@ context_save(&fibril->ctx); context_set(&fibril->ctx, FADDR(fibril_main), fibril->stack, - FIBRIL_INITIAL_STACK_PAGES_NO * getpagesize(), fibril->tcb); + stack_size, fibril->tcb); return (fid_t) fibril; @@ -298,5 +299,5 @@ fibril_t *fibril = (fibril_t *) fid; - free(fibril->stack); + as_area_destroy(fibril->stack); fibril_teardown(fibril); } Index: uspace/lib/c/generic/malloc.c =================================================================== --- uspace/lib/c/generic/malloc.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ uspace/lib/c/generic/malloc.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -289,5 +289,5 @@ size_t asize = ALIGN_UP(size, PAGE_SIZE); void *astart = as_area_create(AS_AREA_ANY, asize, - AS_AREA_WRITE | AS_AREA_READ); + AS_AREA_WRITE | AS_AREA_READ | AS_AREA_CACHEABLE); if (astart == AS_MAP_FAILED) return false; Index: uspace/lib/c/generic/pio_trace.c =================================================================== --- uspace/lib/c/generic/pio_trace.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) +++ uspace/lib/c/generic/pio_trace.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -0,0 +1,145 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup libc + * @{ + */ +/** @file + */ + +#include +#include +#include +#include +#include +#include +#include + + +typedef struct { + link_t link; + volatile void *base; + size_t size; + void *data; + trace_fnc log; +} region_t; + +static inline region_t * region_instance(link_t *l) +{ + return list_get_instance(l, region_t, link); +} + +static inline region_t * region_create(volatile void* base, size_t size, + trace_fnc log, void* data) +{ + region_t *new_reg = malloc(sizeof(region_t)); + if (new_reg) { + link_initialize(&new_reg->link); + new_reg->base = base; + new_reg->data = data; + new_reg->size = size; + new_reg->log = log; + } + return new_reg; +} + +static inline void region_destroy(region_t *r) +{ + free(r); +} + +typedef struct { + list_t list; + fibril_rwlock_t guard; +} pio_regions_t; + +static pio_regions_t * get_regions(void) +{ + static pio_regions_t regions = { + .list = { + .head = { ®ions.list.head, ®ions.list.head }, + }, + .guard = FIBRIL_RWLOCK_INITIALIZER(regions.guard), + }; + return ®ions; +} + + +void pio_trace_log(const volatile void *r, uint32_t val, bool write) +{ + pio_regions_t *regions = get_regions(); + fibril_rwlock_read_lock(®ions->guard); + list_foreach(regions->list, it) { + assert(it); + region_t *reg = region_instance(it); + assert(reg); + if ((r >= reg->base) && (r < reg->base + reg->size)) { + if (reg->log) + reg->log(r, val, reg->base, + reg->size, reg->data, write); + break; + } + } + fibril_rwlock_read_unlock(®ions->guard); +} + +int pio_trace_enable(void *base, size_t size, trace_fnc log, void *data) +{ + pio_regions_t *regions = get_regions(); + assert(regions); + + region_t *region = region_create(base, size, log, data); + if (!region) + return ENOMEM; + + fibril_rwlock_write_lock(®ions->guard); + list_append(®ion->link, ®ions->list); + fibril_rwlock_write_unlock(®ions->guard); + return EOK; +} + +void pio_trace_disable(void *r) +{ + pio_regions_t *regions = get_regions(); + assert(regions); + + fibril_rwlock_write_lock(®ions->guard); + list_foreach_safe(regions->list, it, next) { + assert(it); + region_t *reg = region_instance(it); + assert(reg); + if (r >= reg->base && (r < reg->base + reg->size)) { + list_remove(®->link); + region_destroy(reg); + } + } + fibril_rwlock_write_unlock(®ions->guard); +} + +/** @} + */ Index: uspace/lib/c/generic/stack.c =================================================================== --- uspace/lib/c/generic/stack.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) +++ uspace/lib/c/generic/stack.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2012 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup libc + * @{ + */ +/** @file + */ + +#include +#include + +size_t stack_size_get(void) +{ + static sysarg_t stack_size = 0; + + if (!stack_size) + sysinfo_get_value("default.stack_size", &stack_size); + + return (size_t) stack_size; +} + +/** @} + */ Index: uspace/lib/c/generic/stdlib.c =================================================================== --- uspace/lib/c/generic/stdlib.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ uspace/lib/c/generic/stdlib.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -39,10 +39,10 @@ long int random(void) { - return glbl_seed = ((1366*glbl_seed + 150889) % RAND_MAX); + return glbl_seed = ((1366 * glbl_seed + 150889) % RAND_MAX); } void srandom(unsigned int seed) { - glbl_seed = seed; + glbl_seed = seed % RAND_MAX; } Index: uspace/lib/c/generic/thread.c =================================================================== --- uspace/lib/c/generic/thread.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ uspace/lib/c/generic/thread.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -39,4 +39,5 @@ #include #include +#include #include #include @@ -44,8 +45,4 @@ #include #include "private/thread.h" - -#ifndef THREAD_INITIAL_STACK_PAGES - #define THREAD_INITIAL_STACK_PAGES 2 -#endif /** Main thread function. @@ -101,7 +98,8 @@ return ENOMEM; - size_t stack_size = getpagesize() * THREAD_INITIAL_STACK_PAGES; + size_t stack_size = stack_size_get(); void *stack = as_area_create(AS_AREA_ANY, stack_size, - AS_AREA_READ | AS_AREA_WRITE | AS_AREA_CACHEABLE); + AS_AREA_READ | AS_AREA_WRITE | AS_AREA_CACHEABLE | AS_AREA_GUARD | + AS_AREA_LATE_RESERVE); if (stack == AS_MAP_FAILED) { free(uarg); Index: uspace/lib/c/include/ddi.h =================================================================== --- uspace/lib/c/include/ddi.h (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ uspace/lib/c/include/ddi.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -36,5 +36,7 @@ #define LIBC_DDI_H_ +#include #include +#include #include #include @@ -50,6 +52,73 @@ extern int dmamem_unmap_anonymous(void *); -extern int iospace_enable(task_id_t, void *, unsigned long); extern int pio_enable(void *, size_t, void **); + +typedef void (*trace_fnc)(const volatile void *place, uint32_t val, + volatile void* base, size_t size, void *data, bool write); + +extern int pio_trace_enable(void *, size_t, trace_fnc, void *); +extern void pio_trace_log(const volatile void *, uint32_t val, bool write); +extern void pio_trace_disable(void *); + +extern void pio_write_8(ioport8_t *, uint8_t); +extern void pio_write_16(ioport16_t *, uint16_t); +extern void pio_write_32(ioport32_t *, uint32_t); + +extern uint8_t pio_read_8(const ioport8_t *); +extern uint16_t pio_read_16(const ioport16_t *); +extern uint32_t pio_read_32(const ioport32_t *); + +static inline uint8_t pio_change_8( + ioport8_t *reg, uint8_t val, uint8_t mask, useconds_t delay) +{ + uint8_t v = pio_read_8(reg); + udelay(delay); + pio_write_8(reg, (v & ~mask) | val); + return v; +} + +static inline uint16_t pio_change_16( + ioport16_t *reg, uint16_t val, uint16_t mask, useconds_t delay) +{ + uint16_t v = pio_read_16(reg); + udelay(delay); + pio_write_16(reg, (v & ~mask) | val); + return v; +} + +static inline uint32_t pio_change_32( + ioport32_t *reg, uint32_t val, uint32_t mask, useconds_t delay) +{ + uint32_t v = pio_read_32(reg); + udelay(delay); + pio_write_32(reg, (v & ~mask) | val); + return v; +} + +static inline uint8_t pio_set_8(ioport8_t *r, uint8_t v, useconds_t d) +{ + return pio_change_8(r, v, 0, d); +} +static inline uint16_t pio_set_16(ioport16_t *r, uint16_t v, useconds_t d) +{ + return pio_change_16(r, v, 0, d); +} +static inline uint32_t pio_set_32(ioport32_t *r, uint32_t v, useconds_t d) +{ + return pio_change_32(r, v, 0, d); +} + +static inline uint8_t pio_clear_8(ioport8_t *r, uint8_t v, useconds_t d) +{ + return pio_change_8(r, 0, v, d); +} +static inline uint16_t pio_clear_16(ioport16_t *r, uint16_t v, useconds_t d) +{ + return pio_change_16(r, 0, v, d); +} +static inline uint32_t pio_clear_32(ioport32_t *r, uint32_t v, useconds_t d) +{ + return pio_change_32(r, 0, v, d); +} extern int irq_register(int, int, int, irq_code_t *); Index: uspace/lib/c/include/macros.h =================================================================== --- uspace/lib/c/include/macros.h (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ uspace/lib/c/include/macros.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -62,4 +62,10 @@ #endif +#define _paddname(line) PADD_ ## line ## __ +#define _padd(width, line) uint ## width ## _t _paddname(line) +#define PADD32 _padd(32, __LINE__) +#define PADD16 _padd(16, __LINE__) +#define PADD8 _padd(8, __LINE__) + /** @} */ Index: uspace/lib/c/include/stack.h =================================================================== --- uspace/lib/c/include/stack.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) +++ uspace/lib/c/include/stack.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2012 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup libc + * @{ + */ +/** @file + */ + +#ifndef LIBC_STACK_H_ +#define LIBC_STACK_H_ + +#include + +extern size_t stack_size_get(void); + +#endif + +/** @} + */ Index: uspace/lib/softfloat/common.c =================================================================== --- uspace/lib/softfloat/common.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ uspace/lib/softfloat/common.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -39,5 +39,5 @@ /* Table for fast leading zeroes counting. */ char zeroTable[256] = { - 8, 7, 7, 6, 6, 6, 6, 4, 4, 4, 4, 4, 4, 4, 4, \ + 8, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, \ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, \ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, \ @@ -307,16 +307,24 @@ /** * Round and normalize number expressed by exponent and fraction with - * first bit (equal to hidden bit) at 62nd bit. + * first bit (equal to hidden bit) at bit 62. * * @param exp Exponent part. - * @param fraction Fraction with hidden bit shifted to 62nd bit. + * @param fraction Fraction with hidden bit shifted to bit 62. */ void round_float64(int32_t *exp, uint64_t *fraction) { - /* rounding - if first bit after fraction is set then round up */ + /* + * Rounding - if first bit after fraction is set then round up. + */ + + /* + * Add 1 to the least significant bit of the fraction respecting the + * current shift to bit 62 and see if there will be a carry to bit 63. + */ (*fraction) += (0x1 << (64 - FLOAT64_FRACTION_SIZE - 3)); + /* See if there was a carry to bit 63. */ if ((*fraction) & - (FLOAT64_HIDDEN_BIT_MASK << (64 - FLOAT64_FRACTION_SIZE - 3))) { + (FLOAT64_HIDDEN_BIT_MASK << (64 - FLOAT64_FRACTION_SIZE - 1))) { /* rounding overflow */ ++(*exp); Index: uspace/lib/usbdev/include/usb/dev/request.h =================================================================== --- uspace/lib/usbdev/include/usb/dev/request.h (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ uspace/lib/usbdev/include/usb/dev/request.h (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -93,8 +93,8 @@ uint8_t request; /** Main parameter to the request. */ - union { + union __attribute__ ((packed)) { uint16_t value; /* FIXME: add #ifdefs according to host endianness */ - struct { + struct __attribute__ ((packed)) { uint8_t value_low; uint8_t value_high; @@ -108,4 +108,6 @@ uint16_t length; } __attribute__ ((packed)) usb_device_request_setup_packet_t; + +int assert[(sizeof(usb_device_request_setup_packet_t) == 8) ? 1: -1]; int usb_control_request_set(usb_pipe_t *, Index: uspace/srv/bd/ata_bd/ata_bd.c =================================================================== --- uspace/srv/bd/ata_bd/ata_bd.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ uspace/srv/bd/ata_bd/ata_bd.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -49,5 +49,4 @@ #include -#include #include #include Index: uspace/srv/bd/gxe_bd/gxe_bd.c =================================================================== --- uspace/srv/bd/gxe_bd/gxe_bd.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ uspace/srv/bd/gxe_bd/gxe_bd.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -37,5 +37,4 @@ #include -#include #include #include Index: uspace/srv/hid/input/port/pl050.c =================================================================== --- uspace/srv/hid/input/port/pl050.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ uspace/srv/hid/input/port/pl050.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -37,9 +37,7 @@ #include -#include #include #include #include -#include #include #include Index: uspace/srv/hid/output/port/ega.c =================================================================== --- uspace/srv/hid/output/port/ega.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ uspace/srv/hid/output/port/ega.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -36,5 +36,4 @@ #include #include -#include #include #include "../output.h" @@ -211,6 +210,5 @@ return rc; - rc = iospace_enable(task_get_id(), (void *) EGA_IO_BASE, - EGA_IO_SIZE); + rc = pio_enable((void*)EGA_IO_BASE, EGA_IO_SIZE, NULL); if (rc != EOK) return rc; Index: uspace/srv/hid/s3c24xx_ts/s3c24xx_ts.c =================================================================== --- uspace/srv/hid/s3c24xx_ts/s3c24xx_ts.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ uspace/srv/hid/s3c24xx_ts/s3c24xx_ts.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -38,5 +38,4 @@ #include -#include #include #include Index: uspace/srv/hw/char/s3c24xx_uart/s3c24xx_uart.c =================================================================== --- uspace/srv/hw/char/s3c24xx_uart/s3c24xx_uart.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ uspace/srv/hw/char/s3c24xx_uart/s3c24xx_uart.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -38,5 +38,4 @@ #include -#include #include #include Index: uspace/srv/hw/irc/i8259/i8259.c =================================================================== --- uspace/srv/hw/irc/i8259/i8259.c (revision 82edef2f5532d5ca29a1c05cbe6b80ccf84adbd2) +++ uspace/srv/hw/irc/i8259/i8259.c (revision e1c6d5dfb8468c498db7202bf029bc2e762edd18) @@ -42,5 +42,4 @@ #include #include -#include #include #include