Changes in / [17cc8f4f:e1a27be] in mainline


Ignore:
Files:
4 edited

Legend:

Unmodified
Added
Removed

  • boot/arch/arm32/include/mm.h

    r17cc8f4f re1a27be  
    4747/** Describe "section" page table entry (one-level paging with 1 MB sized pages). */
    4848#define PTE_DESCRIPTOR_SECTION  0x02
    49 /** Shift of memory address in section descriptor */
    50 #define PTE_SECTION_SHIFT  20
    5149
    5250/** Page table access rights: user - no access, kernel - read/write. */
    5351#define PTE_AP_USER_NO_KERNEL_RW  0x01
    54 
    55 /** Start of memory mapped I/O area for GTA02 */
    56 #define GTA02_IOMEM_START  0x48000000
    57 /** End of memory mapped I/O area for GTA02 */
    58 #define GTA02_IOMEM_END  0x60000000
    5952
    6053/* Page table level 0 entry - "section" format is used

  • boot/arch/arm32/src/asm.S

    r17cc8f4f re1a27be  
    6060        # before passing control to the copied code.
    6161        #
    62 
    63 #if defined(MACHINE_gta02)
    64 
    65 #define CP15_C1_IC              12
    66 #define CP15_C1_DC              2
    67 #define CP15_C7_SEG_SHIFT       5
    68 #define CP15_C7_SEG_SIZE        3
    69 #define CP15_C7_IDX_SHIFT       26
    70 
    71         # Disable I-cache and D-cache before the kernel is started.
    72         mrc     p15, 0, r4, c1, c0, 0
    73         bic     r4, r4, #(1 << CP15_C1_DC)
    74         bic     r4, r4, #(1 << CP15_C1_IC)
    75         mcr     p15, 0, r4, c1, c0, 0
    76 
    77         # Now clean D-cache to guarantee coherency between I-cache and D-cache.
    78 
    79         # D-cache clean and invalidate procedure.
    80         # See ARM920T TRM pages 2-17, 4-17.
    81 
    82         # Initialize segment
    83         mov     r4, #0
    84         # Initialize index
    85 1:      mov     r5, #0
    86 2:      orr     r6, r4, r5
    87         # Clean and invalidate a single line
    88         mcr     p15, 0, r6, c7, c10, 2
    89         # Increment index
    90         add     r5, r5, #(1 << CP15_C7_IDX_SHIFT)
    91         cmp     r5, #0
    92         bne     2b
    93         # Increment segment
    94         add     r4, #(1 << CP15_C7_SEG_SHIFT)
    95         tst     r4, #(1 << (CP15_C7_SEG_SHIFT + CP15_C7_SEG_SIZE))
    96         beq     1b
    97 #endif
    98 
    9962        mov pc, r0

  • boot/arch/arm32/src/mm.c

    r17cc8f4f re1a27be  
    3838#include <arch/mm.h>
    3939
    40 /** Check if caching can be enabled for a given memory section.
    41  *
    42  * Memory areas used for I/O are excluded from caching.
    43  * At the moment caching is enabled only on GTA02.
    44  *
    45  * @param section       The section number.
    46  *
    47  * @return      1 if the given section can be mapped as cacheable, 0 otherwise.
    48 */
    49 static inline int section_cacheable(pfn_t section)
    50 {
    51 #ifdef MACHINE_gta02
    52         unsigned long address = section << PTE_SECTION_SHIFT;
    53 
    54         if (address >= GTA02_IOMEM_START && address < GTA02_IOMEM_END)
    55                 return 0;
    56         else
    57                 return 1;
    58 #else
    59         return 0;
    60 #endif
    61 }
    62 
    6340/** Initialize "section" page table entry.
    6441 *
    … …  
    7855        pte->descriptor_type = PTE_DESCRIPTOR_SECTION;
    7956        pte->bufferable = 1;
    80         pte->cacheable = section_cacheable(frame);
     57        pte->cacheable = 0;
    8158        pte->xn = 0;
    8259        pte->domain = 0;
    … …  
    146123                "ldr r1, =0x00000005\n"
    147124#else
    148 #ifdef MACHINE_gta02
    149                 /* Mask to enable paging (bit 0),
    150                    D-cache (bit 2), I-cache (bit 12) */
    151                 "ldr r1, =0x00001005\n"
    152 #else
    153125                /* Mask to enable paging */
    154126                "ldr r1, =0x00000001\n"
    155 #endif
    156127#endif
    157128                "orr r0, r0, r1\n"

  • kernel/arch/arm32/src/ras.c

    r17cc8f4f re1a27be  
    6767void ras_check(unsigned int n, istate_t *istate)
    6868{
    69         bool restart_needed = false;
    70         uintptr_t restart_pc = 0;
     69        bool restart = false;
    7170
    7271        if (istate_from_uspace(istate)) {
    … …  
    7473                        if ((ras_page[RAS_START] < istate->pc) &&
    7574                            (ras_page[RAS_END] > istate->pc)) {
    76                                 restart_needed = true;
    77                                 restart_pc = ras_page[RAS_START];
     75                                restart = true;
    7876                        }
    7977                        ras_page[RAS_START] = 0;
    … …  
    8381
    8482        exc_dispatch(n, istate);
    85         if (restart_needed)
    86                 istate->pc = restart_pc;
     83        if (restart)
     84                istate->pc = ras_page[RAS_START];
    8785}
    8886
Note: See TracChangeset for help on using the changeset viewer.