Index: kernel/arch/mips32/src/asm.S
===================================================================
--- kernel/arch/mips32/src/asm.S	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/mips32/src/asm.S	(revision e0a4686ebb68dd7d42dd083c5ea6c37d6ced027d)
@@ -62,5 +62,5 @@
 FUNCTION_BEGIN(memcpy_to_uspace)
 	move $t2, $a0  /* save dst */
-	
+
 	addiu $v0, $a1, 3
 	li $v1, -4  /* 0xfffffffffffffffc */
@@ -68,9 +68,9 @@
 	beq $a1, $v0, 3f
 	move $t0, $a0
-	
+
 	0:
 		beq $a2, $zero, 2f
 		move $a3, $zero
-	
+
 	1:
 		addu $v0, $a1, $a3
@@ -80,9 +80,9 @@
 		bne $a3, $a2, 1b
 		sb $a0, 0($v1)
-	
+
 	2:
 		jr $ra
 		move $v0, $t2
-	
+
 	3:
 		addiu $v0, $a0, 3
@@ -90,11 +90,11 @@
 		bne $a0, $v0, 0b
 		srl $t1, $a2, 2
-		
+
 		beq $t1, $zero, 5f
 		move $a3, $zero
-		
+
 		move $a3, $zero
 		move $a0, $zero
-	
+
 	4:
 		addu $v0, $a1, $a0
@@ -105,15 +105,15 @@
 		bne $a3, $t1, 4b
 		addiu $a0, $a0, 4
-	
+
 	5:
 		andi $a2, $a2, 0x3
 		beq $a2, $zero, 2b
 		nop
-		
+
 		sll $v0, $a3, 2
 		addu $t1, $v0, $t0
 		move $a3, $zero
 		addu $t0, $v0, $a1
-	
+
 	6:
 		addu $v0, $t0, $a3
@@ -123,5 +123,5 @@
 		bne $a3, $a2, 6b
 		sb $a0, 0($v1)
-		
+
 		jr $ra
 		move $v0, $t2
@@ -188,5 +188,5 @@
 	fpu_gp_save 30, $a0
 	fpu_gp_save 31, $a0
-	
+
 	fpu_ct_save 1, $a0
 	fpu_ct_save 2, $a0
@@ -259,5 +259,5 @@
 	fpu_gp_restore 30, $a0
 	fpu_gp_restore 31, $a0
-	
+
 	fpu_ct_restore 1, $a0
 	fpu_ct_restore 2, $a0
Index: kernel/arch/mips32/src/context.S
===================================================================
--- kernel/arch/mips32/src/context.S	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/mips32/src/context.S	(revision e0a4686ebb68dd7d42dd083c5ea6c37d6ced027d)
@@ -47,8 +47,8 @@
 	sw $s8, CONTEXT_OFFSET_S8($a0)
 	sw $gp, CONTEXT_OFFSET_GP($a0)
-	
+
 	sw $ra, CONTEXT_OFFSET_PC($a0)
 	sw $sp, CONTEXT_OFFSET_SP($a0)
-	
+
 	# context_save returns 1
 	j $31
@@ -67,8 +67,8 @@
 	lw $s8, CONTEXT_OFFSET_S8($a0)
 	lw $gp, CONTEXT_OFFSET_GP($a0)
-	
+
 	lw $ra, CONTEXT_OFFSET_PC($a0)
 	lw $sp, CONTEXT_OFFSET_SP($a0)
-	
+
 	# context_restore returns 0
 	j $31
Index: kernel/arch/mips32/src/debug/stacktrace.c
===================================================================
--- kernel/arch/mips32/src/debug/stacktrace.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/mips32/src/debug/stacktrace.c	(revision e0a4686ebb68dd7d42dd083c5ea6c37d6ced027d)
@@ -157,5 +157,5 @@
 			 * We have a candidate for frame pointer.
 			 */
-			
+
 			/* Seek to the end of this function. */
 			for (cur = inst + 1; !IS_JR_RA(*cur); cur++)
@@ -170,5 +170,5 @@
 			continue;
 		}
-		
+
 		if (IS_JR_RA(*inst)) {
 			if (!ctx->istate)
@@ -189,5 +189,5 @@
 	} while ((!IS_ADDIU_SP_SP_IMM(*inst) && !IS_ADDI_SP_SP_IMM(*inst)) ||
 	    (IMM_GET(*inst) >= 0));
-	
+
 	/*
 	 * We are at the instruction which allocates the space for the current
@@ -210,5 +210,5 @@
 			if (base == SP || (has_fp && base == fp)) {
 				uint32_t *addr = (void *) (ctx->fp + offset);
-				
+
 				if (offset % 4 != 0)
 					return false;
Index: kernel/arch/mips32/src/debugger.c
===================================================================
--- kernel/arch/mips32/src/debugger.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/mips32/src/debugger.c	(revision e0a4686ebb68dd7d42dd083c5ea6c37d6ced027d)
@@ -138,10 +138,10 @@
 {
 	unsigned int i;
-	
+
 	for (i = 0; jmpinstr[i].andmask; i++) {
 		if ((instr & jmpinstr[i].andmask) == jmpinstr[i].value)
 			return true;
 	}
-	
+
 	return false;
 }
@@ -158,7 +158,7 @@
 		return 1;
 	}
-	
+
 	irq_spinlock_lock(&bkpoint_lock, true);
-	
+
 	/* Check, that the breakpoints do not conflict */
 	unsigned int i;
@@ -176,9 +176,9 @@
 			return 0;
 		}
-		
-	}
-	
+
+	}
+
 	bpinfo_t *cur = NULL;
-	
+
 	for (i = 0; i < BKPOINTS_MAX; i++) {
 		if (!breakpoints[i].address) {
@@ -187,5 +187,5 @@
 		}
 	}
-	
+
 	if (!cur) {
 		printf("Too many breakpoints.\n");
@@ -193,7 +193,7 @@
 		return 0;
 	}
-	
+
 	printf("Adding breakpoint on address %p\n", (void *) argv->intval);
-	
+
 	cur->address = (uintptr_t) argv->intval;
 	cur->instruction = ((sysarg_t *) cur->address)[0];
@@ -205,16 +205,16 @@
 		cur->bkfunc = (void (*)(void *, istate_t *)) argv[1].intval;
 	}
-	
+
 	if (is_jump(cur->instruction))
 		cur->flags |= BKPOINT_ONESHOT;
-	
+
 	cur->counter = 0;
-	
+
 	/* Set breakpoint */
 	*((sysarg_t *) cur->address) = 0x0d;
 	smc_coherence(cur->address);
-	
+
 	irq_spinlock_unlock(&bkpoint_lock, true);
-	
+
 	return 1;
 }
@@ -229,7 +229,7 @@
 		return 0;
 	}
-	
+
 	irq_spinlock_lock(&bkpoint_lock, true);
-	
+
 	bpinfo_t *cur = &breakpoints[argv->intval];
 	if (!cur->address) {
@@ -238,5 +238,5 @@
 		return 0;
 	}
-	
+
 	if ((cur->flags & BKPOINT_INPROG) && (cur->flags & BKPOINT_ONESHOT)) {
 		printf("Cannot remove one-shot breakpoint in-progress\n");
@@ -244,12 +244,12 @@
 		return 0;
 	}
-	
+
 	((uint32_t *) cur->address)[0] = cur->instruction;
 	smc_coherence(((uint32_t *) cur->address)[0]);
 	((uint32_t *) cur->address)[1] = cur->nextinstruction;
 	smc_coherence(((uint32_t *) cur->address)[1]);
-	
+
 	cur->address = (uintptr_t) NULL;
-	
+
 	irq_spinlock_unlock(&bkpoint_lock, true);
 	return 1;
@@ -262,12 +262,12 @@
 {
 	unsigned int i;
-	
+
 	printf("[nr] [count] [address ] [inprog] [oneshot] [funccall] [in symbol\n");
-	
+
 	for (i = 0; i < BKPOINTS_MAX; i++) {
 		if (breakpoints[i].address) {
 			const char *symbol = symtab_fmt_name_lookup(
 			    breakpoints[i].address);
-			
+
 			printf("%-4u %7zu %p %-8s %-9s %-10s %s\n", i,
 			    breakpoints[i].counter, (void *) breakpoints[i].address,
@@ -278,5 +278,5 @@
 		}
 	}
-	
+
 	return 1;
 }
@@ -290,8 +290,8 @@
 {
 	unsigned int i;
-	
+
 	for (i = 0; i < BKPOINTS_MAX; i++)
 		breakpoints[i].address = (uintptr_t) NULL;
-	
+
 #ifdef CONFIG_KCONSOLE
 	cmd_initialize(&bkpts_info);
@@ -299,15 +299,15 @@
 		log(LF_OTHER, LVL_WARN, "Cannot register command %s",
 		    bkpts_info.name);
-	
+
 	cmd_initialize(&delbkpt_info);
 	if (!cmd_register(&delbkpt_info))
 		log(LF_OTHER, LVL_WARN, "Cannot register command %s",
 		    delbkpt_info.name);
-	
+
 	cmd_initialize(&addbkpt_info);
 	if (!cmd_register(&addbkpt_info))
 		log(LF_OTHER, LVL_WARN, "Cannot register command %s",
 		    addbkpt_info.name);
-	
+
 	cmd_initialize(&addbkpte_info);
 	if (!cmd_register(&addbkpte_info))
@@ -331,11 +331,11 @@
 	if (cp0_cause_read() & 0x80000000)
 		panic("Breakpoint in branch delay slot not supported.");
-	
+
 	irq_spinlock_lock(&bkpoint_lock, false);
-	
+
 	bpinfo_t *cur = NULL;
 	uintptr_t fireaddr = istate->epc;
 	unsigned int i;
-	
+
 	for (i = 0; i < BKPOINTS_MAX; i++) {
 		/* Normal breakpoint */
@@ -345,5 +345,5 @@
 			break;
 		}
-		
+
 		/* Reinst only breakpoint */
 		if ((breakpoints[i].flags & BKPOINT_REINST) &&
@@ -353,5 +353,5 @@
 		}
 	}
-	
+
 	if (cur) {
 		if (cur->flags & BKPOINT_REINST) {
@@ -359,17 +359,17 @@
 			((uint32_t *) cur->address)[0] = 0x0d;
 			smc_coherence(((uint32_t *)cur->address)[0]);
-			
+
 			/* Return back the second */
 			((uint32_t *) cur->address)[1] = cur->nextinstruction;
 			smc_coherence(((uint32_t *) cur->address)[1]);
-			
+
 			cur->flags &= ~BKPOINT_REINST;
 			irq_spinlock_unlock(&bkpoint_lock, false);
 			return;
 		}
-		
+
 		if (cur->flags & BKPOINT_INPROG)
 			printf("Warning: breakpoint recursion\n");
-		
+
 		if (!(cur->flags & BKPOINT_FUNCCALL)) {
 			printf("***Breakpoint %u: %p in %s.\n", i,
@@ -377,5 +377,5 @@
 			    symtab_fmt_name_lookup(fireaddr));
 		}
-		
+
 		/* Return first instruction back */
 		((uint32_t *)cur->address)[0] = cur->instruction;
@@ -392,12 +392,12 @@
 		    (void *) fireaddr,
 		    symtab_fmt_name_lookup(fireaddr));
-		
+
 		/* Move on to next instruction */
 		istate->epc += 4;
 	}
-	
+
 	if (cur)
 		cur->counter++;
-	
+
 	if (cur && (cur->flags & BKPOINT_FUNCCALL)) {
 		/* Allow zero bkfunc, just for counting */
@@ -414,12 +414,12 @@
 		atomic_set(&haltstate, 1);
 		irq_spinlock_unlock(&bkpoint_lock, false);
-		
+
 		kconsole("debug", "Debug console ready.\n", false);
-		
+
 		irq_spinlock_lock(&bkpoint_lock, false);
 		atomic_set(&haltstate, 0);
 #endif
 	}
-	
+
 	if ((cur) && (cur->address == fireaddr)
 	    && ((cur->flags & BKPOINT_INPROG))) {
@@ -427,9 +427,9 @@
 		if ((cur->flags & BKPOINT_ONESHOT))
 			cur->address = (uintptr_t) NULL;
-		
+
 		/* Remove in-progress flag */
 		cur->flags &= ~BKPOINT_INPROG;
 	}
-	
+
 	irq_spinlock_unlock(&bkpoint_lock, false);
 }
Index: kernel/arch/mips32/src/exception.c
===================================================================
--- kernel/arch/mips32/src/exception.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/mips32/src/exception.c	(revision e0a4686ebb68dd7d42dd083c5ea6c37d6ced027d)
@@ -77,33 +77,33 @@
 	    "lo =%#010" PRIx32 "\thi =%#010" PRIx32 "\n",
 	    istate->epc, istate->status, istate->lo, istate->hi);
-	
+
 	log_printf("a0 =%#010" PRIx32 "\ta1 =%#010" PRIx32 "\t"
 	    "a2 =%#010" PRIx32 "\ta3 =%#010" PRIx32 "\n",
 	    istate->a0, istate->a1, istate->a2, istate->a3);
-	
+
 	log_printf("t0 =%#010" PRIx32 "\tt1 =%#010" PRIx32 "\t"
 	    "t2 =%#010" PRIx32 "\tt3 =%#010" PRIx32 "\n",
 	    istate->t0, istate->t1, istate->t2, istate->t3);
-	
+
 	log_printf("t4 =%#010" PRIx32 "\tt5 =%#010" PRIx32 "\t"
 	    "t6 =%#010" PRIx32 "\tt7 =%#010" PRIx32 "\n",
 	    istate->t4, istate->t5, istate->t6, istate->t7);
-	
+
 	log_printf("t8 =%#010" PRIx32 "\tt9 =%#010" PRIx32 "\t"
 	    "v0 =%#010" PRIx32 "\tv1 =%#010" PRIx32 "\n",
 	    istate->t8, istate->t9, istate->v0, istate->v1);
-	
+
 	log_printf("s0 =%#010" PRIx32 "\ts1 =%#010" PRIx32 "\t"
 	    "s2 =%#010" PRIx32 "\ts3 =%#010" PRIx32 "\n",
 	    istate->s0, istate->s1, istate->s2, istate->s3);
-	
+
 	log_printf("s4 =%#010" PRIx32 "\ts5 =%#010" PRIx32 "\t"
 	    "s6 =%#010" PRIx32 "\ts7 =%#010" PRIx32 "\n",
 	    istate->s4, istate->s5, istate->s6, istate->s7);
-	
+
 	log_printf("s8 =%#010" PRIx32 "\tat =%#010" PRIx32 "\t"
 	    "kt0=%#010" PRIx32 "\tkt1=%#010" PRIx32 "\n",
 	    istate->s8, istate->at, istate->kt0, istate->kt1);
-	
+
 	log_printf("sp =%#010" PRIx32 "\tra =%#010" PRIx32 "\t"
 	    "gp =%#010" PRIx32 "\n",
@@ -171,5 +171,5 @@
 	ip = (cp0_cause_read() & cp0_cause_ip_mask) >> cp0_cause_ip_shift;
 	im = (cp0_status_read() & cp0_status_im_mask) >> cp0_status_im_shift;
-	
+
 	unsigned int i;
 	for (i = 0; i < 8; i++) {
@@ -212,10 +212,10 @@
 {
 	unsigned int i;
-	
+
 	/* Clear exception table */
 	for (i = 0; i < IVT_ITEMS; i++)
 		exc_register(i, "undef", false,
 		    (iroutine_t) unhandled_exception);
-	
+
 	exc_register(EXC_Bp, "bkpoint", true,
 	    (iroutine_t) breakpoint_exception);
@@ -230,10 +230,10 @@
 	exc_register(EXC_Int, "interrupt", true,
 	    (iroutine_t) interrupt_exception);
-	
+
 #ifdef CONFIG_FPU_LAZY
 	exc_register(EXC_CpU, "cpunus", true,
 	    (iroutine_t) cpuns_exception);
 #endif
-	
+
 	exc_register(EXC_Sys, "syscall", true,
 	    (iroutine_t) syscall_exception);
Index: kernel/arch/mips32/src/interrupt.c
===================================================================
--- kernel/arch/mips32/src/interrupt.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/mips32/src/interrupt.c	(revision e0a4686ebb68dd7d42dd083c5ea6c37d6ced027d)
@@ -132,7 +132,7 @@
 		/* Count overflow detected */
 		count_hi++;
-	
+
 	lastcount = cp0_count_read();
-	
+
 	unsigned long drift = cp0_count_read() - nextcount;
 	while (drift > cp0_compare_value) {
@@ -140,8 +140,8 @@
 		CPU->missed_clock_ticks++;
 	}
-	
+
 	nextcount = cp0_count_read() + cp0_compare_value - drift;
 	cp0_compare_write(nextcount);
-	
+
 	/*
 	 * We are holding a lock which prevents preemption.
@@ -151,5 +151,5 @@
 	clock();
 	irq_spinlock_lock(&irq->lock, false);
-	
+
 	if (virtual_timer_fnc != NULL)
 		virtual_timer_fnc();
@@ -172,5 +172,5 @@
 {
 	irq_init(IRQ_COUNT, IRQ_COUNT);
-	
+
 	irq_initialize(&timer_irq);
 	timer_irq.inr = TIMER_IRQ;
@@ -178,8 +178,8 @@
 	timer_irq.handler = timer_irq_handler;
 	irq_register(&timer_irq);
-	
+
 	timer_start();
 	cp0_unmask_int(TIMER_IRQ);
-	
+
 #ifdef MACHINE_msim
 	irq_initialize(&dorder_irq);
@@ -188,5 +188,5 @@
 	dorder_irq.handler = dorder_irq_handler;
 	irq_register(&dorder_irq);
-	
+
 	cp0_unmask_int(DORDER_IRQ);
 #endif
Index: kernel/arch/mips32/src/mips32.c
===================================================================
--- kernel/arch/mips32/src/mips32.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/mips32/src/mips32.c	(revision e0a4686ebb68dd7d42dd083c5ea6c37d6ced027d)
@@ -86,5 +86,5 @@
 {
 	init.cnt = min3(bootinfo->cnt, TASKMAP_MAX_RECORDS, CONFIG_INIT_TASKS);
-	
+
 	size_t i;
 	for (i = 0; i < init.cnt; i++) {
@@ -94,5 +94,5 @@
 		    bootinfo->tasks[i].name);
 	}
-	
+
 	for (i = 0; i < CPUMAP_MAX_RECORDS; i++) {
 		if ((bootinfo->cpumap & (1 << i)) != 0)
@@ -112,5 +112,5 @@
 	/* It is not assumed by default */
 	interrupts_disable();
-	
+
 	/* Initialize dispatch table */
 	exception_init();
@@ -123,5 +123,5 @@
 	memcpy(CACHE_EXC, (char *) cache_error_entry, EXCEPTION_JUMP_SIZE);
 	smc_coherence_block(CACHE_EXC, EXCEPTION_JUMP_SIZE);
-	
+
 	/*
 	 * Switch to BEV normal level so that exception vectors point to the
@@ -130,10 +130,10 @@
 	cp0_status_write(cp0_status_read() &
 	    ~(cp0_status_bev_bootstrap_bit | cp0_status_erl_error_bit));
-	
+
 	/*
 	 * Mask all interrupts
 	 */
 	cp0_mask_all_int();
-	
+
 	debugger_init();
 }
@@ -171,5 +171,5 @@
 	    (uintptr_t) kernel_uarg->uspace_uarg,
 	    (uintptr_t) kernel_uarg->uspace_entry);
-	
+
 	while (1);
 }
Index: kernel/arch/mips32/src/mm/frame.c
===================================================================
--- kernel/arch/mips32/src/mm/frame.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/mips32/src/mm/frame.c	(revision e0a4686ebb68dd7d42dd083c5ea6c37d6ced027d)
@@ -82,5 +82,5 @@
 	if (frame == (KA2PA(MSIM_VIDEORAM) >> ZERO_PAGE_WIDTH))
 		return false;
-	
+
 	/* MSIM device (dkeyboard) */
 	if (frame == (KA2PA(MSIM_KBD_ADDRESS) >> ZERO_PAGE_WIDTH))
@@ -92,5 +92,5 @@
 		return false;
 #endif
-	
+
 	return true;
 }
@@ -108,15 +108,15 @@
 	if ((frame << ZERO_PAGE_WIDTH) < KA2PA(config.base))
 		return false;
-	
+
 	/* Kernel */
 	if (overlaps(frame << ZERO_PAGE_WIDTH, ZERO_PAGE_SIZE,
 	    KA2PA(config.base), config.kernel_size))
 		return false;
-	
+
 	/* Kernel stack */
 	if (overlaps(frame << ZERO_PAGE_WIDTH, ZERO_PAGE_SIZE,
 	    KA2PA(config.stack_base), config.stack_size))
 		return false;
-	
+
 	/* Init tasks */
 	bool safe = true;
@@ -128,5 +128,5 @@
 			break;
 		}
-	
+
 	return safe;
 }
@@ -161,5 +161,5 @@
 			    ZONE_AVAILABLE | ZONE_HIGHMEM);
 	}
-	
+
 	if (phys_regions_count < MAX_REGIONS) {
 		phys_regions[phys_regions_count].start = first;
@@ -182,5 +182,5 @@
 {
 	ipl_t ipl = interrupts_disable();
-	
+
 	/* Clear and initialize TLB */
 	cp0_pagemask_write(ZERO_PAGE_MASK);
@@ -194,9 +194,9 @@
 		tlbwi();
 	}
-		
+
 	pfn_t start_frame = 0;
 	pfn_t frame;
 	bool avail = true;
-	
+
 	/* Walk through all 1 MB frames */
 	for (frame = 0; frame < ZERO_FRAMES; frame++) {
@@ -211,5 +211,5 @@
 				tlb_prepare_entry_lo(&lo1, false, false, false, false, 0);
 				tlb_prepare_entry_hi(&hi, ZERO_PAGE_ASID, ZERO_PAGE_ADDR);
-				
+
 				cp0_pagemask_write(ZERO_PAGE_MASK);
 				cp0_entry_lo0_write(lo0.value);
@@ -218,5 +218,5 @@
 				cp0_index_write(ZERO_PAGE_TLBI);
 				tlbwi();
-				
+
 				ZERO_PAGE_VALUE = 0;
 				if (ZERO_PAGE_VALUE != 0)
@@ -229,5 +229,5 @@
 			}
 		}
-		
+
 		if (!avail) {
 			frame_add_region(start_frame, frame, true);
@@ -236,7 +236,7 @@
 		}
 	}
-	
+
 	frame_add_region(start_frame, frame, true);
-	
+
 	/* Blacklist interrupt vector frame */
 	frame_mark_unavailable(0, 1);
@@ -267,5 +267,5 @@
 	frame_mark_unavailable(0, 1024 * 1024 / FRAME_SIZE);
 #endif
-	
+
 	/* Cleanup */
 	cp0_pagemask_write(ZERO_PAGE_MASK);
@@ -275,5 +275,5 @@
 	cp0_index_write(ZERO_PAGE_TLBI);
 	tlbwi();
-	
+
 	interrupts_restore(ipl);
 }
@@ -286,5 +286,5 @@
 {
 	printf("[base    ] [size    ]\n");
-	
+
 	size_t i;
 	for (i = 0; i < phys_regions_count; i++) {
Index: kernel/arch/mips32/src/mm/tlb.c
===================================================================
--- kernel/arch/mips32/src/mm/tlb.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/mips32/src/mm/tlb.c	(revision e0a4686ebb68dd7d42dd083c5ea6c37d6ced027d)
@@ -76,10 +76,10 @@
 
 	/* Clear and initialize TLB. */
-	
+
 	for (i = 0; i < TLB_ENTRY_COUNT; i++) {
 		cp0_index_write(i);
 		tlbwi();
 	}
-	
+
 	/*
 	 * The kernel is going to make use of some wired
@@ -98,5 +98,5 @@
 	uintptr_t badvaddr;
 	pte_t pte;
-	
+
 	badvaddr = cp0_badvaddr_read();
 
@@ -291,16 +291,16 @@
 	lo1_save.value = cp0_entry_lo1_read();
 	mask_save.value = cp0_pagemask_read();
-	
+
 	printf("[nr] [asid] [vpn2    ] [mask] [gvdc] [pfn     ]\n");
-	
+
 	for (i = 0; i < TLB_ENTRY_COUNT; i++) {
 		cp0_index_write(i);
 		tlbr();
-		
+
 		mask.value = cp0_pagemask_read();
 		hi.value = cp0_entry_hi_read();
 		lo0.value = cp0_entry_lo0_read();
 		lo1.value = cp0_entry_lo1_read();
-		
+
 		printf("%-4u %-6u %0#10x %-#6x  %1u%1u%1u%1u  %0#10x\n",
 		    i, hi.asid, HI_VPN22ADDR(hi.vpn2), mask.mask,
@@ -309,5 +309,5 @@
 		    lo1.g, lo1.v, lo1.d, lo1.c, LO_PFN2ADDR(lo1.pfn));
 	}
-	
+
 	cp0_entry_hi_write(hi_save.value);
 	cp0_entry_lo0_write(lo0_save.value);
@@ -339,8 +339,8 @@
 		cp0_entry_lo0_write(lo0.value);
 		cp0_entry_lo1_write(lo1.value);
-				
+
 		tlbwi();
 	}
-	
+
 	cp0_entry_hi_write(hi_save.value);
 }
@@ -360,11 +360,11 @@
 
 	hi_save.value = cp0_entry_hi_read();
-	
+
 	for (i = 0; i < TLB_ENTRY_COUNT; i++) {
 		cp0_index_write(i);
 		tlbr();
-		
+
 		hi.value = cp0_entry_hi_read();
-		
+
 		if (hi.asid == asid) {
 			lo0.value = cp0_entry_lo0_read();
@@ -380,5 +380,5 @@
 		}
 	}
-	
+
 	cp0_entry_hi_write(hi_save.value);
 }
@@ -399,5 +399,5 @@
 
 	assert(interrupts_disabled());
-	
+
 	if (asid == ASID_INVALID)
 		return;
@@ -431,5 +431,5 @@
 		}
 	}
-	
+
 	cp0_entry_hi_write(hi_save.value);
 }
Index: kernel/arch/mips32/src/start.S
===================================================================
--- kernel/arch/mips32/src/start.S	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/mips32/src/start.S	(revision e0a4686ebb68dd7d42dd083c5ea6c37d6ced027d)
@@ -89,25 +89,25 @@
 	sw $s7, ISTATE_OFFSET_S7(\r)
 	sw $s8, ISTATE_OFFSET_S8(\r)
-	
+
 	mflo $at
 	sw $at, ISTATE_OFFSET_LO(\r)
 	mfhi $at
 	sw $at, ISTATE_OFFSET_HI(\r)
-	
+
 	sw $gp, ISTATE_OFFSET_GP(\r)
 	sw $ra, ISTATE_OFFSET_RA(\r)
 	sw $k0, ISTATE_OFFSET_KT0(\r)
 	sw $k1, ISTATE_OFFSET_KT1(\r)
-	
+
 	mfc0 $t0, $status
 	mfc0 $t1, $epc
-	
+
 	/* save only KSU, EXL, ERL, IE */
 	and $t2, $t0, REG_SAVE_MASK
-	
+
 	/* clear KSU, EXL, ERL, IE */
 	li $t3, ~(REG_SAVE_MASK)
 	and $t0, $t0, $t3
-	
+
 	sw $t2, ISTATE_OFFSET_STATUS(\r)
 	sw $t1, ISTATE_OFFSET_EPC(\r)
@@ -122,13 +122,13 @@
 	mfc0 $t0, $status
 	lw $t1, ISTATE_OFFSET_STATUS(\r)
-	
+
 	/* mask UM, EXL, ERL, IE */
 	li $t2, ~REG_SAVE_MASK
 	and $t0, $t0, $t2
-	
+
 	/* copy UM, EXL, ERL, IE from saved status */
 	or $t0, $t0, $t1
 	mtc0 $t0, $status
-	
+
 	lw $v0, ISTATE_OFFSET_V0(\r)
 	lw $v1, ISTATE_OFFSET_V1(\r)
@@ -147,17 +147,17 @@
 	lw $t8, ISTATE_OFFSET_T8(\r)
 	lw $t9, ISTATE_OFFSET_T9(\r)
-	
+
 	lw $gp, ISTATE_OFFSET_GP(\r)
 	lw $ra, ISTATE_OFFSET_RA(\r)
 	lw $k1, ISTATE_OFFSET_KT1(\r)
-	
+
 	lw $at, ISTATE_OFFSET_LO(\r)
 	mtlo $at
 	lw $at, ISTATE_OFFSET_HI(\r)
 	mthi $at
-	
+
 	lw $at, ISTATE_OFFSET_EPC(\r)
 	mtc0 $at, $epc
-	
+
 	lw $at, ISTATE_OFFSET_AT(\r)
 	lw $sp, ISTATE_OFFSET_SP(\r)
@@ -172,14 +172,14 @@
 	mfc0 $k0, $status
 	andi $k0, 0x10
-	
+
 	beq $k0, $0, 1f
 	move $k0, $sp
-	
+
 	/* move $k0 pointer to kernel stack */
 	la $k0, supervisor_sp
-	
+
 	/* move $k0 (supervisor_sp) */
 	lw $k0, ($k0)
-	
+
 	1:
 .endm
@@ -190,12 +190,12 @@
 	lui $sp, %hi(end_stack)
 	ori $sp, $sp, %lo(end_stack)
-	
+
 	/* not sure about this, but might be needed for PIC code */
 	lui $gp, 0x8000
-	
+
 	/* $a1 contains physical address of bootinfo_t */
 	jal mips32_pre_main
 	addiu $sp, -ABI_STACK_FRAME
-	
+
 	j main_bsp
 	nop
@@ -219,20 +219,20 @@
 exception_handler:
 	KERNEL_STACK_TO_K0
-	
+
 	sub $k0, ISTATE_SIZE
 	sw $sp, ISTATE_OFFSET_SP($k0)
 	move $sp, $k0
-	
+
 	mfc0 $k0, $cause
-	
+
 	sra $k0, $k0, 0x2    /* cp0_exc_cause() part 1 */
 	andi $k0, $k0, 0x1f  /* cp0_exc_cause() part 2 */
 	sub $k0, 8           /* 8 = SYSCALL */
-	
+
 	beqz $k0, syscall_shortcut
 	add $k0, 8           /* revert $k0 back to correct exc number */
-	
+
 	REGISTERS_STORE_AND_EXC_RESET $sp
-	
+
 	move $a1, $sp
 	move $a0, $k0
@@ -240,5 +240,5 @@
 	addiu $sp, -ABI_STACK_FRAME
 	addiu $sp, ABI_STACK_FRAME
-	
+
 	REGISTERS_LOAD $sp
 	/* the $sp is automatically restored to former value */
@@ -265,13 +265,13 @@
 	sw $t3, ISTATE_OFFSET_EPC($sp)  /* save EPC */
 	sw $k1, ISTATE_OFFSET_KT1($sp)  /* save $k1 not saved on context switch */
-	
+
 	and $t4, $t2, REG_SAVE_MASK  /* save only KSU, EXL, ERL, IE */
 	li $t5, ~(0x1f)
 	and $t2, $t2, $t5  /* clear KSU, EXL, ERL */
 	ori $t2, $t2, 0x1  /* set IE */
-	
+
 	sw $t4, ISTATE_OFFSET_STATUS($sp)
 	mtc0 $t2, $status
-	
+
 	/*
 	 * Call the higher level system call handler.
@@ -280,12 +280,12 @@
 	sw $t0, ISTATE_OFFSET_T0($sp)  /* save the 5th argument on the stack */
 	sw $t1, ISTATE_OFFSET_T1($sp)  /* save the 6th argument on the stack */
-	
+
 	jal syscall_handler
 	sw $v0, ISTATE_OFFSET_V0($sp)  /* save the syscall number on the stack */
-	
+
 	/* restore status */
 	mfc0 $t2, $status
 	lw $t3, ISTATE_OFFSET_STATUS($sp)
-	
+
 	/*
 	 * Change back to EXL = 1 (from last exception), otherwise
@@ -297,5 +297,5 @@
 	or $t2, $t2, $t3  /* copy saved UM, EXL, ERL, IE */
 	mtc0 $t2, $status
-	
+
 	/* restore epc + 4 */
 	lw $t2, ISTATE_OFFSET_EPC($sp)
@@ -303,5 +303,5 @@
 	addi $t2, $t2, 4
 	mtc0 $t2, $epc
-	
+
 	lw $sp, ISTATE_OFFSET_SP($sp)  /* restore $sp */
 	eret
@@ -314,10 +314,10 @@
 	sw $sp, ISTATE_OFFSET_SP($k0)
 	move $sp, $k0
-	
+
 	move $a0, $sp
 	jal tlb_refill
 	addiu $sp, -ABI_STACK_FRAME
 	addiu $sp, ABI_STACK_FRAME
-	
+
 	REGISTERS_LOAD $sp
 	eret
@@ -330,10 +330,10 @@
 	sw $sp, ISTATE_OFFSET_SP($k0)
 	move $sp, $k0
-	
+
 	move $a0, $sp
 	jal cache_error
 	addiu $sp, -ABI_STACK_FRAME
 	addiu $sp, ABI_STACK_FRAME
-	
+
 	REGISTERS_LOAD $sp
 	eret