Index: kernel/arch/sparc64/src/mm/sun4v/tsb.c
===================================================================
--- kernel/arch/sparc64/src/mm/sun4v/tsb.c	(revision d99c1d2ba8c7b2c687d430f2e9fd237046606545)
+++ kernel/arch/sparc64/src/mm/sun4v/tsb.c	(revision e08162be96bc4ff41d0a733317b13d516f1e1b6d)
@@ -44,6 +44,4 @@
 #include <debug.h>
 
-#define TSB_INDEX_MASK	((1 << (21 + 1 + TSB_SIZE - MMU_PAGE_WIDTH)) - 1)
-
 /** Invalidate portion of TSB.
  *
@@ -58,4 +56,5 @@
 void tsb_invalidate(as_t *as, uintptr_t page, size_t pages)
 {
+	tsb_entry_t *tsb;
 	size_t i0, i;
 	size_t cnt;
@@ -63,16 +62,14 @@
 	ASSERT(as->arch.tsb_description.tsb_base);
 	
-	i0 = (page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK;
-	ASSERT(i0 < TSB_ENTRY_COUNT);
+	i0 = (page >> MMU_PAGE_WIDTH) & TSB_ENTRY_MASK;
 
-	if (pages == (size_t) - 1 || (pages) > TSB_ENTRY_COUNT)
+	if (pages == (size_t) -1 || pages > TSB_ENTRY_COUNT)
 		cnt = TSB_ENTRY_COUNT;
 	else
 		cnt = pages;
 	
-	for (i = 0; i < cnt; i++) {
-		((tsb_entry_t *) PA2KA(as->arch.tsb_description.tsb_base))[
-			(i0 + i) & (TSB_ENTRY_COUNT - 1)].data.v = false;
-	}
+	tsb = (tsb_entry_t *) PA2KA(as->arch.tsb_description.tsb_base);
+	for (i = 0; i < cnt; i++)
+		tsb[(i0 + i) & TSB_ENTRY_MASK].data.v = false;
 }
 
@@ -85,10 +82,12 @@
 	as_t *as;
 	tsb_entry_t *tsb;
-	size_t entry;
+	tsb_entry_t *tte;
+	size_t index;
 
 	as = t->as;
-	entry = (t->page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK; 
-	ASSERT(entry < TSB_ENTRY_COUNT);
-	tsb = &((tsb_entry_t *) PA2KA(as->arch.tsb_description.tsb_base))[entry];
+	index = (t->page >> MMU_PAGE_WIDTH) & TSB_ENTRY_MASK; 
+	
+	tsb = (tsb_entry_t *) PA2KA(as->arch.tsb_description.tsb_base);
+	tte = &tsb[index];
 
 	/*
@@ -98,25 +97,25 @@
 	 */
 
-	tsb->data.v = false;
+	tte->data.v = false;
 
 	write_barrier();
 
-	tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
+	tte->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
 
-	tsb->data.value = 0;
-	tsb->data.nfo = false;
-	tsb->data.ra = t->frame >> MMU_FRAME_WIDTH;
-	tsb->data.ie = false;
-	tsb->data.e = false;
-	tsb->data.cp = t->c;	/* cp as cache in phys.-idxed, c as cacheable */
-	tsb->data.cv = false;
-	tsb->data.p = t->k;	/* p as privileged, k as kernel */
-	tsb->data.x = true;
-	tsb->data.w = false;
-	tsb->data.size = PAGESIZE_8K;
+	tte->data.value = 0;
+	tte->data.nfo = false;
+	tte->data.ra = t->frame >> MMU_FRAME_WIDTH;
+	tte->data.ie = false;
+	tte->data.e = false;
+	tte->data.cp = t->c;	/* cp as cache in phys.-idxed, c as cacheable */
+	tte->data.cv = false;
+	tte->data.p = t->k;	/* p as privileged, k as kernel */
+	tte->data.x = true;
+	tte->data.w = false;
+	tte->data.size = PAGESIZE_8K;
 	
 	write_barrier();
 	
-	tsb->data.v = t->p;	/* v as valid, p as present */
+	tte->data.v = t->p;	/* v as valid, p as present */
 }
 
@@ -130,10 +129,11 @@
 	as_t *as;
 	tsb_entry_t *tsb;
-	size_t entry;
+	tsb_entry_t *tte;
+	size_t index;
 
 	as = t->as;
-	entry = (t->page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK; 
-	ASSERT(entry < TSB_ENTRY_COUNT);
-	tsb = &((tsb_entry_t *) PA2KA(as->arch.tsb_description.tsb_base))[entry];
+	index = (t->page >> MMU_PAGE_WIDTH) & TSB_ENTRY_MASK;
+	tsb = (tsb_entry_t *) PA2KA(as->arch.tsb_description.tsb_base);
+	tte = &tsb[index];
 
 	/*
@@ -143,27 +143,27 @@
 	 */
 
-	tsb->data.v = false;
+	tte->data.v = false;
 
 	write_barrier();
 
-	tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
+	tte->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
 
-	tsb->data.value = 0;
-	tsb->data.nfo = false;
-	tsb->data.ra = t->frame >> MMU_FRAME_WIDTH;
-	tsb->data.ie = false;
-	tsb->data.e = false;
-	tsb->data.cp = t->c;	/* cp as cache in phys.-idxed, c as cacheable */
+	tte->data.value = 0;
+	tte->data.nfo = false;
+	tte->data.ra = t->frame >> MMU_FRAME_WIDTH;
+	tte->data.ie = false;
+	tte->data.e = false;
+	tte->data.cp = t->c;	/* cp as cache in phys.-idxed, c as cacheable */
 #ifdef CONFIG_VIRT_IDX_DCACHE
-	tsb->data.cv = t->c;
+	tte->data.cv = t->c;
 #endif /* CONFIG_VIRT_IDX_DCACHE */
-	tsb->data.p = t->k;	/* p as privileged, k as kernel */
-	tsb->data.x = true;
-	tsb->data.w = ro ? false : t->w;
-	tsb->data.size = PAGESIZE_8K;
+	tte->data.p = t->k;	/* p as privileged, k as kernel */
+	tte->data.x = true;
+	tte->data.w = ro ? false : t->w;
+	tte->data.size = PAGESIZE_8K;
 	
 	write_barrier();
 	
-	tsb->data.v = t->p;	/* v as valid, p as present */
+	tte->data.v = t->p;	/* v as valid, p as present */
 }
 
