Changeset e08162b in mainline for kernel/arch/sparc64/src/mm/sun4v


Ignore:
Timestamp:
2016-01-07T13:41:38Z (10 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
f4582c6
Parents:
7254df6
Message:

sparc64: TSB needs to be naturally aligned

The ITSB and DTSB on sun4u and the TSB on sun4v are mapped by a single
64K page, so they need to be aligned to 64K. Moreover, the TSB pointer
contruction demands the natural alignment: 32K for ITSB/DTSB on sun4u
and 64K for the unified TSB on sun4v.

The code was also streamlined and made more beautiful.

Location:
kernel/arch/sparc64/src/mm/sun4v
Files:
2 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/sparc64/src/mm/sun4v/as.c

    r7254df6 re08162b  
    6666{
    6767#ifdef CONFIG_TSB
    68         uintptr_t tsb =
    69             frame_alloc(SIZE2FRAMES(TSB_ENTRY_COUNT * sizeof(tsb_entry_t)),
    70             flags, 0);
    71         if (!tsb)
     68        uintptr_t tsb_base = frame_alloc(TSB_FRAMES, flags, TSB_SIZE - 1);
     69        if (!tsb_base)
    7270                return -1;
    73        
     71
     72        tsb_entry_t *tsb = (tsb_entry_t *) PA2KA(tsb_base);
     73
    7474        as->arch.tsb_description.page_size = PAGESIZE_8K;
    7575        as->arch.tsb_description.associativity = 1;
    7676        as->arch.tsb_description.num_ttes = TSB_ENTRY_COUNT;
    7777        as->arch.tsb_description.pgsize_mask = 1 << PAGESIZE_8K;
    78         as->arch.tsb_description.tsb_base = tsb;
     78        as->arch.tsb_description.tsb_base = tsb_base;
    7979        as->arch.tsb_description.reserved = 0;
    8080        as->arch.tsb_description.context = 0;
    8181       
    82         memsetb((void *) PA2KA(as->arch.tsb_description.tsb_base),
    83                 TSB_ENTRY_COUNT * sizeof(tsb_entry_t), 0);
     82        memsetb(tsb, TSB_SIZE, 0);
    8483#endif
    8584       
    … …  
    9089{
    9190#ifdef CONFIG_TSB
    92         size_t frames = SIZE2FRAMES(TSB_ENTRY_COUNT * sizeof(tsb_entry_t));
    93         frame_free(as->arch.tsb_description.tsb_base, frames);
     91        frame_free(as->arch.tsb_description.tsb_base, TSB_FRAMES);
    9492       
    95         return frames;
     93        return TSB_FRAMES;
    9694#else
    9795        return 0;
    … …  
    126124        uintptr_t tsb = PA2KA(as->arch.tsb_description.tsb_base);
    127125       
    128         if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
     126        if (!overlaps(tsb, TSB_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
    129127                /*
    130128                 * TSBs were allocated from memory not covered
    … …  
    137135        }
    138136       
    139         __hypercall_fast2(MMU_TSB_CTXNON0, 1, KA2PA(&(as->arch.tsb_description)));
     137        __hypercall_fast2(MMU_TSB_CTXNON0, 1, KA2PA(&as->arch.tsb_description));
    140138#endif
    141139}
    … …  
    166164        uintptr_t tsb = PA2KA(as->arch.tsb_description.tsb_base);
    167165       
    168         if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
     166        if (!overlaps(tsb, TSB_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
    169167                /*
    170168                 * TSBs were allocated from memory not covered

  • kernel/arch/sparc64/src/mm/sun4v/tsb.c

    r7254df6 re08162b  
    4444#include <debug.h>
    4545
    46 #define TSB_INDEX_MASK  ((1 << (21 + 1 + TSB_SIZE - MMU_PAGE_WIDTH)) - 1)
    47 
    4846/** Invalidate portion of TSB.
    4947 *
    … …  
    5856void tsb_invalidate(as_t *as, uintptr_t page, size_t pages)
    5957{
     58        tsb_entry_t *tsb;
    6059        size_t i0, i;
    6160        size_t cnt;
    … …  
    6362        ASSERT(as->arch.tsb_description.tsb_base);
    6463       
    65         i0 = (page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK;
    66         ASSERT(i0 < TSB_ENTRY_COUNT);
     64        i0 = (page >> MMU_PAGE_WIDTH) & TSB_ENTRY_MASK;
    6765
    68         if (pages == (size_t) - 1 || (pages) > TSB_ENTRY_COUNT)
     66        if (pages == (size_t) -1 || pages > TSB_ENTRY_COUNT)
    6967                cnt = TSB_ENTRY_COUNT;
    7068        else
    7169                cnt = pages;
    7270       
    73         for (i = 0; i < cnt; i++) {
    74                 ((tsb_entry_t *) PA2KA(as->arch.tsb_description.tsb_base))[
    75                         (i0 + i) & (TSB_ENTRY_COUNT - 1)].data.v = false;
    76         }
     71        tsb = (tsb_entry_t *) PA2KA(as->arch.tsb_description.tsb_base);
     72        for (i = 0; i < cnt; i++)
     73                tsb[(i0 + i) & TSB_ENTRY_MASK].data.v = false;
    7774}
    7875
    … …  
    8582        as_t *as;
    8683        tsb_entry_t *tsb;
    87         size_t entry;
     84        tsb_entry_t *tte;
     85        size_t index;
    8886
    8987        as = t->as;
    90         entry = (t->page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK;
    91         ASSERT(entry < TSB_ENTRY_COUNT);
    92         tsb = &((tsb_entry_t *) PA2KA(as->arch.tsb_description.tsb_base))[entry];
     88        index = (t->page >> MMU_PAGE_WIDTH) & TSB_ENTRY_MASK;
     89       
     90        tsb = (tsb_entry_t *) PA2KA(as->arch.tsb_description.tsb_base);
     91        tte = &tsb[index];
    9392
    9493        /*
    … …  
    9897         */
    9998
    100         tsb->data.v = false;
     99        tte->data.v = false;
    101100
    102101        write_barrier();
    103102
    104         tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
     103        tte->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
    105104
    106         tsb->data.value = 0;
    107         tsb->data.nfo = false;
    108         tsb->data.ra = t->frame >> MMU_FRAME_WIDTH;
    109         tsb->data.ie = false;
    110         tsb->data.e = false;
    111         tsb->data.cp = t->c;    /* cp as cache in phys.-idxed, c as cacheable */
    112         tsb->data.cv = false;
    113         tsb->data.p = t->k;     /* p as privileged, k as kernel */
    114         tsb->data.x = true;
    115         tsb->data.w = false;
    116         tsb->data.size = PAGESIZE_8K;
     105        tte->data.value = 0;
     106        tte->data.nfo = false;
     107        tte->data.ra = t->frame >> MMU_FRAME_WIDTH;
     108        tte->data.ie = false;
     109        tte->data.e = false;
     110        tte->data.cp = t->c;    /* cp as cache in phys.-idxed, c as cacheable */
     111        tte->data.cv = false;
     112        tte->data.p = t->k;     /* p as privileged, k as kernel */
     113        tte->data.x = true;
     114        tte->data.w = false;
     115        tte->data.size = PAGESIZE_8K;
    117116       
    118117        write_barrier();
    119118       
    120         tsb->data.v = t->p;     /* v as valid, p as present */
     119        tte->data.v = t->p;     /* v as valid, p as present */
    121120}
    122121
    … …  
    130129        as_t *as;
    131130        tsb_entry_t *tsb;
    132         size_t entry;
     131        tsb_entry_t *tte;
     132        size_t index;
    133133
    134134        as = t->as;
    135         entry = (t->page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK;
    136         ASSERT(entry < TSB_ENTRY_COUNT);
    137         tsb = &((tsb_entry_t *) PA2KA(as->arch.tsb_description.tsb_base))[entry];
     135        index = (t->page >> MMU_PAGE_WIDTH) & TSB_ENTRY_MASK;
     136        tsb = (tsb_entry_t *) PA2KA(as->arch.tsb_description.tsb_base);
     137        tte = &tsb[index];
    138138
    139139        /*
    … …  
    143143         */
    144144
    145         tsb->data.v = false;
     145        tte->data.v = false;
    146146
    147147        write_barrier();
    148148
    149         tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
     149        tte->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
    150150
    151         tsb->data.value = 0;
    152         tsb->data.nfo = false;
    153         tsb->data.ra = t->frame >> MMU_FRAME_WIDTH;
    154         tsb->data.ie = false;
    155         tsb->data.e = false;
    156         tsb->data.cp = t->c;    /* cp as cache in phys.-idxed, c as cacheable */
     151        tte->data.value = 0;
     152        tte->data.nfo = false;
     153        tte->data.ra = t->frame >> MMU_FRAME_WIDTH;
     154        tte->data.ie = false;
     155        tte->data.e = false;
     156        tte->data.cp = t->c;    /* cp as cache in phys.-idxed, c as cacheable */
    157157#ifdef CONFIG_VIRT_IDX_DCACHE
    158         tsb->data.cv = t->c;
     158        tte->data.cv = t->c;
    159159#endif /* CONFIG_VIRT_IDX_DCACHE */
    160         tsb->data.p = t->k;     /* p as privileged, k as kernel */
    161         tsb->data.x = true;
    162         tsb->data.w = ro ? false : t->w;
    163         tsb->data.size = PAGESIZE_8K;
     160        tte->data.p = t->k;     /* p as privileged, k as kernel */
     161        tte->data.x = true;
     162        tte->data.w = ro ? false : t->w;
     163        tte->data.size = PAGESIZE_8K;
    164164       
    165165        write_barrier();
    166166       
    167         tsb->data.v = t->p;     /* v as valid, p as present */
     167        tte->data.v = t->p;     /* v as valid, p as present */
    168168}
    169169
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