Changeset e06ef614 in mainline for kernel/arch/amd64/src/asm.S
- Timestamp:
- 2010-11-02T20:10:30Z (14 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 49d819b4, efedee77
- Parents:
- 28f4adb (diff), e80329d6 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
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- 1 edited
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kernel/arch/amd64/src/asm.S
r28f4adb re06ef614 95 95 memcpy_from_uspace_failover_address: 96 96 memcpy_to_uspace_failover_address: 97 xor q %rax, %rax /* return 0, failure */97 xorl %eax, %eax /* return 0, failure */ 98 98 ret 99 99 … … 143 143 144 144 set_efer_flag: 145 mov q $0xc0000080, %rcx145 movl $0xc0000080, %ecx 146 146 rdmsr 147 147 btsl %edi, %eax … … 150 150 151 151 read_efer_flag: 152 mov q $0xc0000080, %rcx152 movl $0xc0000080, %ecx 153 153 rdmsr 154 154 ret … … 243 243 * Stop stack traces here if we came from userspace. 244 244 */ 245 xor q %rdx, %rdx245 xorl %edx, %edx 246 246 cmpq $(GDT_SELECTOR(KTEXT_DES)), ISTATE_OFFSET_CS(%rsp) 247 247 cmovnzq %rdx, %rbp … … 386 386 movq ISTATE_OFFSET_RSP(%rsp), %rsp 387 387 388 /* 389 * Clear the rest of the scratch registers to prevent information leak. 390 * The 32-bit XOR on the low GPRs actually clears the entire 64-bit 391 * register and the instruction is shorter. 392 */ 393 xorl %edx, %edx 394 xorl %esi, %esi 395 xorl %edi, %edi 396 xorq %r8, %r8 397 xorq %r9, %r9 398 xorq %r10, %r10 399 388 400 sysretq 389 401 … … 413 425 movq %rdi, %rsi 414 426 movq $(PA2KA(0xb8000)), %rdi /* base of EGA text mode memory */ 415 xor q %rax, %rax427 xorl %eax, %eax 416 428 417 429 /* Read bits 8 - 15 of the cursor address */ … … 493 505 movq $(PA2KA(0xb80a0)), %rsi 494 506 movq $(PA2KA(0xb8000)), %rdi 495 mov q $480, %rcx507 movl $480, %ecx 496 508 rep movsq 497 509 498 510 /* Clear the 24th row */ 499 xor q %rax, %rax500 mov q $20, %rcx511 xorl %eax, %eax 512 movl $20, %ecx 501 513 rep stosq 502 514
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