Changeset dff90fa7 in mainline for kernel/arch/ia32/src

Timestamp:

2013-06-05T19:41:12Z (13 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

74dcc07

Parents:

f288d85 (diff), 6db5d4b (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

mainline changes

Location:

kernel/arch/ia32/src

Files:

• boot/vesa_real.inc (modified) (3 diffs)
• cpu/cpu.c (modified) (1 diff)
• fpu_context.c (modified) (4 diffs)
• mm/page.c (modified) (2 diffs)
• pm.c (modified) (1 diff)

kernel/arch/ia32/src/boot/vesa_real.inc

@@ -31 +31 @@
 vesa_init:
         lidtl vesa_idtr
-        jmp $GDT_SELECTOR(VESA_INIT_DES), $vesa_init_real - vesa_init
+        
+        mov $GDT_SELECTOR(VESA_INIT_DATA_DES), %bx
+        
+        mov %bx, %es
+        mov %bx, %fs
+        mov %bx, %gs
+        mov %bx, %ds
+        mov %bx, %ss
+        
+        jmp $GDT_SELECTOR(VESA_INIT_CODE_DES), $vesa_init_real - vesa_init
 
 vesa_idtr:
@@ -39 +48 @@
 .code16
 vesa_init_real:
-        
         mov %cr0, %eax
         and $~1, %eax
@@ -45 +53 @@
         
         jmp $VESA_INIT_SEGMENT, $vesa_init_real2 - vesa_init
-        
+
 vesa_init_real2:
         mov $VESA_INIT_SEGMENT, %bx

kernel/arch/ia32/src/cpu/cpu.c

@@ -115 +115 @@
                         "mov %[help], %%cr4\n"
                         : [help] "+r" (help)
-                        : [mask] "i" (CR4_OSFXSR_MASK | (1 << 10))
+                        : [mask] "i" (CR4_OSFXSR_MASK | CR4_OSXMMEXCPT_MASK)
                 );
         }
-
+        
 #ifndef PROCESSOR_i486
         if (CPU->arch.fi.bits.sep) {

kernel/arch/ia32/src/fpu_context.c

@@ -27 +27 @@
  */
 
-/** @addtogroup ia32    
+/** @addtogroup ia32
  * @{
  */
@@ -37 +37 @@
 #include <arch.h>
 #include <cpu.h>
-
 
 /** x87 FPU scr values (P3+ MMX2) */
@@ -60 +59 @@
         X87_DENORMAL_EXC_FLAG = (1 << 1),
         X87_INVALID_OP_EXC_FLAG = (1 << 0),
-
+        
         X87_ALL_MASK = X87_PRECISION_MASK | X87_UNDERFLOW_MASK | X87_OVERFLOW_MASK | X87_ZERO_DIV_MASK | X87_DENORMAL_OP_MASK | X87_INVALID_OP_MASK,
 };
 
-
 typedef void (*fpu_context_function)(fpu_context_t *fctx);
 
-static fpu_context_function fpu_save, fpu_restore;
+static fpu_context_function fpu_save;
+static fpu_context_function fpu_restore;
 
 static void fpu_context_f_save(fpu_context_t *fctx)
@@ -104 +103 @@
 void fpu_fxsr(void)
 {
-        fpu_save=fpu_context_fx_save;
-        fpu_restore=fpu_context_fx_restore;
+        fpu_save = fpu_context_fx_save;
+        fpu_restore = fpu_context_fx_restore;
 }
 

kernel/arch/ia32/src/mm/page.c

@@ -84 +84 @@
 void page_fault(unsigned int n __attribute__((unused)), istate_t *istate)
 {
-        uintptr_t page;
+        uintptr_t badvaddr;
         pf_access_t access;
         
-        page = read_cr2();
+        badvaddr = read_cr2();
                 
         if (istate->error_word & PFERR_CODE_RSVD)
@@ -97 +97 @@
                 access = PF_ACCESS_READ;
         
-        if (as_page_fault(page, access, istate) == AS_PF_FAULT) {
-                fault_if_from_uspace(istate, "Page fault: %#x.", page);
-                panic_memtrap(istate, access, page, NULL);
-        }
+        (void) as_page_fault(badvaddr, access, istate);
 }
 

kernel/arch/ia32/src/pm.c

@@ -75 +75 @@
         /* VESA Init descriptor */
 #ifdef CONFIG_FB
-        { 0xffff, 0, VESA_INIT_SEGMENT >> 12, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 0, 0, 0 }
+        { 0xffff, 0, VESA_INIT_SEGMENT >> 12, AR_PRESENT | AR_CODE | AR_READABLE | DPL_KERNEL, 0xf, 0, 0, 0, 0, 0 },
+        { 0xffff, 0, VESA_INIT_SEGMENT >> 12, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, 0xf, 0, 0, 0, 0, 0 }
 #endif
 };