Index: boot/arch/arm32/src/mm.c
===================================================================
--- boot/arch/arm32/src/mm.c	(revision b80d132402ab3e047769aa6169f32b1a76c36aa1)
+++ boot/arch/arm32/src/mm.c	(revision df334cafb6079da76f94d74a1dfd100644bddde8)
@@ -136,20 +136,10 @@
 		"mrc p15, 0, r0, c1, c0, 0\n"
 		
-#if defined(PROCESSOR_cortex_a8) | defined(MACHINE_gta02)
-		/* Mask to enable paging, I-cache D-cache and branch predict
-		 * See kernel/arch/arm32/include/regutils.h for bit values.
-		 * It's safe because Cortex-A8 implements IVIPT extension
-		 * See Cortex-A8 TRM ch. 7.2.6 p. 7-4 (PDF 245).
-		 * It's safe for gta02 too because we turn the caches off
-		 * before switching to kernel. */
-		"ldr r1, =0x00001801\n"
-#elif defined(PROCESSOR_ARCH_armv7_a) | defined(PROCESSOR_ARCH_armv6)
-		/* Enable paging, data cache and branch prediction
-		 * see arch/arm32/src/cpu/cpu.c for reasoning */
-		"ldr r1, =0x00000805\n"
-#else
-		/* Mask to enable paging */
-		"ldr r1, =0x00000001\n"
-#endif
+		/* Enable ICache, DCache, BPredictors and MMU,
+		 * we disable caches before jumping to kernel
+		 * so this is safe for all archs.
+		 */
+		"ldr r1, =0x00001805\n"
+		
 		"orr r0, r0, r1\n"